Hi Dongjiu Geng,
On 09/06/18 13:40, Marc Zyngier wrote:
> On Fri, 08 Jun 2018 20:48:40 +0100, Dongjiu Geng wrote:
>> For the migrating VMs, user space may need to know the exception
>> state. For example, in the machine A, KVM make an SError pending,
>> when migrate to B, KVM also needs to pend an
Hi Dongjiu Geng,
Please only put 'RESEND' in the subject if the patch content is identical.
This patch is not the same as v4.
On 08/06/18 20:48, Dongjiu Geng wrote:
> For the migrating VMs, user space may need to know the exception
> state. For example, in the machine A, KVM make an SError pendin
Hi Suzuki,
Nit: KVM in the subject line?
On 27/03/18 14:15, Suzuki K Poulose wrote:
> Add a helper to convert ID_AA64MMFR0_EL1:PARange to they physical
> size shift. Limit the size to the maximum supported by the kernel.
> We are about to move the user of this code and this helps to
> keep the ch
Hi Suzuki,
On 27/03/18 14:15, Suzuki K Poulose wrote:
> We set VTCR_EL2 very early during the stage2 init and don't
> touch it ever. This is fine as we had a fixed IPA size. This
> patch changes the behavior to set the VTCR for a given VM,
> depending on its stage2 table. The common configuration
Hi Alex,
(I haven't read through all this yet, just on this one:)
On 04/19/2018 03:57 PM, Alex G. wrote:
> Maybe it's better move the AER handling to NMI/IRQ context, since
> ghes_handle_aer() is only scheduling the real AER andler, and is irq
> safe. I'm scratching my head about why we're messi
Hi Alex,
On 04/16/2018 10:59 PM, Alex G. wrote:
> On 04/13/2018 11:38 AM, James Morse wrote:
>> This assumes a cache-invalidate will clear the error, which I don't
think we're
>> guaranteed on arm.
>> It also destroys any adjacent data, "everyone's
Hi Alex,
On 09/04/18 19:11, Alex G. wrote:
> On 04/06/2018 01:24 PM, James Morse wrote:
> Do you have any ETA on when your SEA patches are going to make it
> upstream? There's not much point in updating my patchset if it's going
> to conflict with your work.
The
Hi York,
You have a DT binding in here, please CC the devicetree list. You're touching
code under arch/arm64, so you need the arm list too. get_maintainer.pl will take
your patch and give you the list of which lists and maintainers to CC.
(I've added those lists, the full patch is here:
https://p
Hi gengdongjiu,
On 26/02/18 16:13, gengdongjiu wrote:
> 2018-02-24 1:58 GMT+08:00 James Morse :
>> On 22/02/18 18:02, Dongjiu Geng wrote:
>>> The RAS SError Syndrome can be Implementation-Defined,
>>> arm64_is_ras_serror() is used to judge whether it is RAS SError,
Hi Dongjiu Geng,
On 03/03/18 16:09, Dongjiu Geng wrote:
> Export one API to specify virtual SEI syndrome value
> for guest, and add a helper to get the VSESR_EL2 value.
This patch adds two helpers that nothing calls... its not big, please merge it
with the patch that uses these.
> diff --git a/
Hi Dongjiu Geng,
On 03/03/18 16:09, Dongjiu Geng wrote:
> RAS Extension provides VSESR_EL2 register to specify
> virtual SError syndrome value, this patch adds a new
> IOCTL to export user-invisible states related to
> SError exceptions. User space can setup the
> kvm_vcpu_events to inject specifi
Hi Dongjiu Geng,
On 03/03/18 16:09, Dongjiu Geng wrote:
> Before user space injects a SError, it needs to know whether it can
> specify the guest Exception Syndrome, so KVM should tell user space
> whether it has such capability.
> diff --git a/Documentation/virtual/kvm/api.txt
> b/Documentation
Hi gengdongjiu,
On 08/03/18 06:18, gengdongjiu wrote:
> Hi James,
>sorry for my late response due to chines new year.
Happy new year,
> 2018-02-16 1:55 GMT+08:00 James Morse :
>> On 12/02/18 10:19, gengdongjiu wrote:
>>> On 2018/2/10 1:44, James Morse wrote:
>&
Hi Tyler,
On 05/01/17 22:31, Baicar, Tyler wrote:
> On 12/20/2016 8:29 AM, James Morse wrote:
>> On 07/12/16 21:48, Tyler Baicar wrote:
>>> ARM APEI extension proposal added SEA (Synchrounous External
>>> Abort) notification type for ARMv8.
>>> Add a new GHE
Hi Tyler,
On 16/01/17 11:53, Will Deacon wrote:
> On Thu, Jan 12, 2017 at 11:15:18AM -0700, Tyler Baicar wrote:
>> SEA exceptions are often caused by an uncorrected hardware
>> error, and are handled when data abort and instruction abort
>> exception classes have specific values for their Fault St
Hi Tyler,
On 12/01/17 18:15, Tyler Baicar wrote:
> SEA exceptions are often caused by an uncorrected hardware
> error, and are handled when data abort and instruction abort
> exception classes have specific values for their Fault Status
> Code.
> When SEA occurs, before killing the process, go thr
Hi Tyler,
On 12/01/17 18:15, Tyler Baicar wrote:
> ARM APEI extension proposal added SEA (Synchrounous External
Nit: Synchronous
> Abort) notification type for ARMv8.
> Add a new GHES error source handling function for SEA. If an error
> source's notification type is SEA, then this function can
Hi Tyler,
On 18/01/17 23:51, Baicar, Tyler wrote:
> On 1/18/2017 7:50 AM, James Morse wrote:
>> On 12/01/17 18:15, Tyler Baicar wrote:
>>> ARM APEI extension proposal added SEA (Synchrounous External
>>> Abort) notification type for ARMv8.
>>> Add a new GHES er
Hi Tyler,
On 20/01/17 20:58, Baicar, Tyler wrote:
> On 1/19/2017 10:57 AM, James Morse wrote:
>> On 18/01/17 23:51, Baicar, Tyler wrote:
>>> On 1/18/2017 7:50 AM, James Morse wrote:
>>>> On 12/01/17 18:15, Tyler Baicar wrote:
>>>>> diff --git a/driver
Hi Tyler,
On 18/01/17 23:26, Baicar, Tyler wrote:
> On 1/17/2017 3:31 AM, James Morse wrote:
>> On 12/01/17 18:15, Tyler Baicar wrote:
>>> SEA exceptions are often caused by an uncorrected hardware
>>> error, and are handled when data abort and instruction abort
Hi Tyler,
On 20/01/17 20:35, Baicar, Tyler wrote:
> On 1/19/2017 10:55 AM, James Morse wrote:
>> On 18/01/17 23:26, Baicar, Tyler wrote:
>>> On 1/17/2017 3:31 AM, James Morse wrote:
>>>> On 12/01/17 18:15, Tyler Baicar wrote:
>>>>> +info.si_addr =
Hi Yury,
[CC: Andy Gross]
On 29/01/17 12:21, Yury Norov wrote:
> On Sun, Jan 29, 2017 at 03:42:55PM +0530, Yury Norov wrote:
>> Hi all,
>>
>> I pulled next-20170125 kernel, and found it hanged on boot. The exact reason
>> is
>> panic on dereferencing of the 0xffc8 address, which is most prob
Hi Rafael,
On 07/07/16 01:33, Rafael J. Wysocki wrote:
> Below is my sort of version of this (untested) and I did it this way, because
> the issue is specific to resume from hibernation (the workaround need not be
> applied anywhere else) and the hibernate_resume_nonboot_cpu_disable() thing
> may
Hi,
On 07/07/16 03:50, Chen, Yu C wrote:
>> From: Rafael J. Wysocki [mailto:r...@rjwysocki.net]
>> Below is my sort of version of this (untested) and I did it this way,
>> because the
>> issue is specific to resume from hibernation (the workaround need not be
>> applied anywhere else) and the hib
Hi Mark,
On 15/06/16 18:04, Mark Rutland wrote:
> If the toolchain does not support -fsanitize-coverage=trace-pc, we blat
> this option from CFLAGS_KCOV, and build the kernel without
> instrumentation, even if CONFIG_KCOV was selected. However, we still
> build the rest of the kcov infrastructure,
;> Any ideas?
>> According to Dmitry (thanks, Dmitry!) this has regressed recently, but
>> there's a pending patch that should probably fix the problem:
>> http://lkml.iu.edu/hypermail/linux/kernel/1605.2/04379.html
>
> Thanks for the pointer! With that applied, the program runs.
>
> However, it looks like I missed a warning from the kernel build system,
> and my toolchain doesn't actually support -fsanitize-coverage=trace-pc,
> so I'm not going to be able to test that further.
I dusted off a compiler that supports this, and ran the sample program under
Documentation with the above unproxify patch.
Tested-by: James Morse
Thanks,
James
if (hest_hdr->type != ACPI_HEST_TYPE_GENERIC_ERROR &&
> + hest_hdr->type != ACPI_HEST_TYPE_GENERIC_ERROR_V2)
> return 0;
>
> if (!((struct acpi_hest_generic *)hest_hdr)->enabled)
> diff --git a/include/acpi/ghes.h b/include/acpi/ghes.h
> index 720446c..68f088a 100644
> --- a/include/acpi/ghes.h
> +++ b/include/acpi/ghes.h
> @@ -13,7 +13,10 @@
> #define GHES_EXITING 0x0002
>
> struct ghes {
> - struct acpi_hest_generic *generic;
> + union {
> + struct acpi_hest_generic *generic;
> + struct acpi_hest_generic_v2 *generic_v2;
> + };
> struct acpi_hest_generic_status *estatus;
> u64 buffer_paddr;
> unsigned long flags;
>
Looks good to me, for what its worth:
Reviewed-by: James Morse
Thanks,
James
ct acpi_hest_generic_data_v300 *)(gdata)) + 1) :
> + gdata + 1;
> +}
> diff --git a/include/linux/cper.h b/include/linux/cper.h
> index dcacb1a..13ea41c 100644
> --- a/include/linux/cper.h
> +++ b/include/linux/cper.h
> @@ -255,6 +255,18 @@ enum {
>
> #define CPER_PCIE_SLOT_SHIFT 3
>
> +#define acpi_hest_generic_data_error_length(gdata) \
> + (((struct acpi_hest_generic_data *)(gdata))->error_data_length)
> +#define acpi_hest_generic_data_size(gdata) \
> + ((acpi_hest_generic_data_version(gdata) >= 3) ? \
> + sizeof(struct acpi_hest_generic_data_v300) :\
> + sizeof(struct acpi_hest_generic_data))
> +#define acpi_hest_generic_data_record_size(gdata)\
> + (acpi_hest_generic_data_size(gdata) + \
> + acpi_hest_generic_data_error_length(gdata))
> +#define acpi_hest_generic_data_next(gdata) \
> + ((void *)(gdata) + acpi_hest_generic_data_record_size(gdata))
> +
How come these aren't in ghes.h?
Reviewed-by: James Morse
Thanks,
James
Hi Tyler,
On 21/11/16 22:35, Tyler Baicar wrote:
> Add support for ARMv8 Common Platform Error Record (CPER).
> UEFI 2.6 specification adds support for ARMv8 specific
> processor error information to be reported as part of the
> CPER records. This provides more detail on for processor error logs.
Hi Tyler,
On 07/12/16 21:48, Tyler Baicar wrote:
> ARM APEI extension proposal added SEA (Synchrounous External
> Abort) notification type for ARMv8.
> Add a new GHES error source handling function for SEA. If an error
> source's notification type is SEA, then this function can be registered
> int
e));
out:
%<----
I can post it as a separate fixes patch if you prefer.
I also tested kexec. FWIW:
Tested-by: James Morse
Thanks,
James
[0] Trace
[4.191607] Freezing user space processes ... (elapsed 0.000 seconds) done.
[4.224251] random: fast init d
Hi Robert, Will,
On 01/12/16 16:45, Will Deacon wrote:
> On Wed, Nov 30, 2016 at 07:21:31PM +0100, Robert Richter wrote:
>> On ThunderX systems with certain memory configurations we see the
>> following BUG_ON():
>>
>> kernel BUG at mm/page_alloc.c:1848!
>>
>> This happens for some configs with 6
Hi Robert,
On 02/12/16 07:11, Robert Richter wrote:
> On 01.12.16 17:26:55, James Morse wrote:
>> On 01/12/16 16:45, Will Deacon wrote:
>>> Thanks for sending out the new patch. Whilst I'm still a bit worried about
>>> changing pfn_valid like this, I guess we&#x
ds to a later BUG_ON().
These patches make hibernate's savable_page() take its escape route
via 'if (PageReserved(page) && pfn_is_nosave(pfn))'.
[0] https://lkml.org/lkml/2016/11/30/566
James Morse (2):
arm64: mm: Mark nomap regions with the PG_reserved flag
map pages.
Add the memblock nomap regions to the ranges reported as being
'pfn_nosave' to the hibernate core code. This only works if all
pages in the nomap region are also marked with PG_reserved.
Signed-off-by: James Morse
---
arch/arm64/kernel/hibernate.c | 6 +-
1 file ch
struct pages in the nomap regions.
This gives pfn walkers the necessary hint that the page might not
be accessible, allowing pfn_valid()s meaning to change slightly.
Signed-off-by: James Morse
---
arch/arm64/mm/init.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/a
r error logs.
Looks good to me, a few minor comments below.
Reviewed-by: James Morse
> diff --git a/drivers/firmware/efi/cper.c b/drivers/firmware/efi/cper.c
> index 8fa4e23..1ac2572 100644
> --- a/drivers/firmware/efi/cper.c
> +++ b/drivers/firmware/efi/cper.c
> @@ -18
Hi,
On 21/03/17 06:32, gengdongjiu wrote:
> On 2017/3/20 23:08, James Morse wrote:
>> On 20/03/17 13:58, Marc Zyngier wrote:
>>> On 20/03/17 12:28, gengdongjiu wrote:
>>>> On 2017/3/20 19:24, Marc Zyngier wrote:
>>>>> On 20/03/17 07:55, Dongjiu
Hi Christoffer,
On 21/03/17 11:34, Christoffer Dall wrote:
> On Tue, Mar 21, 2017 at 02:32:29PM +0800, gengdongjiu wrote:
>> On 2017/3/20 23:08, James Morse wrote:
>>>>>> On 20/03/17 07:55, Dongjiu Geng wrote:
>>>>>>> In the RAS implementation
Hi Wang Xiongfeng,
On 22/03/17 02:46, Xiongfeng Wang wrote:
>> Guests are a special case as QEMU may never access the faulty memory itself,
>> so
>> it won't receive the 'late' signal. It looks like ARM/arm64 KVM lacks support
>> for KVM_PFN_ERR_HWPOISON which sends SIGBUS from KVM's fault-handli
Hi gengdongjiu
On 22/03/17 13:37, gengdongjiu wrote:
> On 2017/3/21 21:10, James Morse wrote:
>> On 21/03/17 06:32, gengdongjiu wrote:
>>> so for both SEA and SEI, do you prefer to below steps?
>>> EL0/EL1 SEI/SEA ---> EL3 firmware first handle --> EL2 hyperv
Hi Punit,
On 01/02/17 21:38, Tyler Baicar wrote:
> From: "Jonathan (Zhixiong) Zhang"
>
> If ACPI_APEI and MEMORY_FAILURE is configured, select
> ACPI_APEI_MEMORY_FAILURE. This enables memory failure recovery
> when such memory failure is reported through ACPI APEI. APEI
> (ACPI Platform Error In
Hi Dongjiu Geng,
On 23/03/17 13:01, Dongjiu Geng wrote:
> when the pfn is KVM_PFN_ERR_HWPOISON, it indicates to send
> SIGBUS signal from KVM's fault-handling code to qemu, qemu
> can handle this signal according to the fault address.
I'm afraid I beat you to it on this one:
https://www.spinics.n
Hi Tyler,
On 06/03/17 20:44, Tyler Baicar wrote:
> ARM APEI extension proposal added SEA (Synchronous External Abort)
> notification type for ARMv8.
> Add a new GHES error source handling function for SEA. If an error
> source's notification type is SEA, then this function can be registered
> into
Hi Xie XiuQi,
On 20/03/17 07:48, Xie XiuQi wrote:
> On 2017/3/14 17:45, James Morse wrote:
>> On 08/03/17 04:09, Xie XiuQi wrote:
>>> Add ghes handling for SEI so that the host kernel could parse and
>>> report detailed error information for SEI which occur in the guest
Hi Dongjiu Geng,
On 20/03/17 13:58, Marc Zyngier wrote:
> On 20/03/17 12:28, gengdongjiu wrote:
>> On 2017/3/20 19:24, Marc Zyngier wrote:
>>> Please include James Morse on anything RAS related, as he's already
>>> looking at related patches.
(Thanks Marc,)
>
ster/notifier code.Rename the list and notifier
> to show this is no longer just SCI, but anything from the
> Hardware Error Device.
Reviewed-by: James Morse
... what looks like an existing bug:
> diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
> index b192b42..fd3
EA, the platform analyzes
> + and handles hardware error notifications from SEA, and it may then
> + form a HW error record for the OS to parse and handle. This
> + option allows the OS to look for such hardware error record, and
> + take appropriate action.
> +
> config ACPI_APEI_MEMORY_FAILURE
> bool "APEI memory error recovering support"
> depends on ACPI_APEI && MEMORY_FAILURE
Reviewed-by: James Morse
Thanks,
James
Hi Tyler,
On 06/03/17 20:44, Tyler Baicar wrote:
> When a memory error, CPU error, PCIe error, or other type of hardware error
> that's covered by RAS occurs, firmware should populate the shared GHES memory
> location with the proper GHES structures to notify the OS of the error.
> For example, pl
Hi Tyler,
On 06/03/17 20:45, Tyler Baicar wrote:
> Currently external aborts are unsupported by the guest abort
> handling. Add handling for SEAs so that the host kernel reports
> SEAs which occur in the guest kernel.
> diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
On 07/03/17 17:58, Baicar, Tyler wrote:
> On 3/7/2017 4:48 AM, James Morse wrote:
>> On 06/03/17 20:45, Tyler Baicar wrote:
>>> Currently external aborts are unsupported by the guest abort
>>> handling. Add handling for SEAs so that the host kernel reports
>>>
Hi!
On 03/01/17 06:34, Rajat Jain wrote:
> Add code to actually configure the L1 substate settigns on the
> upstream and downstream device, while taking care of the rules
> dictated by the PCIe spec.
While testing hibernate on an arm64 juno with v4.11-rc1, I get a NULL pointer
dereference from pc
Hi guys,
On 08/03/17 23:08, Rajat Jain wrote:
> On Wed, Mar 8, 2017 at 2:39 PM, Bjorn Helgaas wrote:
>> On Wed, Mar 08, 2017 at 06:44:36PM +0000, James Morse wrote:
>>> On 03/01/17 06:34, Rajat Jain wrote:
>>>> Add code to actually configure the L1 substate set
Hi Shiju,
On 07/03/17 16:07, Shiju Jose wrote:
> Add common handler in ghes for HW errors notified via hed(PNP0C33) driver.
> 1. Rename ghes_notify_sci() to ghes_notify_hed().
> 2. Rename struct notifier_block ghes_notifier_sci to
>struct notifier_block ghes_notifier_hed.
> 3. Rename ghes_sci
Hi Xie XiuQi,
On 08/03/17 04:09, Xie XiuQi wrote:
> Add ghes handling for SEI so that the host kernel could parse and
> report detailed error information for SEI which occur in the guest
> kernel.
How does this interact with Synchronous External Abort as a notify method?
Both of these take the in
Hi Xie XiuQi,
On 03/03/17 10:39, Xie XiuQi wrote:
> ARM APEI extension proposal added SEI (asynchronous SError interrupt)
> notification type for ARMv8.
>
> Add a new GHES error source handling function for SEI. In firmware
> first mode, if an error source's notification type is SEI. Then GHES
>
Hi Tyler,
On 28/02/17 19:43, Baicar, Tyler wrote:
> On 2/24/2017 3:42 AM, James Morse wrote:
>> On 21/02/17 21:22, Tyler Baicar wrote:
>>> Currently external aborts are unsupported by the guest abort
>>> handling. Add handling for SEAs so that the host kernel reports
On 16/06/16 17:36, Alexander Potapenko wrote:
> On Thu, Jun 16, 2016 at 6:32 PM, Mark Rutland wrote:
>> On Thu, Jun 16, 2016 at 05:25:31PM +0100, Catalin Marinas wrote:
>>> I noticed that there was an ack on v1 form Marc Z that's missing in v2.
>>
>> I believe Marc's reply [1] was to v3 [2], it's
fx,
Nit: please use the "%s""section... that this file consistently uses. This means
this code will still work as expected when someone adds '%ss' support to printk!
> + gdata->error_data_length);
> + print_hex_dump(newpfx, "", DUMP_PREFIX_OFFSET, 16, 4,
> +unknown_err, gdata->error_data_length, 0);
> + }
>
> return;
FWIW:
Reviewed-by: James Morse
Thanks,
James
On 22/02/17 01:12, Russell King - ARM Linux wrote:
> On Tue, Feb 21, 2017 at 07:10:11PM +0000, James Morse wrote:
>> Hi Tyler,
>>
>> On 15/02/17 19:51, Tyler Baicar wrote:
>>> + } else {
>>> + const void *unknown_err;
>>> +
>>>
Hi Tyler,
On 21/02/17 21:22, Tyler Baicar wrote:
> Currently external aborts are unsupported by the guest abort
> handling. Add handling for SEAs so that the host kernel reports
> SEAs which occur in the guest kernel.
> diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
Hi Prasad,
On 15/02/17 05:52, Sodagudi Prasad wrote:
> When any sys call is made from user space orig_addr_limit will be zero and
> after
> that driver is calling set_fs(KERNEL_DS) and then copy_to_user() to user
> space
> memory.
Don't do this, its exactly the case PAN+UAO and the code you p
Hi Tyler,
On 13/02/17 22:45, Baicar, Tyler wrote:
> On 2/9/2017 3:48 AM, James Morse wrote:
>> On 01/02/17 17:16, Tyler Baicar wrote:
>>> From: "Jonathan (Zhixiong) Zhang"
>>>
>>> Even if an error status block's severity is fatal, the ker
Hi Prasad,
On 15/02/17 21:12, Sodagudi Prasad wrote:
> On 2017-02-15 04:09, James Morse wrote:
>> On 15/02/17 05:52, Sodagudi Prasad wrote:
>>> that driver is calling set_fs(KERNEL_DS) and then copy_to_user() to user
>>> space
>>> memory.
>>
>>
Hi Stephen,
On 17/02/17 01:19, Stephen Boyd wrote:
> If a page is marked read only we should print out that fact,
> instead of printing out that there was a page fault. Right now we
> get a cryptic error message that something went wrong with an
> unhandled fault, but we don't evaluate the esr to
Hi Stephen,
On 17/02/17 15:53, Stephen Boyd wrote:
> Quoting James Morse (2017-02-17 03:00:39)
>> On 17/02/17 01:19, Stephen Boyd wrote:
>>> diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
>>> index 156169c6981b..8bd4e7f11c70 100644
>>> --- a/arch/a
Hi Wang Xiongfeng,
On 25/02/17 07:15, Xiongfeng Wang wrote:
> On 2017/2/22 5:22, Tyler Baicar wrote:
>> Currently external aborts are unsupported by the guest abort
>> handling. Add handling for SEAs so that the host kernel reports
>> SEAs which occur in the guest kernel.
>> diff --git a/arch/arm
Hi,
On 28/02/17 06:25, Xiongfeng Wang wrote:
> On 2017/2/27 21:58, James Morse wrote:
>> On 25/02/17 07:15, Xiongfeng Wang wrote:
>>> Can we inject an sea into the guest, so that the guest can kill the
>>> application which causes the error if the guest won't be te
->generic, ghes->estatus);
> }
> + if (ghes_severity(ghes->estatus->error_severity) >= GHES_SEV_PANIC) {
> + __ghes_call_panic();
> + }
> +
I think this ghes_severity() then panic() should go above the:
> if (!ghes_estatus_cached(ghes->estatus)) {
and we should call __ghes_print_estatus() here too, to make sure the message
definitely got out!
With that,
Reviewed-by: James Morse
Thanks,
James
t; error (translation table walk)" },
> + { do_sea, SIGBUS, 0, "level 0 synchronous
> parity error (translation table walk)" },
> + { do_sea, SIGBUS, 0, "level 1 synchronous
> parity error (translation table walk)" },
> + { do_sea, SIGBUS, 0, "level 2 synchronous
> parity error (translation table walk)" },
> + { do_sea, SIGBUS, 0, "level 3 synchronous
> parity error (translation table walk)" },
> { do_bad, SIGBUS, 0, "unknown 32"
> },
> { do_alignment_fault, SIGBUS, BUS_ADRALN,"alignment fault"
> },
> { do_bad, SIGBUS, 0, "unknown 34"
> },
>
With the ESR_ELx_FnV change above,
Reviewed-by: James Morse
Thanks,
James
Hi Tyler,
On 01/02/17 17:16, Tyler Baicar wrote:
> ARM APEI extension proposal added SEA (Synchronous External Abort)
> notification type for ARMv8.
> Add a new GHES error source handling function for SEA. If an error
> source's notification type is SEA, then this function can be registered
> into
_exit)
>
> add x1, x10, #PAGE_SIZE
> /* Clean the copied page to PoU - based on flush_icache_range() */
> - dcache_line_size x2, x3
> + raw_dcache_line_size x2, x3
> sub x3, x2, #1
> bic x4, x10, x3
> 2: dc cvau, x4/* clean D line / unified line */
Looks like no-change to me!
If you think you need it:
Acked-by: James Morse
Thanks,
James
Hi David,
On 09/03/16 05:32, David Long wrote:
> From: "David A. Long"
>
> Add HAVE_REGS_AND_STACK_ACCESS_API feature for arm64.
>
> Signed-off-by: David A. Long
> diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
> index ff7f132..efebf0f 100644
> --- a/arch/arm64/kernel/pt
Hi Guenter,
On 14/03/16 14:37, Guenter Roeck wrote:
> To give people an idea what to expect in the merge window, here are my current
> build and runtime test results. Some of the runtime failures are due to the
> newly introduced i2c bug, but many (including the arm64 boot failures) have
> been ar
Hi Peter!
On 11/01/16 16:25, Peter Zijlstra wrote:
> Like enable_on_exec, perf_event_enable() event scheduling has problems
> respecting the context hierarchy when trying to schedule events (for
> example, it will try and add a pinned event without first removing
> existing flexible events).
>
>
On 08/03/16 10:26, Peter Zijlstra wrote:
> In any case, please try -rc6, which includes:
Bother, I should have thought to test with the later rcs, I foolishly stopped
with rc5.
> a096309bc467 perf: Fix scaling vs. perf_install_in_context()
> bd2afa49d194 perf: Fix scaling vs. perf_event_enabl
Hi Pratyush,
On 18/03/16 13:29, Pratyush Anand wrote:
> Probably, I can see why does not it work. So, when we are single stepping an
> instruction and page fault occurs, we will come to el1_da in entry.S. Here, we
> do enable_dbg. As soon as we will do this, we will start receiving single step
> e
Hi!
On 10/02/16 18:12, Shi, Yang wrote:
> On 2/10/2016 4:10 AM, Will Deacon wrote:
>> On Wed, Feb 10, 2016 at 11:52:31AM +0000, James Morse wrote:
>>> On 10/02/16 10:29, Will Deacon wrote:
>>>> On Tue, Feb 09, 2016 at 01:26:22PM -0800, Yang Shi wrote:
>>>>
k_ptr = IRQ_STACK_PTR(smp_processor_id());
> + else
> + irq_stack_ptr = 0;
> +
> pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk);
>
> if (!tsk)
>
Neither file includes 'linux/preempt.h' for the definition of preemptible().
(I can't talk: I should have included smp.h for smp_processor_id())
Acked-by: James Morse
Tested-by: James Morse
Thanks!
James
Hi Will,
On 16/09/15 12:25, Will Deacon wrote:
> On Sun, Sep 13, 2015 at 03:42:17PM +0100, Jungseok Lee wrote:
>> diff --git a/arch/arm64/include/asm/thread_info.h
>> b/arch/arm64/include/asm/thread_info.h
>> index dcd06d1..44839c0 100644
>> --- a/arch/arm64/include/asm/thread_info.h
>> +++ b/arc
On 18/09/15 13:57, Jungseok Lee wrote:
> On Sep 18, 2015, at 1:21 AM, Catalin Marinas wrote:
>> in more detail. BTW, I don't think we need the any count for the irq
>> stack as we don't re-enter the same IRQ stack.
>
> Another interrupt could come in since IRQ is enabled when handling softirq
> ac
Hi Jungseok Lee,
I gave this a go on a Juno board, while generating usb/network interrupts:
Tested-by: James Morse
On 13/09/15 15:42, Jungseok Lee wrote:
> Currently, kernel context and interrupts are handled using a single
> kernel stack navigated by sp_el1. This forces many systems
>
> The series is also available here :
>
> git://linux-arm.org/linux-skp.git cpu-ftr/v1-4.3-rc1
Hi Suzuki,
I gave your branch a spin on some insane combinations with a fast-model -
testing PAN only got enabled when all cores supported it.
Tested-by: James Morse
Thanks,
James
--
T
Hi Ard!
On 30/12/15 15:26, Ard Biesheuvel wrote:
> Since the early fixmap page tables are populated using pages that are
> part of the static footprint of the kernel, they are covered by the
> initial kernel mapping, and we can refer to them without using __va/__pa
> translations, which are tied t
Hi Salil,
On 07/07/2020 10:52, Salil Mehta wrote:
>> From: Salil Mehta
Disambiguation: by cpu-hotplug here, you don't mean
CONFIG_HOTPLUG_CPU backed by PSCI, which is commonly what we mean in the arm
world. You
mean: package hot-add. A bunch of CPUs (and maybe more) that weren't present at
boo
The comment in rdtgroup_init() refers to the non existent function
rdt_mount(), which has now been renamed rdt_get_tree(). Fix the
comment.
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
---
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
max_delay is used by x86's __get_mem_config_intel() as a local variable.
Remove it, replacing it with a local variable.
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
---
arch/x86/kernel/cpu/resctrl/core.c | 8
arch/x86/kernel/cpu/resctrl/internal.h | 3 ---
2
Nothing reads struct mbm_states's chunks_bw value, its a copy of
chunks. Remove it.
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
---
arch/x86/kernel/cpu/resctrl/internal.h | 2 --
arch/x86/kernel/cpu/resctrl/monitor.c | 3 +--
2 files changed, 1 insertion(+), 4 deletions(-)
lore.kernel.org/lkml/20200430170400.21501-1-james.mo...@arm.com/
[v1] https://lore.kernel.org/lkml/20200214182401.39008-1-james.mo...@arm.com/
James Morse (10):
x86/resctrl: Nothing uses struct mbm_state chunks_bw
x86/resctrl: Remove max_delay
x86/resctrl: Fix stale comment
x86/resctrl: u
is harmless
as rdtgroup_mkdir() tests these capable flags before allowing the config
directories to be created.
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
---
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 30 --
1 file changed, 14 insertions(+), 16 deletions
intel_cacheinfo.c,
name it get_cpu_cacheinfo_id() to show its relation with
get_cpu_cacheinfo().
Now this is visible on other architectures, check the id attribute
has actually been set.
Signed-off-by: James Morse
Reviewed-by: Babu Moger
Reviewed-by: Reinette Chatre
---
arch/x86/kernel/cpu/resctrl
mains"
error message for affected platforms.
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
Reviewed-by: Babu Moger
---
An alternative to this is for Intel non-linear MBA resources to
clear alloc_capable as they can't be configured anyway.
---
arch/x86/kernel/cpu/resctrl/co
mbm_handle_overflow() and cqm_handle_limbo() are both provided with
the domain's work_struct when called, but use get_domain_from_cpu()
to find the domain, along with the appropriate error handling.
container_of() saves some list walking and bitmap testing, use that
instead.
Signed-off-by:
We are about to disturb the header soup. This header uses struct pid
and struct pid_namespace. Include their header.
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
---
include/linux/resctrl.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/resctrl.h b/include/linux
est
needed for Haswell, but as it always sets this value to 1, it will
never match.
Signed-off-by: James Morse
Reviewed-by: Babu Moger
Reviewed-by: Reinette Chatre
---
arch/x86/kernel/cpu/resctrl/core.c| 14
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 39 ++-
Removing this duplication means user-space visible behaviour and
error messages are not validated or generated in different places.
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
Reviewed-by : Babu Moger
---
arch/x86/kernel/cpu/resctrl/core.c| 3 +-
arch/x86/kernel/cpu/resctrl/ctr
Hi Shiju,
On 15/06/2020 10:53, Shiju Jose wrote:
> Add support to notify the vendor specific non-fatal HW errors
> to the drivers for the error recovery.
This doesn't apply cleanly to v5.8-rc1... thanks for waiting for the merge
window to
finish, but please rebase onto the latest and greatest ke
Hi Tanxiaofei,
(sorry for the late reply)
On 28/09/2020 03:02, Xiaofei Tan wrote:
> After the commit 8fcc4ae6faf8 ("arm64: acpi: Make apei_claim_sea()
> synchronise with APEI's irq work") applied, do_sea() return directly
> for user-mode if apei_claim_sea() handled any error record. Therefore,
>
Hi guys,
On 17/09/2020 09:40, Borislav Petkov wrote:
> On Thu, Sep 10, 2020 at 03:29:56PM +, Shiju Jose wrote:
> You can't know what exactly you wanna do if you don't have a use case
> you're trying to address.
>
>> According to the ARM Processor CPER definition the error types
>> reported a
#x27; machines to know what normal
looks like?
I can't see how a reasonable prediction can be made from just one machine's
behaviour
since boot. These are corrected errors, nothing has gone wrong.
>> Open question from James with my reply to it:
>>
>> On Thu, Oct 01,
401 - 500 of 707 matches
Mail list logo
