From: Jagan Teki
Added basic dts support for MicroZed board.
- UART
- SDHCI
- Ethernet
Cc: Soren Brinkmann
Cc: Michal Simek
Signed-off-by: Jagan Teki
---
Changes for v2:
- Add SDHCI
- Add Ethernet
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/zynq
On Mon, Aug 29, 2016 at 6:54 PM, Jagan Teki wrote:
> On Wed, Aug 10, 2016 at 2:10 AM, Jagan Teki wrote:
>> Add quad page program support with the use of nor->flags
>> and then controller will use 4 lines for data transmission
>> which is quite faster than page program(02h
On Fri, Sep 23, 2016 at 11:33 AM, Michal Simek wrote:
> On 22.9.2016 22:59, Sören Brinkmann wrote:
>> On Thu, 2016-09-22 at 18:51:29 +0530, Jagan Teki wrote:
>>> From: Jagan Teki
>>>
>>> Added basic dts support for MicroZed board.
>>>
>>&g
On Fri, Sep 23, 2016 at 2:07 PM, Michal Simek wrote:
> On 23.9.2016 09:39, Jagan Teki wrote:
>> On Fri, Sep 23, 2016 at 11:33 AM, Michal Simek
>> wrote:
>>> On 22.9.2016 22:59, Sören Brinkmann wrote:
>>>> On Thu, 2016-09-22 at 18:51:29 +0530, Jaga
From: Jagan Teki
Added basic dts support for MicroZed board.
- UART
- SDHCI
- Ethernet
Cc: Soren Brinkmann
Cc: Michal Simek
Signed-off-by: Jagan Teki
---
Changes for v3:
- Add Xilinx copyright
Changes for v2:
- Add SDHCI
- Add Ethernet
arch/arm/boot/dts/Makefile
nt to not specify them in this way
Please try to understand that due to the case where we used fixed
voltage regulators on SOM as mentioned By Metteo and Michael dt nodes
should have regulator-always-on and regulator-boot-on properties. And
even we added one of our module which is already in ML[1]
Hope
This is series add dts support for Engicam I.Core M6 qdl modules on
top of */shawnguo/linux.git for-next.
Jagan Teki (6):
of: Add vendor prefix for Engicam s.r.l company
ARM: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual initial support
ARM: dts: imx6q: Add Engicam i.CoreM6 DualLite/Solo
From: Jagan Teki
Add usbotg support for Engicam i.CoreM6 dql modules.
Cc: Sascha Hauer
Cc: Fabio Estevam
Cc: Shawn Guo
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
Changes for v6:
- none
Changes for v5:
- none
Changes for v4:
- new patch
From: Jagan Teki
Add usbhost support for Engicam i.CoreM6 dql modules.
Cc: Sascha Hauer
Cc: Fabio Estevam
Cc: Shawn Guo
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
Changes for v6:
- none
Changes for v5:
- none
Changes for v4:
- new patch
From: Jagan Teki
Engicam providing design services of electronic systems with
high content of technology, relying on a long experience in
electronic design.
For more info visit
http://www.engicam.com/en/
Cc: Sascha Hauer
Cc: Fabio Estevam
Cc: Shawn Guo
Cc: Matteo Lisi
Cc: Michael Trimarchi
From: Jagan Teki
i.CoreM6 Quad/Dual modules are system on module solutions manufactured
by Engicam with following characteristics:
CPU NXP i.MX6 DQ, 800MHz
RAM 1GB, 32, 64 bit, DDR3-800/1066
NAND SLC,512MB
Power supply Single 5V
MAX LCD RES FULLHD
and more info
From: Jagan Teki
Add FEC support for Engicam i.CoreM6 dql modules.
Observed similar 'eth0: link is not ready' issue which was
discussed in [1] due rmii mode with external ref_clk, so added
clock node along with the properties mentioned by Shawn in [2]
FEC link log:
$ ifc
From: Jagan Teki
i.CoreM6 DualLite/Solo modules are system on module solutions manufactured
by Engicam with following characteristics:
CPU NXP i.MX6 DL, 800MHz
RAM 1GB, 32, 64 bit, DDR3-800/1066
NAND SLC,512MB
Power supply Single 5V
MAX LCD RES FULLHD
and more
On Wed, Sep 14, 2016 at 4:06 AM, Fabio Estevam wrote:
> On Sun, Sep 11, 2016 at 3:30 PM, Jagan Teki wrote:
>
>> + reg_3p3v: regulator-3p3v {
>> + compatible = "regulator-fixed";
>> + regulator-name = "3P3V";
>>
kernel.org/patch/3490511/
Cc: Sascha Hauer
Cc: Fabio Estevam
Cc: Shawn Guo
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
Changes for v5:
- new patch
arch/arm/boot/dts/imx6qdl-icore.dtsi | 37
1 file changed, 37 insertions(+)
di
This is series add dts support for Engicam I.Core M6 qdl modules.
Jagan Teki (6):
of: Add vendor prefix for Engicam s.r.l company
ARM: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual initial support
ARM: dts: imx6q: Add Engicam i.CoreM6 DualLite/Solo initial support
ARM: dts: imx6qdl-icore
://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q
Cc: Sascha Hauer
Cc: Fabio Estevam
Cc: Shawn Guo
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
Changes for v5:
- none
Changes for v4:
- new patch
Changes for v3:
- Use compatible as
: Jagan Teki
---
Changes for v5:
- none
Changes for v4:
- new patch
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-prefixes.txt
://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q
Cc: Sascha Hauer
Cc: Fabio Estevam
Cc: Shawn Guo
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
Note: Fabio, Look like engicam uses some fixed regulators so regulator-boot-on
and regulator-always-on are needed for
Add usbhost support for Engicam i.CoreM6 dql modules.
Cc: Sascha Hauer
Cc: Fabio Estevam
Cc: Shawn Guo
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
Changes for v5:
- none
Changes for v4:
- new patch
arch/arm/boot/dts/imx6qdl-icore.dtsi | 15
Add usbotg support for Engicam i.CoreM6 dql modules.
Cc: Sascha Hauer
Cc: Fabio Estevam
Cc: Shawn Guo
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
Changes for v5:
- none
Changes for v4:
- new patch
arch/arm/boot/dts/imx6qdl-icore.dtsi | 23
On 22 April 2016 at 12:09, Yunhui Cui wrote:
> From: Yunhui Cui
>
> With the physical sectors combination, S25FS-S family flash
> requires some special operations for read/write functions.
>
> Signed-off-by: Yunhui Cui
> ---
> drivers/mtd/spi-nor/spi-nor.c | 59
> ++
these family parts again and do two different erase
operations.
Cc: Brian Norris
Cc: Yunhui Cui
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
drivers/mtd/spi-nor/spi-nor.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index d0
these family parts again and do two different erase
operations.
Cc: Brian Norris
Cc: Yunhui Cui
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
Changes for v2:
- Fix wrong vendor name in commit message
drivers/mtd/spi-nor/spi-nor.c | 1 +
1 file changed, 1 insertion(+)
diff --
Series add new dts nodes like gmac, usb, io_domains and fixed existing
regulator, pmic stuff as per schematic.
Jagan Teki (9):
ARM: dts: rockchip: rk3288-vyasa: Remove vdd_log from rk808, DCDC_REG1
ARM: dts: rockchip: rk3288-vyasa: Use fixed voltage range for vccio_sd
ARM: dts: rockchip
vdd_log, never used on DCDC_REG1 of rk808 from latest schematic so
remove the same and update the regulator-name as 'vdd_arm' to sync
with existing rk3288 board dts files.
Signed-off-by: Jagan Teki
---
arch/arm/boot/dts/rk3288-vyasa.dts | 4 ++--
1 file changed, 2 insertions(+), 2
vccio_sd has supplied to vqmmc-supply for sdmmc, use fixed voltage
range of 3.3v for better IO lines supply voltage.
Signed-off-by: Jagan Teki
---
arch/arm/boot/dts/rk3288-vyasa.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts
b/arch
Add supporting regulators for rk3288-vyasa board, dc12_vbat is
parent regulatorand followed regulators as are child regulators.
regulator naming conversion followed as per schematic for better
readability and easy for identification.
Signed-off-by: Jagan Teki
---
arch/arm/boot/dts/rk3288
rk808, SWITCH_REG1 has configured for sdmmc regulator as vcc_sd,
so use the same by renaming vcc33_sd to vcc_sd(as per schematic)
and drop explicit regulator definition from root.
Signed-off-by: Jagan Teki
---
arch/arm/boot/dts/rk3288-vyasa.dts | 22 ++
1 file changed, 2
Add usb otg support for rk3288-vyasa, board support usb1 otg
power through otg_vbus_drv and naming conversion followed
as per schematic.
Signed-off-by: Jagan Teki
---
Note: g_ether/g_serial fired an issue with mainline tree
https://paste.ubuntu.com/25752571/
arch/arm/boot/dts/rk3288-vyasa.dts
Signed-off-by: Jagan Teki
---
arch/arm/boot/dts/rk3288-vyasa.dts | 41 ++
1 file changed, 41 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts
b/arch/arm/boot/dts/rk3288-vyasa.dts
index 0fa447f..c79a4c7 100644
--- a/arch/arm/boot/dts/rk3288
Add usb host support for rk3288-vyasa, board support hub power
through phy_pwr_en and usb2 host power through usb2_pwr_en and
naming conversion followed as per schematic.
Signed-off-by: Jagan Teki
---
arch/arm/boot/dts/rk3288-vyasa.dts | 48 ++
include/dt
Add io domains supported by rk3288-vyasa board.
Signed-off-by: Jagan Teki
---
arch/arm/boot/dts/rk3288-vyasa.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts
b/arch/arm/boot/dts/rk3288-vyasa.dts
index 2f1389a..0e0995f 100644
--- a/arch
RTC_DRV_RK808 need to have build statically for the platforms
do use MFB_RK808 so replace module with statical link.
Signed-off-by: Jagan Teki
---
arch/arm/configs/multi_v7_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch
Signed-off-by: Jagan Teki
---
Changes for v2:
- status s/ok/okay
arch/arm/boot/dts/rk3288-vyasa.dts | 41 ++
1 file changed, 41 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts
b/arch/arm/boot/dts/rk3288-vyasa.dts
index 0fa447f..c79a4c7 100644
On Mon, Oct 16, 2017 at 11:32 PM, Heiko Stübner wrote:
> Hi,
>
> Am Montag, 16. Oktober 2017, 17:46:27 CEST schrieb Jagan Teki:
>> RTC_DRV_RK808 need to have build statically for the platforms
>> do use MFB_RK808 so replace module with statical link.
>
> why would you
+ zhaoyifan
(Added Orangepi member for data-sheet upload confirmation)
On Fri, May 26, 2017 at 2:29 PM, Andre Przywara wrote:
> Hi,
>
> On 26/05/17 04:54, Chen-Yu Tsai wrote:
>> On Fri, May 26, 2017 at 6:30 AM, André Przywara
>> wrote:
>>> On 25/05/17 20:26, Jaga
On Fri, May 26, 2017 at 10:10 PM, wrote:
> 在 2017-05-26 03:26，Jagan Teki 写道：
>>
>> From: Jagan Teki
>>
>> Orangepi Prime is an open-source single-board computer
>> using the Allwinner h5 SOC.
>
>
> Sorry but I have already added this board and it&#x
From: Jagan Teki
from BPI(BIPAI KEJI LIMITED) products the Bananapi board
is named as 'Bananapi M1' and this is the starting
bananapi board from M1 series.
So rename dts and suffix 'M1' on model for the same,
so-that next sequence on bananapi starts like M1 Plus, M2 and s
From: Jagan Teki
Since Bananapi brand is owned by BIPAI KEJI(BPI), the previous
Lemaker and Sinovoip no longer use the bananapi brand, hence
Updated the model and compatible for existing bananapi boards
which is denoted same like in binanapi site.
Example: for Bananapi M64 board as
model
From: Jagan Teki
Since Bananapi brand is owned by BIPAI KEJI(BPI),
the previous Sinovoip no longer use the bananapi brand,
hence rename sun6i-a31s-sinovoip-bpi-m2.dts to
sun6i-a31s-bananapi-m2.dts
Signed-off-by: Jagan Teki
---
Note: Bananapi BPI product site
http://www.banana-pi.org
On Tue, May 30, 2017 at 3:15 AM, Karsten Merker wrote:
> On Mon, May 29, 2017 at 07:30:26PM +0000, Jagan Teki wrote:
>> From: Jagan Teki
>>
>> from BPI(BIPAI KEJI LIMITED) products the Bananapi board
>> is named as 'Bananapi M1' and this is the starting
>&
From: Jagan Teki
NanoPi A64 is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner A64 SOC.
Nanopi A64 features
- Allwinner A64, 64-bit Quad-core Cortex-A53@648MHz to 1.152GHz, DVFS
- 1GB DDR3 RAM
- MicroSD
- Gigabit Ethernet (RTL8211E)
- Wi-Fi 802.11b/g
From: Jagan Teki
NanoPi M1 Plus is designed and developed by FriendlyElec
using the Allwinner 64-bit H5 SOC.
NanoPi Neo2 key features
- Allwinner H5, Quad-core 64-bit Cortex-A53
- 512MB DDR3 RAM
- microSD slot
- 10/100/1000M Ethernet
- Serial Debug Port
- 5V 2A DC MicroUSB power-supply
Signed
From: Jagan Teki
NanoPi M1 Plus is designed and developed by FriendlyElec
for professionals, enterprise users, makers and hobbyists
using the Allwinner H3 SOC.
NanoPi M1 Plus key features
- Allwinner H3, Quad-core Cortex-A7@1.2GHz
- 1GB DDR3 RAM
- 8GB eMMC
- microSD slot
- 10/100/1000M Ethernet
On 27 August 2015 at 17:19, punnaiah choudary kalluri
wrote:
> On Thu, Aug 27, 2015 at 3:45 PM, Jagan Teki wrote:
>> On 27 August 2015 at 14:18, punnaiah choudary kalluri
>> wrote:
>>> On Thu, Aug 27, 2015 at 11:53 AM, Jagan Teki wrote:
>>>> On 26 Aug
On 26 August 2015 at 16:18, Jagan Teki wrote:
> The clear flag status register operation is required by Micron
> SPI-NOR chips, which support FSR. And if error bits of FSR
> have been set like protection, voltage, erase, and program,
> it must be cleared by executing clear F
On 8 September 2015 at 15:19, Bayi Cheng wrote:
> Add device tree binding documentation for serial flash with
> Mediatek serial flash controller
>
> Signed-off-by: Bayi Cheng
> ---
> Documentation/devicetree/bindings/mtd/mtk_nor.txt | 25
> +++
> 1 file changed, 25 insertion
On 8 September 2015 at 15:19, Bayi Cheng wrote:
> Add Mediatek nor flash node
>
> Signed-off-by: Bayi Cheng
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> b/arch/arm64/boot/dts/medi
On 4 September 2015 at 13:59, Vignesh R wrote:
> In addition to providing direct access to SPI bus, some spi controller
> hardwares (like ti-qspi) provide special memory mapped port
> to accesses SPI flash devices in order to increase read performance.
> This means the controller can automatically
On 19 August 2015 at 15:26, Jagan Teki wrote:
> Use existing write_sr() call instead of decoding and
> calling nor->write_reg separately.
>
> Signed-off-by: Jagan Teki
> Cc: David Woodhouse
> Cc: Brian Norris
> ---
> drivers/mtd/spi-nor/spi-nor.c | 3 +--
> 1 f
On 19 August 2015 at 15:26, Jagan Teki wrote:
> Since write enabling shall do with buf and len without
> need of exctra write_enable argument, hence removed the
> same from write_reg.
>
> Signed-off-by: Jagan Teki
> Cc: David Woodhouse
> Cc: Brian Norris
> Cc: Han
Move usdhc2 and gpmi along with pinctrl nodes on
imx6ul-isiot.dtsi from dts files and mark it as 'disabled'
and the relevant dts will enable the status as 'okay'
Signed-off-by: Jagan Teki
---
arch/arm/boot/dts/imx6ul-isiot-emmc.dts | 23 ---
arch/arm/boot/dts/imx6ul
Adopt the SPDX license identifier headers to ease license compliance
management.
Also added Engicam Copyright on missing files.
Signed-off-by: Jagan Teki
---
arch/arm/boot/dts/imx6dl-icore-mipi.dts | 2 +-
arch/arm/boot/dts/imx6dl-icore-rqs.dts| 38 +-
arch/arm/boot
Use consistent pinctrl node names for Engicam dt files,
sufix 'grp' look consistent than actual node name
- pinctrl_gpmi_nand: gpmi-nand {
+ pinctrl_gpmi_nand: gpminandgrp {
Signed-off-by: Jagan Teki
---
arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi | 2 +-
arch/arm/boot/dts/imx6qdl-
Add Ethernet support for orangepi-one-plus board,
- Ethernet port connected via RTL8211E PHY
- GMAC_EN is connected via PD6
- GMAC-3V supplied from ALDO2 regulator
Signed-off-by: Jagan Teki
---
.../allwinner/sun50i-h6-orangepi-one-plus.dts | 29 +++
1 file changed, 29 insertions
Add reg_drivevbus regualtor for boards which are using
external regulator to drive the OTG VBus through N_VBUSEN
PMIC pin.
Signed-off-by: Jagan Teki
---
Changes for v4:
- rebase on master
Changes for v3:
- none
arch/arm64/boot/dts/allwinner/axp803.dtsi | 5 +
1 file changed, 5 insertions
Like axp221, axp223, axp813 the axp803 is also supporting external
regulator to drive the OTG VBus through N_VBUSEN PMIC pin.
Add support for it.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
Changes for v4:
- rebase on master
Changes for v3:
- Update drivevbus in table of regulators
Add usb otg support for bananapi-m64 board,
- USB-ID connected with PH9
- USB-DRVVBUS controlled by N_VBUSEN pin from PMIC
Signed-off-by: Jagan Teki
---
Changes for v4:
- rebase on master
- tested otg host mode.
Changes for v3:
- Move the position of reg_drivevbus as per binding documentation
Add usb otg support for a64-olinuxino board,
- USB0-ID connected with PH9
- USB0-VBUSDET connected with PH6
- USB-DRVVBUS controlled by N_VBUSEN pin from PMIC
Signed-off-by: Jagan Teki
---
Changes for v2:
- rebase on master
- tested otg host mode.
.../boot/dts/allwinner/sun50i-a64
Add usb otg support for orangepi-zero-plus2 board:
- Add usb_otg node with dr_mode as 'otg'
- USB0-IDDET connected to PA21
- VBUS connected through DCIN which always on
Tested mass storage function.
Signed-off-by: Jagan Teki
---
Changes for v2:
- Change dr_mode to peripheral
.../dts
Switch to use koe_tx31d200vm0baa LVDS timings from
panel-simple instead hard coding the same in dts.
Signed-off-by: Jagan Teki
---
Changes for v4:
- Send as seprate patch from previous series
https://patchwork.kernel.org/patch/10199423/
Changes for v3, v2:
- none
arch/arm/boot/dts/imx6q
Up to 2 GB DDR3-1066
Video InterfacesUp to 1 Parallel Up to 2 LVDS HDMI 1.4
port 8 bit CSI INPUT MIPI-CSI INPUT
1 x 10/100 Ethernet interface, 2 x USB, 1 x PCIe, 1 x I2S etc
Signed-off-by: Jagan Teki
---
Changes for v4:
- Send as seprate patch from previous
Like axp221, axp223, axp813 the axp803 is also supporting external
regulator to drive the OTG VBus through N_VBUSEN PMIC pin.
Add support for it.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
Reviewed-by: Chen-Yu Tsai
---
Changes for v5:
- Collect Chen-Yu reviewed-by tag
Changes for v4
Add reg_drivevbus regualtor for boards which are using
external regulator to drive the OTG VBus through N_VBUSEN
PMIC pin.
Signed-off-by: Jagan Teki
Reviewed-by: Chen-Yu Tsai
---
Changes for v5:
- Collect Chen-Yu reviewed-by tag
Changes for v4:
- rebase on master
Changes for v3:
- none
arch
Add usb otg support for bananapi-m64 board,
- USB-ID connected with PH9
- USB-DRVVBUS controlled by N_VBUSEN pin from PMIC
Signed-off-by: Jagan Teki
Reviewed-by: Chen-Yu Tsai
---
Changes for v5:
- Kept reg_drivevbus node in alphabetical order.
- Collect Chen-Yu reviewed-by tag
Changes for v4
ound 1c0c000.lcd-controller
(ops sun4i_tcon_ops)
[ 18.843246] sun4i-drm display-engine: bound 1ca.dsi (ops
sun6i_dsi_ops [sun6i_dsi])
[ 18.851263] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 18.857878] [drm] No driver support for vblank timestamp query.
<< hang here >>
[1]
https://github.com/openedev/linux-openedev/commit/9030929673b21971ff77b7593e88c26e84ed3742
[2]
https://github.com/openedev/linux-openedev/commit/725afe3ce4507fa975fcb4a04b1bbb90d9d44a91
Jagan.
--
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
On Fri, Apr 13, 2018 at 5:39 PM, Maxime Ripard
wrote:
> On Fri, Apr 13, 2018 at 05:30:04PM +0530, Jagan Teki wrote:
>> On Wed, Apr 11, 2018 at 6:13 PM, Maxime Ripard
>> wrote:
>> > On Wed, Apr 04, 2018 at 11:57:08AM +0200, Maxime Ripard wrote:
>> >> Hi,
>&g
Added 'bticino' vendor prefix for Bticino International.
Signed-off-by: Jagan Teki
Signed-off-by: Simone CIANNI
Signed-off-by: Raffaele RECALCATI
Reviewed-by: Rob Herring
---
Changes for v2:
- Collect review tag from Rob
Documentation/devicetree/bindings/vendor-prefixes.txt | 1
This patch adds initial support for BTicino i.MX6DL Mamoj board.
Signed-off-by: Jagan Teki
Signed-off-by: Simone CIANNI
Signed-off-by: Raffaele RECALCATI
---
Changes for v2:
- Squash 'PFUZE100 support' patch
- Remove fec PHY reset mux
arch/arm/boot/dts/Makefile | 1 +
arc
Hi Maxime,
On Tue, Mar 6, 2018 at 7:25 PM, Maxime Ripard wrote:
> Hi,
>
> Here is an preliminary version of the MIPI-DSI support for the Allwinner
> SoCs.
>
> This controller can be found on a number of recent SoCs, such as the
> A31, A33 or the A64.
>
> Given the sparse documentation, there's a
The MIPI DSI controller on Allwinner A64 is similar to
Allwinner A31 without support of DSI mod clock.
Signed-off-by: Jagan Teki
---
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/sunxi
The MIPI DSI controller on Allwinner A64 is similar to
Allwinner A31 without support of DSI mod clock(CLK_DSI_SCLK)
So, alter has_mod_clk bool via driver data for respective
SoC's compatible.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
transfer types this make
debugging easy for new transfer types.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 156b371243c6
clock logic in next versions.
Thanks,
Jagan.
Jagan Teki (12):
clk: sunxi-ng: a64: Fix gate bit of DSI DPHY
drm/sun4i: sun6i_mipi_dsi: Add Allwinner A64 MIPI DSI support
dt-bindings: sun6i-dsi: Add compatible for A64 MIPI DSI
drm/sun4i: sun6i_mipi_dsi: Enable missing DSI bus cl
DSI DPHY gate bit on MIPI DSI clock register is bit 15
not bit 30.
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index
DSI bus_clk is already available in sun6i_dsi but missed to
get the clk and process for enable/disable.
This patch add support for it.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/sun4i
TCON DRQ set bits for non-burst DSI mode can computed via
horizontal front porch instead of front porch + sync timings.
Since there no documentation for TCON_DRQ_REG(0x7c) register
this change is taken as reference from BPI-M64-bsp.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i
According to horizontal and vertical timings are defined
per the diagram from include/drm/drm_modes.h
Back porch = [hv]total - [hv]sync_end
So, update SUN6I_DSI_BASIC_SIZE0_VBP calculation as
mode->vtotal - mode->vsync_end
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi
out.
[CRTC:36:crtc-0] vblank wait timed out
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 9918fdb990ff
Bananapi S070WV20-CT16 is 800x480, 4-lane MIPI-DSI panel, the
same panel PCB comes with parallel RBG which is supported via
panel-simple with "bananapi,s070wv20-ct16" compatible.
Signed-off-by: Jagan Teki
---
.../panel/bananapi,s070wv20-ct16-dsi.txt | 21 +++
1 fi
Bananapi S070WV20-CT16 is 800x480, 4-lane MIPI-DSI panel which
can be used to connect via BPI-M64 board, so add a driver for it.
The same panel PCB comes with parallel RBG which is supported via
panel-simple driver with "bananapi,s070wv20-ct16" compatible.
Signed-off-by: Jagan Teki
--
The A64 has a MIPI-DSI block which is similar to A31
without mod clock.
So, add dsi node with A64 compatible, dphy node with
A31 compatible and finally connect dsi to tcon0 to
make proper DSI pipeline.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 44
This patch add support for Bananapi S070WV20-CT16 DSI panel to
BPI-M64 board.
DSI panel connected via board DSI port with,
- DC1SW as AVDD supply
- DCDC1 as DVDD supply
- PD6 gpio for reset pin
- PD5 gpio for backlight enable pin
- PD7 gpio for backlight vdd supply
Signed-off-by: Jagan Teki
On Thu, Sep 27, 2018 at 6:13 PM Chen-Yu Tsai wrote:
>
> Hi,
>
> On Thu, Sep 27, 2018 at 7:49 PM Jagan Teki wrote:
> >
> > DSI bus_clk is already available in sun6i_dsi but missed to
> > get the clk and process for enable/disable.
> >
> > This patch
On Thu, Sep 27, 2018 at 8:51 PM Maxime Ripard wrote:
>
> On Thu, Sep 27, 2018 at 05:18:44PM +0530, Jagan Teki wrote:
> > According to horizontal and vertical timings are defined
> > per the diagram from include/drm/drm_modes.h
> >
> > Back porch = [hv]total - [
On Thu, Sep 27, 2018 at 7:47 PM Chen-Yu Tsai wrote:
>
> On Thu, Sep 27, 2018 at 9:44 PM Jagan Teki wrote:
> >
> > On Thu, Sep 27, 2018 at 6:13 PM Chen-Yu Tsai wrote:
> > >
> > > Hi,
> > >
> > > On Thu, Sep 27, 2018 at 7:49 PM Jagan Teki
On Thu, Sep 27, 2018 at 10:44 PM Maxime Ripard
wrote:
>
> On Thu, Sep 27, 2018 at 05:18:46PM +0530, Jagan Teki wrote:
> > Accordingly to BPI-M64-bsp DE DSI code Video start delay
> > can be computed by subtracting total vertical timing with
> > front porch timing and with
On Thu, Sep 27, 2018 at 10:48 PM Maxime Ripard
wrote:
>
> On Thu, Sep 27, 2018 at 05:18:43PM +0530, Jagan Teki wrote:
> > Short transfer write support for DCS and Generic transfer types
> > share similar way to process command sequence in DSI block so
> > add generic wri
On Thu, Sep 27, 2018 at 10:28 PM Maxime Ripard
wrote:
>
> On Thu, Sep 27, 2018 at 05:18:45PM +0530, Jagan Teki wrote:
> > TCON DRQ set bits for non-burst DSI mode can computed via
> > horizontal front porch instead of front porch + sync timings.
> >
> > Si
backlight enable pin
Signed-off-by: Jagan Teki
---
.../dts/allwinner/sun50i-a64-pine64-lts.dts | 37 +++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts
index 72d6961dc312
On Mon, Nov 19, 2018 at 1:57 PM Maxime Ripard wrote:
>
> On Fri, Nov 16, 2018 at 10:09:05PM +0530, Jagan Teki wrote:
> > Loop N1 instruction delay for burst mode lcd panel are
> > computed as per BSP code.
> >
> > Reference code is available in BSP (from linux-sunxi
On Mon, Nov 19, 2018 at 2:00 PM Maxime Ripard wrote:
>
> On Fri, Nov 16, 2018 at 10:09:07PM +0530, Jagan Teki wrote:
> > Burst mode display timings are different from convectional
> > video mode so update the horizontal and vertical timings.
> >
> > Reference code ta
On Mon, Nov 19, 2018 at 2:02 PM Maxime Ripard wrote:
>
> On Fri, Nov 16, 2018 at 10:09:08PM +0530, Jagan Teki wrote:
> > Allwinner MIPI DSI DRQ set value can be varied with respective
> > video modes.
> > - burst mode the set value is always 0
> > - video modes who
On Mon, Nov 19, 2018 at 2:08 PM Maxime Ripard wrote:
>
> On Fri, Nov 16, 2018 at 10:09:10PM +0530, Jagan Teki wrote:
> > Probe tcon0 during dsi_bind, so-that the tcon attributes like
> > divider value, clock rate can get whenever it need.
> >
> > Signed-off-by: Ja
On Tue, Oct 30, 2018 at 1:49 PM Yong Deng wrote:
>
> Allwinner V3s SoC features a CSI module with parallel interface.
>
> This patch implement a v4l2 framework driver for it.
>
> Reviewed-by: Hans Verkuil
> Reviewed-by: Maxime Ripard
> Tested-by: Maxime Ripard
> Signed-off-by: Yong Deng
> ---
me in SUN6I_DSI_BASIC_SIZE0_VBP
On the information note, existing SUN6I_DSI_BASIC_SIZE0_VSA is proper
value.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
b/drivers/gpu/drm/su
lcd_ht -panel->lcd_x - panel->lcd_hbp
=> (timmings->hor_front_porch + panel->lcd_hbp + panel->lcd_x)
- panel->lcd_x - panel->hbp
=> timmings->hor_front_porch
=> mode->hsync_start - mode->hdisplay
So, update the DRQ set bits accordingly.
Signed-o
DSI DPHY gate bit on MIPI DSI clock register is bit 15
not bit 30.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
b/drivers/clk/sunxi-ng/ccu
On Mon, Dec 3, 2018 at 3:44 PM Chen-Yu Tsai wrote:
>
> On Mon, Dec 3, 2018 at 6:07 PM Jagan Teki wrote:
> >
> > This series support CSI on Allwinner A64.
> >
> > The CSI controller seems similar to that of in H3, so fallback
> > compatible is used to load th
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