The pll controller register set includes sets of registers with
different purposes, so it's logically to add syscon entry to be able
to access them from appropriate places.
Signed-off-by: Ivan Khoronzhuk
---
Based on linux-next/master
arch/arm/boot/dts/keystone.dtsi | 5 +
1 file ch
Enable reset driver support in order to have opportunity
to reboot SoC by watchdog and by software.
Signed-off-by: Ivan Khoronzhuk
---
arch/arm/configs/keystone_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/keystone_defconfig
b/arch/arm/configs
use.
So add keystone reset driver to handle all this stuff.
Signed-off-by: Ivan Khoronzhuk
---
drivers/power/reset/Kconfig | 8 ++
drivers/power/reset/Makefile | 1 +
drivers/power/reset/keystone-reset.c | 153 +++
3 files changed, 162
control registers in order to use mux block
registers for all watchdogs.
"ti,wdt_list" - option to declare what watchdog are used to reboot
the SoC, so set "0" WDT as default.
Signed-off-by: Ivan Khoronzhuk
---
arch/arm/boot/dt
On 05/20/2014 10:27 PM, Arnd Bergmann wrote:
On Tuesday 20 May 2014 21:35:23 Ivan Khoronzhuk wrote:
Thank for the note.
Ok.
Memory map:
[00 0231 - 00 023101FF] size=512 PLL Controller
[00 0262 - 00 02620FFF] size=4K device state control registers
I'll define in DT two new s
.
Additionally soft or hard reset can be configured.
Signed-off-by: Ivan Khoronzhuk
---
.../bindings/power/reset/keystone-reset.txt| 66 ++
1 file changed, 66 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/reset/keystone-reset.txt
diff --git a
: reset: keystone-reset: introduce keystone reset driver
- no functional changes, only sanity
Power: reset: add bindings for keystone reset driver
- corrected WDT numeration in examples
- extended description of wdt_list property
v1..v2
- re basedon on v3.15-rc1 without
Remove reset stuff in flavour of using keystone reset driver:
driver/power/reset/keystone-reset.c
Signed-off-by: Ivan Khoronzhuk
---
arch/arm/mach-keystone/keystone.c | 34 --
1 file changed, 34 deletions(-)
diff --git a/arch/arm/mach-keystone/keystone.c
b/arch
Ignore this. It'll be included in "Introduce keystone reset driver"
patch series
On 05/21/2014 05:17 PM, Ivan Khoronzhuk wrote:
The pll controller register set includes sets of registers with
different purposes, so it's logically to add syscon entry to be able
to access t
Ignore this. It'll be included in "Introduce keystone reset driver"
patch series
On 05/21/2014 05:16 PM, Ivan Khoronzhuk wrote:
Device state control registers has register regions with different
purposes so add syscon entry in order to be able to correctly access
them from app
On 05/21/2014 05:50 PM, Arnd Bergmann wrote:
On Wednesday 21 May 2014 17:27:31 Ivan Khoronzhuk wrote:
This node is intended to allow SoC reset in case of software reset
or appropriate watchdogs.
The Keystone SoCs can contain up to 4 watchdog timers to reset
SoC. Each watchdog timer event
On 05/21/2014 05:50 PM, Arnd Bergmann wrote:
On Wednesday 21 May 2014 17:27:33 Ivan Khoronzhuk wrote:
The keystone driver requires the next additional properties:
"ti,syscon-pll" - syscon register range used to access pll controller
registers in order to use res
use.
So add keystone reset driver to handle all this stuff.
Signed-off-by: Ivan Khoronzhuk
---
drivers/power/reset/Kconfig | 8 ++
drivers/power/reset/Makefile | 1 +
drivers/power/reset/keystone-reset.c | 166 +++
3 files changed, 175
.
Additionally soft or hard reset can be configured.
Signed-off-by: Ivan Khoronzhuk
---
.../bindings/power/reset/keystone-reset.txt| 67 ++
1 file changed, 67 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/reset/keystone-reset.txt
diff --git a
Enable reset driver support in order to have opportunity
to reboot SoC by watchdog and by software.
Signed-off-by: Ivan Khoronzhuk
---
arch/arm/configs/keystone_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/keystone_defconfig
b/arch/arm/configs
The main pll controller used to drive theC66x CorePacs, the switch fabric,
and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and
the NETCP modules) requires a PLL Controller to manage the various clock
divisions, gating, and synchronization.
Signed-off-by: Ivan Khoronzhuk
phandle to syscon used to
access device state control registers and the offset
in order to use mux block registers for all watchdogs.
"ti,wdt_list" - option to declare what watchdogs are used to reboot
the SoC, so set "0" WD
Remove reset stuff in flavour of using keystone reset driver:
driver/power/reset/keystone-reset.c
Signed-off-by: Ivan Khoronzhuk
---
arch/arm/mach-keystone/keystone.c | 34 --
1 file changed, 34 deletions(-)
diff --git a/arch/arm/mach-keystone/keystone.c
b/arch
in examples
- extended description of wdt_list property
v1..v2
- re based on v3.15-rc1 without changes
Ivan Khoronzhuk (7):
power: reset: keystone-reset: introduce keystone reset driver
clock: keystone-pllctrl: add bindings for keystone pll controller
mfd: ti-keystone-devct
The Keystone II devices have a set of registers that are used to control
the status of its peripherals. This node is intended to allow access to
this functionality.
Signed-off-by: Ivan Khoronzhuk
---
.../devicetree/bindings/mfd/ti-keystone-devctrl.txt | 19 +++
1 file changed
rstctrl: reset-controller {
compatible = "ti,keystone-reset";
reg = <0x023100e8 4>;/* pll reset control reg */
WBR, Sergei
--
Regards,
Ivan Khoronzhuk
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel
On 05/22/2014 04:54 PM, Arnd Bergmann wrote:
On Thursday 22 May 2014 09:52:27 Santosh Shilimkar wrote:
On Thursday 22 May 2014 09:48 AM, Ivan Khoronzhuk wrote:
These patches introduce keystone reset driver.
The keystone SoC can be rebooted in several ways. By external reset
pin, by soft and
lity.
Signed-off-by: Ivan Khoronzhuk
---
.../devicetree/bindings/mfd/ti-keystone-devctrl.txt | 19 +++
1 file changed, 19 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mfd/ti-keystone-devctrl.txt
diff --git a/Documentation/devicetree/bindings/mfd/ti-key
to be used only via syscon phandle, there is no
driver for it,
and compatible string for "ti,keystone-devctrl" added only to be matched by
a high-level device driver if needed.
I'll send new v6 series to you also.
Once again sorry.
--
Regards,
Ivan Khoronzhuk
--
To unsubscrib
On 05/22/2014 07:14 PM, Ivan Khoronzhuk wrote:
On 05/22/2014 06:33 PM, Lee Jones wrote:
Why do I only have this patch? Where is the rest of the set? Also,
it's on v5 and I don't recall seeing the other 4 versions?
It's strange I've sent whole series on
linux-kernel@v
-dev"
v2..v3
Power: reset: keystone-reset: introduce keystone reset driver
- no functional changes, only sanity
Power: reset: add bindings for keystone reset driver
- corrected WDT numeration in examples
- extended description of wdt_list property
v1..v2
- re
use.
So add keystone reset driver to handle all this stuff.
Reviewed-by: Arnd Bergmann
Signed-off-by: Ivan Khoronzhuk
---
drivers/power/reset/Kconfig | 8 ++
drivers/power/reset/Makefile | 1 +
drivers/power/reset/keystone-reset.c | 166
Remove reset stuff in flavour of using keystone reset driver:
driver/power/reset/keystone-reset.c
Reviewed-by: Arnd Bergmann
Signed-off-by: Ivan Khoronzhuk
---
arch/arm/mach-keystone/keystone.c | 34 --
1 file changed, 34 deletions(-)
diff --git a/arch/arm/mach
The Keystone II devices have a set of registers that are used to control
the status of its peripherals. This node is intended to allow access to
this functionality.
Reviewed-by: Arnd Bergmann
Signed-off-by: Ivan Khoronzhuk
---
.../devicetree/bindings/mfd/ti-keystone-devctrl.txt | 19
Enable reset driver support in order to have opportunity
to reboot SoC by watchdog and by software.
Reviewed-by: Arnd Bergmann
Signed-off-by: Ivan Khoronzhuk
---
arch/arm/configs/keystone_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/keystone_defconfig
b
ault.
Reviewed-by: Arnd Bergmann
Signed-off-by: Ivan Khoronzhuk
---
arch/arm/boot/dts/keystone.dtsi | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index d9f99e7..b05def6 100644
--- a/arch/arm/b
Signed-off-by: Ivan Khoronzhuk
---
.../bindings/clock/ti-keystone-pllctrl.txt | 20
1 file changed, 20 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt
diff --git a/Documentation/devicetree/bindings/clock/ti-keystone
.
Additionally soft or hard reset can be configured.
Reviewed-by: Arnd Bergmann
Signed-off-by: Ivan Khoronzhuk
---
.../bindings/power/reset/keystone-reset.txt| 67 ++
1 file changed, 67 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/reset/keystone
On 05/22/2014 08:11 PM, Lee Jones wrote:
On Thu, 22 May 2014, Ivan Khoronzhuk wrote:
The Keystone II devices have a set of registers that are used to control
the status of its peripherals. This node is intended to allow access to
this functionality.
Reviewed-by: Arnd Bergmann
Signed-off-by
On 05/22/2014 09:03 PM, Sergei Shtylyov wrote:
Hello.
On 05/22/2014 08:44 PM, Ivan Khoronzhuk wrote:
This node is intended to allow SoC reset in case of software reset
or appropriate watchdogs.
The Keystone SoCs can contain up to 4 watchdog timers to reset
SoC. Each watchdog timer event
Remove reset stuff in flavour of using keystone reset driver:
driver/power/reset/keystone-reset.c
Reviewed-by: Arnd Bergmann
Signed-off-by: Ivan Khoronzhuk
---
arch/arm/mach-keystone/keystone.c | 34 --
1 file changed, 34 deletions(-)
diff --git a/arch/arm/mach
Signed-off-by: Ivan Khoronzhuk
---
.../bindings/clock/ti-keystone-pllctrl.txt | 20
1 file changed, 20 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt
diff --git a/Documentation/devicetree/bindings/clock/ti-keystone
Enable reset driver support in order to have opportunity
to reboot SoC by watchdog and by software.
Reviewed-by: Arnd Bergmann
Signed-off-by: Ivan Khoronzhuk
---
arch/arm/configs/keystone_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/keystone_defconfig
b
eystone reset driver
- no functional changes, only sanity
Power: reset: add bindings for keystone reset driver
- corrected WDT numeration in examples
- extended description of wdt_list property
v1..v2
- re based on v3.15-rc1 without changes
Ivan Khoronzhuk (7):
power: reset: k
ault.
Reviewed-by: Arnd Bergmann
Signed-off-by: Ivan Khoronzhuk
---
arch/arm/boot/dts/keystone.dtsi | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index d9f99e7..c1414cb 100644
--- a/arch/arm/b
use.
So add keystone reset driver to handle all this stuff.
Reviewed-by: Arnd Bergmann
Signed-off-by: Ivan Khoronzhuk
---
drivers/power/reset/Kconfig | 8 ++
drivers/power/reset/Makefile | 1 +
drivers/power/reset/keystone-reset.c | 166
.
Additionally soft or hard reset can be configured.
Reviewed-by: Arnd Bergmann
Signed-off-by: Ivan Khoronzhuk
---
.../bindings/power/reset/keystone-reset.txt| 67 ++
1 file changed, 67 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/reset/keystone
The Keystone II devices have a set of registers that are used to control
the status of its peripherals. This node is intended to allow access to
this functionality.
Reviewed-by: Arnd Bergmann
Signed-off-by: Ivan Khoronzhuk
---
.../devicetree/bindings/mfd/ti-keystone-devctrl.txt | 19
On 05/23/2014 09:32 PM, Mike Turquette wrote:
Quoting Ivan Khoronzhuk (2014-05-23 08:43:27)
The main pll controller used to drive theC66x CorePacs, the switch fabric,
and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and
the NETCP modules) requires a PLL Controller to
On 05/24/2014 12:28 AM, Santosh Shilimkar wrote:
On Friday 23 May 2014 11:43 AM, Ivan Khoronzhuk wrote:
These patches introduce keystone reset driver.
The keystone SoC can be rebooted in several ways. By external reset
pin, by soft and by watchdogs. This driver allows software reset and reset
On 04/15/2014 02:25 PM, Ivan Khoronzhuk wrote:
On 04/14/2014 09:44 PM, Arnd Bergmann wrote:
On Monday 14 April 2014 20:41:20 Ivan Khoronzhuk wrote:
+Optional properties:
+
+- ti,soft-reset: Boolean option indicating soft reset.
+ By default hard reset is used
In clk_register_psc() function clk_init_data struct is allocated
in the stack. All members of this struct should be initialized
before using otherwise it will contain garbage. So initialize flags
in this structure too.
Signed-off-by: Ivan Khoronzhuk
---
drivers/clk/keystone/gate.c | 1 +
1 file
any driver.
So to avoid its gating at late init we have to disable it in DT.
Signed-off-by: Ivan Khoronzhuk
---
arch/arm/boot/dts/keystone-clocks.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi
b/arch/arm/boot/dts/keystone-clocks.dtsi
index 236359
the stack. All members of this struct should be initialized
before using otherwise it will contain garbage. So initialize flags
in this structure too.
Signed-off-by: Ivan Khoronzhuk
---
drivers/clk/keystone/gate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/keystone/gate.
IF.
This means that MSMC clock is always needed by SoC and cannot be gated.
It is only one from necessary clocks that was not used by any driver.
So to avoid its gating at late init we have to disable it in DT.
Signed-off-by: Ivan Khoronzhuk
---
arch/arm/boot/dts/keystone-clocks.dtsi | 1 +
Ok
On 01/30/2014 04:32 PM, Santosh Shilimkar wrote:
On Thursday 30 January 2014 08:49 AM, Ivan Khoronzhuk wrote:
Yes. As result the clk->flag field contains garbage. In my case it leads
that flag CLK_IGNORE_UNUSED is set for most of clocks. As result a bunch
of unused clocks cannot
Thanks, I will send v2
On 01/30/2014 04:31 PM, Santosh Shilimkar wrote:
On Thursday 30 January 2014 08:58 AM, Ivan Khoronzhuk wrote:
Ok. I will delete node for this clock from DT and send v1
Sorry for the html reply first of all. That node should never have
been actually added since the
set for most of clocks. As result a
bunch of unused clocks cannot be disabled.
So initialize flags in this structure too.
Signed-off-by: Ivan Khoronzhuk
---
Based on
git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git
keystone/master
v1..v2:
- updated commit description o
ding to system stall.
Signed-off-by: Ivan Khoronzhuk
---
Based on
git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git
keystone/master
v1..v2:
- dropped "msmcsram" clock node, instead disabling
- updated comment message
arch/arm/boot/dts/keystone-clocks.dtsi | 10
Keystone SoC uses the same watchdog driver as Davinci, so
enable WDT and core used by it.
Signed-off-by: Ivan Khoronzhuk
Conflicts:
arch/arm/configs/keystone_defconfig
---
Rebased on
git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git
keystone/master
arch/arm
() instead of setup_irq()
assigned irq for event_device in event_dev->irq
calculated timer.hz_period for CLOCK_EVT_MODE_PERIODIC at init
deleted spare call of keystone_timer_config() in keystone_timer_init()
*
Ivan Khoronzhuk (3):
clocksource: timer-keystone: introduce clockso
.
Signed-off-by: Ivan Khoronzhuk
---
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-keystone.c | 233 +++
2 files changed, 234 insertions(+)
create mode 100644 drivers/clocksource/timer-keystone.c
diff --git a/drivers/clocksource/Makefile b
(unchained mode) of each other.
It is global timer is a free running up-counter and can generate interrupt
when the counter reaches preset counter values.
Documentation:
http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
Signed-off-by: Ivan Khoronzhuk
---
.../bindings/timer/ti,keystone-timer.txt
Add keystone timer entry to keystone device tree.
This 64-bit timer is used as backup clock event device.
Signed-off-by: Ivan Khoronzhuk
---
arch/arm/boot/dts/keystone-clocks.dtsi | 10 ++
arch/arm/boot/dts/keystone.dtsi| 7 +++
2 files changed, 17 insertions(+)
diff --git
Reviewed-by: Stephen Boyd
Acked-by: Santosh shilimkar
On 02/04/2014 01:30 PM, Ivan Khoronzhuk wrote:
Add broadcast clock-event device for the Keystone arch.
The timer can be configured as a general-purpose 64-bit timer,
dual general-purpose 32-bit timers. When configured as dual 32-bit
Sorry I forgot to add
Acked-by: Santosh Shilimkar
On 02/04/2014 01:30 PM, Ivan Khoronzhuk wrote:
This patch provides bindings for the 64-bit timer in the KeyStone
architecture devices. The timer can be configured as a general-purpose 64-bit
timer, dual general-purpose 32-bit timers. When
/writel_relaxed functions.
See:
http://www.spinics.net/lists/arm-kernel/msg294941.html
On 02/04/2014 06:24 PM, Thomas Gleixner wrote:
On Tue, 4 Feb 2014, Ivan Khoronzhuk wrote:
+ keystone_timer_writel(off, TCR);
+ /* here we have to be sure the timer has been disabled */
+
Yes. I'll send with __iowmb() instead of wmb().
On 02/05/2014 12:15 AM, Santosh Shilimkar wrote:
On Tuesday 04 February 2014 03:17 PM, Thomas Gleixner wrote:
On Tue, 4 Feb 2014, Ivan Khoronzhuk wrote:
Please do not top post.
It was so in v1. But it was decided to use explicit m
Add keystone timer entry to keystone device tree.
This 64-bit timer is used as backup clock event device.
Signed-off-by: Ivan Khoronzhuk
---
arch/arm/boot/dts/keystone-clocks.dtsi | 10 ++
arch/arm/boot/dts/keystone.dtsi| 7 +++
2 files changed, 17 insertions(+)
diff --git
(unchained mode) of each other.
It is global timer is a free running up-counter and can generate interrupt
when the counter reaches preset counter values.
Documentation:
http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
Acked-by: Santosh Shilimkar
Signed-off-by: Ivan Khoronzhuk
---
.../bindings/timer
g() returns -1.
used request_irq() instead of setup_irq()
assigned irq for event_device in event_dev->irq
calculated timer.hz_period for CLOCK_EVT_MODE_PERIODIC at init
deleted spare call of keystone_timer_config() in keystone_timer_init()
Ivan Khoronzhuk (3):
.
Reviewed-by: Stephen Boyd
Acked-by: Santosh shilimkar
Signed-off-by: Ivan Khoronzhuk
---
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-keystone.c | 233 +++
2 files changed, 234 insertions(+)
create mode 100644 drivers/clocksource/timer
On 02/05/2014 04:39 PM, Rob Herring wrote:
On Wed, Feb 5, 2014 at 7:47 AM, Ivan Khoronzhuk wrote:
This patch provides bindings for the 64-bit timer in the KeyStone
architecture devices. The timer can be configured as a general-purpose 64-bit
timer, dual general-purpose 32-bit timers. When
On 02/05/2014 07:41 PM, Rob Herring wrote:
On Wed, Feb 5, 2014 at 10:18 AM, Ivan Khoronzhuk wrote:
On 02/05/2014 04:39 PM, Rob Herring wrote:
On Wed, Feb 5, 2014 at 7:47 AM, Ivan Khoronzhuk
wrote:
This patch provides bindings for the 64-bit timer in the KeyStone
architecture devices. The
gs for AEMIF driver
added ti.cs-chipselect property instead of representing chipselect
number in cs node name.
Ivan Khoronzhuk (2):
memory: ti-aemif: introduce AEMIF driver
memory: ti-aemif: add bindings for AEMIF driver
.../bindings/memory-controllers/ti-aemif.txt | 21
selects with 64M byte access
per chip select.
Synchronous memories such as DDR1 SD RAM, SDR SDRAM and Mobile SDR
are not supported.
This controller is used on SoCs like Davinci, Keysone2
Acked-by: Santosh Shilimkar
Signed-off-by: Ivan Khoronzhuk
---
drivers/memory/Kconfig| 11 ++
drivers
emory ranges to it,
as result we can't encode CS number in "reg" for AEMIF child devices
(NAND/NOR/etc), as it will break bindings compatibility.
In this patch, NAND node is used just as an example of child node.
Signed-off-by: Ivan Khoronzhuk
---
.../bindings/memory-contro
emoved compatible property from cs node, it makes code simpler
v1..v2:
- memory: ti-aemif: introduce AEMIF driver
- memory: ti-aemif: add bindings for AEMIF driver
added ti.cs-chipselect property instead of representing chipselect
number in cs node name.
Ivan Khoronzhuk (2):
mem
emory ranges to it,
as result we can't encode CS number in "reg" for AEMIF child devices
(NAND/NOR/etc), as it will break bindings compatibility.
In this patch, NAND node is used just as an example of child node.
Signed-off-by: Ivan Khoronzhuk
---
.../bindings/memory-control
selects with 64M byte access
per chip select.
Synchronous memories such as DDR1 SD RAM, SDR SDRAM and Mobile SDR
are not supported.
This controller is used on SoCs like Davinci, Keysone2
Signed-off-by: [initial author] Murali Karicheri
Signed-off-by: Ivan Khoronzhuk
---
drivers/memory/Kconfig
, so use it in
order to set timeout period.
Signed-off-by: Ivan Khoronzhuk
Acked-by: Santosh Shilimkar
---
drivers/watchdog/Kconfig |2 +
drivers/watchdog/davinci_wdt.c | 152 ++--
2 files changed, 39 insertions(+), 115 deletions(-)
diff --git a
use consistent formatting
- watchdog: davinci: reuse driver for keystone arch
use consistent formatting
- watchdog: davinci: add "clocks" property
merged with above patch
Ivan Khoronzhuk (6):
watchdog: davinci: change driver to use WDT core
watchdog: davinci:
Currently, the davinci watchdog can be read while counting,
so we can add ability to report the remaining time before
the system will reboot.
Signed-off-by: Ivan Khoronzhuk
Acked-by: Santosh Shilimkar
---
drivers/watchdog/davinci_wdt.c | 26 ++
1 file changed, 26
Since Davinci WDT has been switched to use WDT core, it became able
to support timeout-sec property, so add it to it's binding description.
Signed-off-by: Ivan Khoronzhuk
Acked-by: Santosh Shilimkar
---
.../devicetree/bindings/watchdog/davinci-wdt.txt |4
1 file chang
Add watchdog entry to keystone device tree.
Signed-off-by: Ivan Khoronzhuk
Acked-by: Guenter Roeck
---
arch/arm/boot/dts/keystone.dts |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dts
index 100bdf5..a6e5f91 100644
--- a
The keystone arch use the same IP watchdog, so add "ti,keystone-wdt"
compatible and correct identity.
The Keystone arch is using clocks in DT and source clock for watchdog
has to be specified, so add this to binding.
Signed-off-by: Ivan Khoronzhuk
Acked-by: Santosh
Some SoCs, like Keystone 2, can support more than one WDT and each
watchdog device has to use it's own base address, clock source,
watchdog device, so add new davinci_wdt_device structure to hold
device data.
Signed-off-by: Ivan Khoronzhuk
Acked-by: Santosh Shilimkar
Reviewed-by: Guenter
On 02/06/2014 02:35 AM, Josh Cartwright wrote:
Hey Ivan-
On Wed, Feb 05, 2014 at 03:47:38PM +0200, Ivan Khoronzhuk wrote:
Add broadcast clock-event device for the Keystone arch.
The timer can be configured as a general-purpose 64-bit timer,
dual general-purpose 32-bit timers. When configured
On 02/06/2014 01:36 AM, Rob Herring wrote:
On Wed, Feb 5, 2014 at 12:52 PM, Ivan Khoronzhuk wrote:
On 02/05/2014 07:41 PM, Rob Herring wrote:
On Wed, Feb 5, 2014 at 10:18 AM, Ivan Khoronzhuk
wrote:
On 02/05/2014 04:39 PM, Rob Herring wrote:
On Wed, Feb 5, 2014 at 7:47 AM, Ivan Khoronzhuk
On 02/05/2014 10:27 PM, Thomas Gleixner wrote:
On Wed, 5 Feb 2014, Ivan Khoronzhuk wrote:
+ /* here we have to be sure the timer has been disabled */
Sigh. This is not a proper explanation for a barrier, really. You want
to explain what it serializes against what. i.e. you want to
ny more
in case of an unsupported mode the keystone_timer_config() returns -1.
used request_irq() instead of setup_irq()
assigned irq for event_device in event_dev->irq
calculated timer.hz_period for CLOCK_EVT_MODE_PERIODIC at init
deleted spare call of keystone_timer_
(unchained mode) of each other.
It is global timer is a free running up-counter and can generate interrupt
when the counter reaches preset counter values.
Documentation:
http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
Acked-by: Rob Herring
Acked-by: Santosh Shilimkar
Signed-off-by: Ivan Khoronzhuk
.
Reviewed-by: Stephen Boyd
Acked-by: Santosh shilimkar
Signed-off-by: Ivan Khoronzhuk
---
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-keystone.c | 244 +++
2 files changed, 245 insertions(+)
create mode 100644 drivers/clocksource/timer
Add keystone timer entry to keystone device tree.
This 64-bit timer is used as backup clock event device.
Signed-off-by: Ivan Khoronzhuk
---
arch/arm/boot/dts/keystone-clocks.dtsi | 10 ++
arch/arm/boot/dts/keystone.dtsi| 7 +++
2 files changed, 17 insertions(+)
diff --git
watchdog: davinci: add GET_STATUS option support
dropped
- watchdog: davinci: add "timeout-sec" property
use consistent formatting
- watchdog: davinci: reuse driver for keystone arch
use consistent formatting
- watchdog: davinci: add "clocks" property
me
Some SoCs, like Keystone 2, can support more than one WDT and each
watchdog device has to use it's own base address, clock source,
watchdog device, so add new davinci_wdt_device structure to hold
device data.
Acked-by: Santosh Shilimkar
Reviewed-by: Guenter roeck
Signed-off-by: Ivan Khoro
The keystone arch uses the same IP watchdog, so add "ti,keystone-wdt"
compatible and correct identity.
The Keystone arch is using clocks in DT and source clock for watchdog
has to be specified, so add this to binding.
Acked-by: Santosh Shilimkar
Reviewed-by: Guenter Roeck
Signed-of
core, so use it in
order to set timeout period.
Acked-by: Santosh Shilimkar
Reviewed-by: Guenter Roeck
Signed-off-by: Ivan Khoronzhuk
---
drivers/watchdog/Kconfig |1 +
drivers/watchdog/davinci_wdt.c | 147 ++--
2 files changed, 36 insertions
Since Davinci WDT has been switched to use WDT core, it became able
to support timeout-sec property, so add it to it's binding description.
Acked-by: Santosh Shilimkar
Reviewed-by: Guenter Roeck
Signed-off-by: Ivan Khoronzhuk
---
.../devicetree/bindings/watchdog/davinci-wdt.txt |
Currently, the davinci watchdog can be read while counting,
so we can add ability to report the remaining time before
the system will reboot.
Acked-by: Santosh Shilimkar
Reviewed-by: Guenter Roeck
Signed-off-by: Ivan Khoronzhuk
---
drivers/watchdog/davinci_wdt.c | 26
core, so use it in
order to set timeout period.
Davinci WDT can't be stopped and once it's expired - it can be
rearmed only after hardware reset, that's why nowayout feature
is enforced.
Acked-by: Santosh Shilimkar
Reviewed-by: Guenter Roeck
Signed-off-by: Ivan Khoronzhuk
---
d
Extend bindings for davinci_nand driver to be more clear.
This is clarification only, without semantic changes.
Reviewed-by: Grygorii Strashko
Reviewed-by: Taras Kondratiuk
Signed-off-by: Ivan Khoronzhuk
---
.../devicetree/bindings/mtd/davinci-nand.txt | 77 ++--
1
g has to be made with core mechanism.
Acked-by: Santosh Shilimkar
Reviewed-by: Grygorii Strashko
Reviewed-by: Taras Kondratiuk
Signed-off-by: Ivan Khoronzhuk
---
drivers/mtd/nand/davinci_nand.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/davinci_nan
-off-by: Ivan Khoronzhuk
---
.../devicetree/bindings/mtd/davinci-nand.txt | 25
drivers/mtd/nand/davinci_nand.c| 11 ++---
2 files changed, 28 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/davinci-nand.txt
b
cannot request it twice, just ioremap.
Acked-by: Santosh Shilimkar
Reviewed-by: Grygorii Strashko
Reviewed-by: Taras Kondratiuk
Signed-off-by: Ivan Khoronzhuk
---
drivers/mtd/nand/davinci_nand.c |8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand
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