When SWIOTLB is configured, if without this patch kernel compilation
fails.
Signed-off-by: Huacai Chen
Signed-off-by: Hongliang Tao
Signed-off-by: Hua Yan
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/radeon/radeon_ttm.c |4
1 files changed, 4 insertions(+), 0 deletions
On Mon, Aug 13, 2012 at 3:00 PM, Paul Menzel
wrote:
> Dear Chen,
>
>
> thanks for your patch.
>
> Firstly, is Chen your first or last name? If it is your first name, your
> From address should be switched.
Chen is may last name.
>
> Am Montag, den 13.08.2012, 10:0
On Mon, Aug 13, 2012 at 3:50 PM, Paul Menzel
wrote:
> Dear Huacai,
>
>
> Am Montag, den 13.08.2012, 15:16 +0800 schrieb Huacai Chen:
>> On Mon, Aug 13, 2012 at 3:00 PM, Paul Menzel wrote:
>
>> > thanks for your patch.
>> >
>> > Firstly, is Chen y
OK, I will improve the code.
On Mon, Aug 13, 2012 at 4:00 PM, Takashi Iwai wrote:
> At Sat, 11 Aug 2012 17:32:19 +0800,
> Huacai Chen wrote:
>>
>> Lemote A1004(Laptop) and A1205(All-In-One) use Conexant's hda codec,
>> this patch modify patch_conexant.c to add Lemot
type 'struct device *'
V2:
1, Add compilation error messages;
2, Make the From: address the same as Signed-off-by address.
Signed-off-by: Huacai Chen
Signed-off-by: Hongliang Tao
Signed-off-by: Hua Yan
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/radeon/radeon_ttm.c |4 +
thus
disable_nonboot_cpus() hangs. Therefore, we make this patch to avoid
poweroff failure.
V2:
Make the From: address the same as Signed-off-by address.
Signed-off-by: Huacai Chen
Signed-off-by: Hongliang Tao
Signed-off-by: Hua Yan
Cc: Yong Zhang
Cc: sta...@vger.kernel.org
---
arch/mips/kernel/proc
Most of the code are copied from arch/mips/cavium-octeon/dma-octeon.c
and they work well.
Anyway, I'll try your suggestions, thank you.
On Tue, Aug 14, 2012 at 1:54 AM, Konrad Rzeszutek Wilk
wrote:
>> +static void *loongson_dma_alloc_coherent(struct device *dev, size_t size,
>> +
Hi, David,
Seems like you are the original author of code in
arch/mips/cavium-octeon/dma-octeon.c. Could you please tell me why we
need mb() in alloc_coherent(), map_page(), map_sg()? It seems like
because of cache coherency (CPU write some data, then map the page for
a device, if without mb(), th
On Tue, Aug 14, 2012 at 7:48 PM, Ralf Baechle wrote:
> On Mon, Aug 13, 2012 at 08:52:24PM +0800, Huacai Chen wrote:
>
>> When poweroff machine, kernel_power_off() call disable_nonboot_cpus().
>> And if we have HOTPLUG_CPU configured, disable_nonboot_cpus() is not an
>> em
On Tue, Aug 14, 2012 at 1:54 AM, Konrad Rzeszutek Wilk
wrote:
>> +static void *loongson_dma_alloc_coherent(struct device *dev, size_t size,
>> + dma_addr_t *dma_handle, gfp_t gfp, struct
>> dma_attrs *attrs)
>> +{
>> + void *ret;
>> +
>> + if (dma_alloc_from_co
On Thu, Aug 16, 2012 at 5:31 AM, Ralf Baechle wrote:
> On Sat, Aug 11, 2012 at 05:32:18PM +0800, Huacai Chen wrote:
>
>> Subject: [PATCH V5 13/18] drm: Define SAREA_MAX for Loongson (PageSize =
>> 16KB).
>
> But your code doesn't define it just for Loongsson as
On Thu, Aug 16, 2012 at 4:24 AM, Ralf Baechle wrote:
> On Mon, Aug 13, 2012 at 01:54:47PM -0400, Konrad Rzeszutek Wilk wrote:
>
>> > +static void *loongson_dma_alloc_coherent(struct device *dev, size_t size,
>> > + dma_addr_t *dma_handle, gfp_t gfp, struct
>> > dma_attrs
On Thu, Aug 16, 2012 at 9:58 AM, Matt Turner wrote:
> On Sat, Aug 11, 2012 at 2:32 AM, Huacai Chen wrote:
>> Signed-off-by: Huacai Chen
>> Signed-off-by: Hongliang Tao
>> Signed-off-by: Hua Yan
>> Cc: dri-de...@lists.freedesktop.org
>> ---
>> includ
On Tue, Aug 14, 2012 at 7:48 PM, Ralf Baechle wrote:
> On Mon, Aug 13, 2012 at 08:52:24PM +0800, Huacai Chen wrote:
>
>> When poweroff machine, kernel_power_off() call disable_nonboot_cpus().
>> And if we have HOTPLUG_CPU configured, disable_nonboot_cpus() is not an
>> em
, Increase the default boost of internal mic for Lemote A1004.
8, Fix a #ifdef issue in dma-coherence.h.
9, Some other small fixes.
Huacai Chen(15):
MIPS: Loongson: Add basic Loongson-3 definition.
MIPS: Loongson: Add basic Loongson-3 CPU support.
MIPS: Loongson: Introduce and use cpu_has_c
Add four Loongson-3 based machine types:
MACH_LEMOTE_A1004/MACH_LEMOTE_A1201 are laptops;
MACH_LEMOTE_A1101 is mini-itx;
MACH_LEMOTE_A1205 is all-in-one machine.
The most significant differrent between A1004/A1201 and A1101/A1205 is
the laptops have EC but others don't.
Signed-off-by: H
except 2E/2F series.
Signed-off-by: Huacai Chen
Signed-off-by: Hongliang Tao
Signed-off-by: Hua Yan
---
arch/mips/include/asm/mach-loongson/boot_param.h | 151 ++
arch/mips/include/asm/mach-loongson/loongson.h |4 +-
arch/mips/loongson/common/env.c
Signed-off-by: Huacai Chen
Signed-off-by: Hongliang Tao
Signed-off-by: Hua Yan
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/drm_vm.c |2 +-
drivers/gpu/drm/ttm/ttm_bo_util.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm
Signed-off-by: Huacai Chen
Signed-off-by: Hongliang Tao
Signed-off-by: Hua Yan
---
arch/mips/configs/loongson3_defconfig | 283 +
1 files changed, 283 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/configs/loongson3_defconfig
diff --git a/arch
KSEG1 (both uncached and
unmmaped).
2, The default clocksource of Loongson is MIPS. Since clock source is a
global device, timekeeping need the CP0' Count registers of each core
be synchronous. Thus, when a core is up, we use a SMP_ASK_C0COUNT IPI
to ask Core-0's Count.
Signed
this patch we make changes to avoid boot failure.
Signed-off-by: Huacai Chen
Signed-off-by: Hongliang Tao
Signed-off-by: Hua Yan
---
arch/mips/loongson/common/init.c |5 +
arch/mips/loongson/common/setup.c |8 +-
arch/mips/loongson/loongson-3/Makefile |2 +
arch
Added Kconfig options include: Loongson-3 CPU and machine definition,
CPU cache features, UEFI-like firmware interface, HT-linked PCI, and
big memory support.
Signed-off-by: Huacai Chen
Signed-off-by: Hongliang Tao
Signed-off-by: Hua Yan
---
arch/mips/Kconfig | 26
Lemote A1004(Laptop) and A1205(All-In-One) use Conexant's hda codec,
this patch modify patch_conexant.c to add Lemote specific code.
Both A1004 and A1205 use the same pin configurations, but A1004 need
to increase the default boost of internal mic.
Signed-off-by: Jie Chen
Signed-off-by: H
Loongson-3 maintains cache coherency by hardware. So we introduce a cpu
feature named cpu_has_coherent_cache and use it to modify MIPS's cache
flushing functions.
Signed-off-by: Huacai Chen
Signed-off-by: Hongliang Tao
Signed-off-by: Hua Yan
---
arch/mips/include/asm/cacheflush.h |
ide a
platform-specific dma_map_ops::set_dma_mask() to make sure each
driver's dma_mask and coherent_dma_mask is below 32-bit.
Signed-off-by: Huacai Chen
Signed-off-by: Hongliang Tao
Signed-off-by: Hua Yan
---
arch/mips/include/asm/dma-mapping.h|5 +
.../mips/include/asm/mac
on-3A(including so-called Loongson-2Gq), they are
64-bit multi-core MIPS CPUs.
Signed-off-by: Huacai Chen
Signed-off-by: Hongliang Tao
Signed-off-by: Hua Yan
---
arch/mips/include/asm/addrspace.h|6 ++
arch/mips/include/asm/cpu.h |5 +++--
UARTs:
CPU UART: REG_BASE + OFFSET;
LPC UART: LIO1_BASE + OFFSET;
PCI UART: PCIIO_BASE + OFFSET.
Since LPC UART are linked in "Local Bus", both CPU UART and LPC UART
are called "CPU provided serial port".
Signed-off-by: Huacai Chen
Signed-off-by: Hongliang Tao
Signed-off-by: Hua
ion
registers of HT1 controller.
Signed-off-by: Huacai Chen
Signed-off-by: Hongliang Tao
Signed-off-by: Hua Yan
---
arch/mips/include/asm/mach-loongson/irq.h | 24 +++
arch/mips/include/asm/mach-loongson/loongson.h |9 +++
arch/mips/loongson/Makefile|6 ++
Basic Loongson-3 CPU support include CPU probing and TLB/cache
initializing.
Signed-off-by: Huacai Chen
Signed-off-by: Hongliang Tao
Signed-off-by: Hua Yan
---
arch/mips/kernel/Makefile|1 +
arch/mips/kernel/cpu-probe.c | 14 +++---
arch/mips/lib/Makefile |1 +
arch
Loongson family machines use Hyper-Transport bus for inter-core
connection and device connection. The PCI bus is a subordinate
linked at HT1.
With UEFI-like firmware interface, We don't need fixup for PCI irq
routing.
Signed-off-by: Huacai Chen
Signed-off-by: Hongliang Tao
Signed-off-by
I think they will go through mips tree.
On Fri, Aug 17, 2012 at 5:09 PM, Takashi Iwai wrote:
> At Fri, 17 Aug 2012 16:43:32 +0800,
> Huacai Chen wrote:
>>
>> Lemote A1004(Laptop) and A1205(All-In-One) use Conexant's hda codec,
>> this patch modify patch_conexant.
On Mon, Oct 8, 2012 at 4:22 PM, Takashi Iwai wrote:
> At Fri, 5 Oct 2012 21:25:09 +0800,
> Huacai Chen wrote:
>>
>> Lemote A1004(Laptop) and A1205(All-In-One) use Conexant's hda codec,
>> this patch modify patch_conexant.c to add Lemote specific code.
>>
>&
n
Cc: Andy Gross
Cc: Mark A. Greer
Cc: Robert Baldyga
Cc: Marek Szyprowski
Signed-off-by: Huacai Chen
---
drivers/infiniband/hw/mthca/mthca_main.c | 2 +-
drivers/media/v4l2-core/videobuf2-dma-contig.c | 2 +-
drivers/net/ethernet/broadcom/b44.c| 8 +++
drivers
e (no writeback) will cause data corruption.
Cc: sta...@vger.kernel.org
Signed-off-by: Huacai Chen
---
drivers/scsi/scsi_lib.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c
index 9cf6a80..19abc2e 100644
--- a/drivers
, cache_invalidate (no writeback) will cause
data corruption.
Cc: sta...@vger.kernel.org
Signed-off-by: Huacai Chen
---
drivers/ata/libata-core.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index ee4c1ec
data, cache_invalidate (no writeback) will cause data corruption.
Cc: sta...@vger.kernel.org
Signed-off-by: Huacai Chen
---
drivers/scsi/libsas/sas_expander.c | 93 +++---
1 file changed, 57 insertions(+), 36 deletions(-)
diff --git a/drivers/scsi/libsas/sas_expander.c
b/drivers
Currently, MIPS is an architecture which support coherent & noncoherent
devices co-exist. So implement get_cache_alignment() function pointer
in 'struct dma_map_ops' to return different dma alignments.
Cc: sta...@vger.kernel.org
Signed-off-by: Huacai Chen
---
arch/mips/cav
Hi, Willy,
Does these two patches really needed for 3.10? They are marked for 4.4 and 4.6.
ext4: avoid deadlock when expanding inode size
ext4: in ext4_seek_{hole,data}, return -ENXIO for negative offsets
Huacai
, so fix them
together. If without this fix, compressed booting of these archs will
fail because stack checking is enabled by default (>=4.16).
V2: Fix build on ARM.
Cc: sta...@vger.kernel.org
Signed-off-by: Huacai Chen
---
arch/arm/boot/compressed/head.S| 4
arch/arm/boot/compres
Hi, Yoshinori, Rich and SuperH developers,
I'm not familiar with SuperH assembly, but SuperH has the same bug
obviously. Could you please fix that?
Huacai
On Mon, Mar 12, 2018 at 10:04 AM, Huacai Chen wrote:
> Call __stack_chk_guard_setup() in decompress_kernel() is too late that
On Mon, Nov 12, 2018 at 3:29 AM Greg Kroah-Hartman
wrote:
>
> On Fri, Oct 19, 2018 at 09:31:29PM +0800, Huacai Chen wrote:
> > Commit 448a5a552f336bd7b847b1951 ("drivers: base: cacheinfo: use OF
> > property_read_u32 instead of get_property,read_number") makes cache
&g
e, Jul 10, 2018 at 12:49 AM, Paul Burton wrote:
> Hi Huacai,
>
> On Mon, Jul 09, 2018 at 10:26:38AM +0800, Huacai Chen wrote:
>> After commit 7f56b58a92aaf2c ("locking/mcs: Use smp_cond_load_acquire()
>> in MCS spin loop") Loongson-3 fails to boot. This is because Loong
as old kernels.
Fixes: 448a5a552f33 ("drivers: base: cacheinfo: use OF property_read_u32
instead of get_property,read_number")
Cc: sta...@vger.kernel.org
Signed-off-by: Huacai Chen
Reviewed-by: Sudeep Holla
---
V2: Add Cc and Reviewed-by
V3: Add ChangeLog
drivers/base/cacheinfo.c | 6
se on Loongson).
Cc: sta...@vger.kernel.org
Signed-off-by: Huacai Chen
---
V2: Update commit message.
drivers/scsi/lpfc/lpfc_compat.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/lpfc/lpfc_compat.h b/drivers/scsi/lpfc/lpfc_compat.h
index 43cf46a..0cd1e3c
wig
Cc: Michael Hernandez
Signed-off-by: Huacai Chen
---
kernel/irq/affinity.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/kernel/irq/affinity.c b/kernel/irq/affinity.c
index 45b68b4..9b766eb 100644
--- a/kernel/irq/affinity.c
+++ b/kernel/irq/affin
as old kernels.
Signed-off-by: Huacai Chen
---
drivers/base/cacheinfo.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index 5d5b598..dd6a685 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
cheinfo.c
Regards,
Huacai
On Wed, Oct 17, 2018 at 5:35 PM Sudeep Holla wrote:
>
> On Wed, Oct 17, 2018 at 09:26:03AM +0800, Huacai Chen wrote:
> > Commit 448a5a552f336bd7b847b1951 ("drivers: base: cacheinfo: use OF
> > property_read_u32 instead of get_property,read_n
as old kernels.
Fixes: 448a5a552f33 ("drivers: base: cacheinfo: use OF property_read_u32
instead of get_property,read_number")
Signed-off-by: Huacai Chen
Reviewed-by: Sudeep Holla
---
drivers/base/cacheinfo.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/d
On Wed, Jul 18, 2018 at 1:52 AM, Paul Burton wrote:
> Hi Huacai,
>
> On Fri, Jul 13, 2018 at 03:37:57PM +0800, Huacai Chen wrote:
>> Linux expects that if a CPU modifies a memory location, then that
>> modification will eventually become visible to other CPUs in the system
Hi, Bibo,
On Mon, Jan 22, 2024 at 6:03 PM Bibo Mao wrote:
>
> This patch refines ipi handling on LoongArch platform, there are
> three changes with this patch.
> 1. Add generic get_percpu_irq api, replace some percpu irq function
> such as get_ipi_irq/get_pmc_irq/get_timer_irq with get_percpu_irq
Hi, Bibo,
On Mon, Jan 22, 2024 at 6:03 PM Bibo Mao wrote:
>
> On LoongArch system, ipi hw uses iocsr registers, there is one iocsr
> register access on ipi sender and two iocsr access on ipi receiver
> which is ipi interrupt handler. On VM mode all iocsr registers
> accessing will trap into hyper
Hi, Bibo,
Without this patch I can also create a SMP VM, so what problem does
this patch want to solve?
Huacai
On Mon, Jan 22, 2024 at 6:03 PM Bibo Mao wrote:
>
> Physical cpuid is used to irq routing for irqchips such as ipi/msi/
> extioi interrupt controller. And physical cpuid is stored at C
Hi, Oreoluwa,
On Sat, Feb 10, 2024 at 8:29 AM Oreoluwa Babatunde
wrote:
>
> The platform_init() function which is called during device bootup
> contains a few calls to memblock_alloc().
> This is an issue because these allocations are done before reserved
> memory regions are set aside in arch_me
Hi, Oreoluwa,
On Thu, Feb 15, 2024 at 5:31 AM Oreoluwa Babatunde
wrote:
>
>
> On 2/14/2024 5:03 AM, Huacai Chen wrote:
> > Hi, Oreoluwa,
> >
> > On Sat, Feb 10, 2024 at 8:29 AM Oreoluwa Babatunde
> > wrote:
> >> The platform_init() function which is c
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
>
> This patch refines ipi handling on LoongArch platform, there are
> three changes with this patch.
> 1. Add generic get_percpu_irq() api, replace some percpu irq functions
> such as get_ipi_irq()/get_pmc_irq()/get_timer_irq() with get_p
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
>
> On LoongArch system, hypercall instruction is supported when system
> runs on VM mode. This patch adds dummy function with hypercall
> instruction emulation, rather than inject EXCCODE_INE invalid
> instruction exception.
>
> Signed-of
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
>
> The patch adds paravirt interface for guest kernel, function
> pv_guest_initi() firstly checks whether system runs on VM mode. If kernel
> runs on VM mode, it will call function kvm_para_available() to detect
> whether current VMM is K
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:20 AM Bibo Mao wrote:
>
> On LoongArch system, ipi hw uses iocsr registers, there is one iocsr
> register access on ipi sending, and two iocsr access on ipi receiving
> which is ipi interrupt handler. On VM mode all iocsr registers
> accessing will cause VM to
On Mon, Feb 19, 2024 at 12:18 PM maobibo wrote:
>
>
>
> On 2024/2/19 上午10:45, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Thu, Feb 1, 2024 at 11:20 AM Bibo Mao wrote:
> >>
> >> On LoongArch system, ipi hw uses iocsr registers, there is one iocsr
&g
On Mon, Feb 19, 2024 at 12:11 PM maobibo wrote:
>
>
>
> On 2024/2/19 上午10:42, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
> >>
> >> The patch adds paravirt interface for guest kernel, function
> >
On Mon, Feb 19, 2024 at 3:37 PM maobibo wrote:
>
>
>
> On 2024/2/19 下午3:16, Huacai Chen wrote:
> > On Mon, Feb 19, 2024 at 12:18 PM maobibo wrote:
> >>
> >>
> >>
> >> On 2024/2/19 上午10:45, Huacai Chen wrote:
> >>> Hi,
On Mon, Feb 19, 2024 at 5:21 PM maobibo wrote:
>
>
>
> On 2024/2/19 下午4:48, Huacai Chen wrote:
> > On Mon, Feb 19, 2024 at 12:11 PM maobibo wrote:
> >>
> >>
> >>
> >> On 2024/2/19 上午10:42, Huacai Chen wrote:
> >>> Hi,
Hi, Bibo,
On Thu, Feb 22, 2024 at 11:28 AM Bibo Mao wrote:
>
> Instruction cpucfg can be used to get processor features. And there
> is trap exception when it is executed in VM mode, and also it is
> to provide cpu features to VM. On real hardware cpucfg area 0 - 20
> is used. Here one specified
Hi, Bibo,
On Thu, Feb 22, 2024 at 11:28 AM Bibo Mao wrote:
>
> Paravirt interface pv_ipi_init() is added here for guest kernel, it
> firstly checks whether system runs on VM mode. If kernel runs on VM mode,
> it will call function kvm_para_available() to detect current VMM type.
> Now only KVM VM
Hi, Bibo,
On Thu, Feb 22, 2024 at 11:28 AM Bibo Mao wrote:
>
> On LoongArch system, ipi hw uses iocsr registers, there is one iocsr
> register access on ipi sending, and two iocsr access on ipi receiving
> which is ipi interrupt handler. On VM mode all iocsr accessing will
> cause VM to trap into
On Mon, Feb 26, 2024 at 10:04 AM maobibo wrote:
>
>
>
> On 2024/2/24 下午5:13, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Thu, Feb 22, 2024 at 11:28 AM Bibo Mao wrote:
> >>
> >> Instruction cpucfg can be used to get processor features. And there
erui wrote:
> >> On 2/27/24 11:14, maobibo wrote:
> >>>
> >>>
> >>> On 2024/2/27 上午4:02, Jiaxun Yang wrote:
> >>>>
> >>>>
> >>>> 在2024年2月26日二月 上午8:04，maobibo写道：
> >>>>> On 20
Hi, Bibo,
On Tue, Apr 30, 2024 at 9:45 AM Bibo Mao wrote:
>
> Percpu struct kvm_steal_time is added here, its size is 64 bytes and
> also defined as 64 bytes, so that the whole structure is in one physical
> page.
>
> When vcpu is onlined, function pv_enable_steal_time() is called. This
> functio
Hi, Bibo,
I have done an off-list discussion with some KVM experts, and they
think user-space have its right to know PV features, so cpucfg
solution is acceptable.
And I applied this series with some modifications at
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git/lo
Hi, Bibo,
On Sun, Apr 28, 2024 at 6:05 PM Bibo Mao wrote:
>
> Physical cpuid is used for interrupt routing for irqchips such as
> ipi/msi/extioi interrupt controller. And physical cpuid is stored
> at CSR register LOONGARCH_CSR_CPUID, it can not be changed once vcpu
> is created and physical cpui
Hi, Bibo,
On Sun, Apr 28, 2024 at 6:05 PM Bibo Mao wrote:
>
> PARAVIRT option and pv ipi is added on guest kernel side, function
> pv_ipi_init() is to add ipi sending and ipi receiving hooks. This function
> firstly checks whether system runs on VM mode. If kernel runs on VM mode,
> it will call
Hi, Bibo,
On Sun, Apr 28, 2024 at 6:05 PM Bibo Mao wrote:
>
> On LoongArch system, there is hypercall instruction special for
> virtualization. When system executes this instruction on host side,
> there is illegal instruction exception reported, however it will
> trap into host when it is execut
On Mon, May 6, 2024 at 3:00 PM maobibo wrote:
>
>
>
> On 2024/5/6 上午9:53, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Sun, Apr 28, 2024 at 6:05 PM Bibo Mao wrote:
> >>
> >> PARAVIRT option and pv ipi is added on guest kernel side, function
Hi, Bibo,
On Mon, May 6, 2024 at 2:36 PM maobibo wrote:
>
>
>
> On 2024/5/6 上午9:49, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Sun, Apr 28, 2024 at 6:05 PM Bibo Mao wrote:
> >>
> >> Physical cpuid is used for interrupt routing for irqchips such
On Mon, May 6, 2024 at 4:18 PM maobibo wrote:
>
>
>
> On 2024/5/6 下午3:06, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Mon, May 6, 2024 at 2:36 PM maobibo wrote:
> >>
> >>
> >>
> >> On 2024/5/6 上午9:49, Huacai Chen wrote:
> >
On Mon, May 6, 2024 at 5:35 PM maobibo wrote:
>
>
>
> On 2024/5/6 下午4:59, Huacai Chen wrote:
> > On Mon, May 6, 2024 at 4:18 PM maobibo wrote:
> >>
> >>
> >>
> >> On 2024/5/6 下午3:06, Huacai Chen wrote:
> >>> H
On Mon, May 6, 2024 at 6:05 PM maobibo wrote:
>
>
>
> On 2024/5/6 下午5:40, Huacai Chen wrote:
> > On Mon, May 6, 2024 at 5:35 PM maobibo wrote:
> >>
> >>
> >>
> >> On 2024/5/6 下午4:59, Huacai Chen wrote:
> >>> On Mon, May 6, 2024 at
On Tue, May 7, 2024 at 9:40 AM maobibo wrote:
>
>
>
> On 2024/5/6 下午10:17, Huacai Chen wrote:
> > On Mon, May 6, 2024 at 6:05 PM maobibo wrote:
> >>
> >>
> >>
> >> On 2024/5/6 下午5:40, Huacai Chen wrote:
> >>> On Mon, May 6, 2024
On Tue, May 7, 2024 at 11:06 AM maobibo wrote:
>
>
>
> On 2024/5/7 上午10:05, Huacai Chen wrote:
> > On Tue, May 7, 2024 at 9:40 AM maobibo wrote:
> >>
> >>
> >>
> >> On 2024/5/6 下午10:17, Huacai Chen wrote:
> >>> On Mon, May 6, 202
On Sat, Jun 29, 2024 at 9:40 PM Oleg Nesterov wrote:
>
> On 06/29, Tiezhu Yang wrote:
> >
> > On Thu, 27 Jun 2024 19:38:06 +0200
> > Oleg Nesterov wrote:
> >
> > ...
> >
> > > > > +arch_initcall(check_emit_break);
> > > > > +
> > > >
> > > > I wouldn't even bother with this, but whatever.
> > >
>
Hi, Oleg,
On Sat, Jun 29, 2024 at 11:05 PM Oleg Nesterov wrote:
>
> LoongArch defines UPROBE_SWBP_INSN as a function call and this breaks
> arch_uprobe_trampoline() which uses it to initialize a static variable.
>
> Add the new "__builtin_constant_p" helper, __emit_break(), and redefine
> the cur
On Mon, Jul 1, 2024 at 2:22 PM Tiezhu Yang wrote:
>
> On 06/29/2024 11:03 PM, Oleg Nesterov wrote:
> > LoongArch defines UPROBE_SWBP_INSN as a function call and this breaks
> > arch_uprobe_trampoline() which uses it to initialize a static variable.
> >
> > Add the new "__builtin_constant_p" helper
Hi, Bibo,
On Fri, May 24, 2024 at 3:38 PM Bibo Mao wrote:
>
> Steal time feature is added here in kvm side, VM can search supported
> features provided by KVM hypervisor, feature KVM_FEATURE_STEAL_TIME
> is added here. Like x86, steal time structure is saved in guest memory,
> one hypercall funct
On Sat, Jul 6, 2024 at 2:59 PM maobibo wrote:
>
> Huacai,
>
> On 2024/7/6 上午11:00, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Fri, May 24, 2024 at 3:38 PM Bibo Mao wrote:
> >>
> >> Steal time feature is added here in kvm side, VM can search su
On Mon, Jul 8, 2024 at 9:16 AM maobibo wrote:
>
>
>
> On 2024/7/6 下午5:41, Huacai Chen wrote:
> > On Sat, Jul 6, 2024 at 2:59 PM maobibo wrote:
> >>
> >> Huacai,
> >>
> >> On 2024/7/6 上午11:00, Huacai Chen wrote:
> >>> Hi,
Hi, Bibo,
On Mon, Aug 12, 2024 at 11:02 AM Bibo Mao wrote:
>
> Export kernel paravirt features to user space, so that VMM can control
> the single paravirt feature. By default paravirt features will be the same
> with kvm supported features if VMM does not set it.
>
> Also a new feature KVM_FEATU
Hi, Bibo,
On Mon, Aug 12, 2024 at 11:02 AM Bibo Mao wrote:
>
> Interrupts can be routed to maximal four virtual CPUs with one HW
> EIOINTC interrupt controller model, since interrupt routing is encoded with
> CPU bitmap and EIOINTC node combined method. Here add the EIOINTC virt
> extension suppo
On Tue, Aug 20, 2024 at 11:21 AM maobibo wrote:
>
> Huacai,
>
> Thanks for reviewing my patch.
> I reply inline.
>
> On 2024/8/19 下午9:32, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Mon, Aug 12, 2024 at 11:02 AM Bibo Mao wrote:
> >>
> >> E
On Tue, Aug 20, 2024 at 12:02 PM maobibo wrote:
>
> Huacai,
>
> On 2024/8/19 下午9:34, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Mon, Aug 12, 2024 at 11:02 AM Bibo Mao wrote:
> >>
> >> Interrupts can be routed to maximal four virtual CPUs wit
Hi, Bibo,
On Fri, Aug 23, 2024 at 2:39 PM Bibo Mao wrote:
>
> Interrupts can be routed to maximal four virtual CPUs with one HW
> EIOINTC interrupt controller model, since interrupt routing is encoded with
> CPU bitmap and EIOINTC node combined method. Here add the EIOINTC virt
> extension suppor
On Thu, Aug 29, 2024 at 9:46 AM maobibo wrote:
>
> Huacai,
>
> On 2024/8/28 下午10:27, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Fri, Aug 23, 2024 at 2:39 PM Bibo Mao wrote:
> >>
> >> Interrupts can be routed to maximal four virtual CPUs with one H
Hi, Thomas,
On Fri, Aug 30, 2024 at 5:32 PM Bibo Mao wrote:
>
> Interrupts can be routed to maximal four virtual CPUs with one HW
> EIOINTC interrupt controller model, since interrupt routing is encoded with
> CPU bitmap and EIOINTC node combined method. Here add the EIOINTC virt
> extension supp
Hi, Rui Wang,
On Fri, Feb 12, 2021 at 4:21 PM Rui Wang wrote:
>
> From: wangrui
>
> When user-space program accessing a virtual address and falls into TLB invalid
> exception handling. at almost the same time, if the pmd which that contains
> this
> virtual address is hit by THP scanning, and t
l.org
Signed-off-by: Huacai Chen
---
arch/arm/boot/compressed/head.S| 4
arch/arm/boot/compressed/misc.c| 7 ---
arch/mips/boot/compressed/decompress.c | 7 ---
arch/mips/boot/compressed/head.S | 4
arch/sh/boot/compressed/head_32.S | 8
l.org
Signed-off-by: Huacai Chen
---
arch/arm/boot/compressed/misc.c| 9 +
arch/mips/boot/compressed/decompress.c | 9 +
arch/sh/boot/compressed/misc.c | 9 +
3 files changed, 3 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/compressed/misc.c b/a
Reviewed-by: Huacai Chen
On Tue, Feb 23, 2021 at 12:22 AM Lukas Bulwahn wrote:
>
> The domain lookup for linux-mips.org fails for quite some time now. Hence,
> webpages, the patchwork instance and Ralf Baechle's email there is not
> reachable anymore.
>
> Remove all refe
Reviewed-by: Huacai Chen
On Tue, Feb 23, 2021 at 12:22 AM Lukas Bulwahn wrote:
>
> The linux-mips mailing list now lives at kernel.org. Update all references
> in the kernel tree.
>
> Signed-off-by: Lukas Bulwahn
> ---
> arch/mips/kernel/r4k-bugs64.c | 2 +-
> a
Reviewed-by: Huacai Chen
On Tue, Feb 23, 2021 at 12:22 AM Lukas Bulwahn wrote:
>
> The domain lookup for linux-mips.org fails for quite some time now.
> Further, the two links:
>
> http://decstation.unix-ag.org/
> http://www.computer-refuge.org/classiccmp/ftp.digital.
Reviewed-by: Huacai Chen
On Tue, Feb 23, 2021 at 12:22 AM Lukas Bulwahn wrote:
>
> This is a Copyright line, and just a typo slipped through.
>
> Signed-off-by: Lukas Bulwahn
> ---
> arch/mips/sgi-ip27/ip27-timer.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletion
Reviewed-by: Huacai Chen
On Wed, Feb 10, 2021 at 6:04 PM Christoph Hellwig wrote:
>
> CONFIG_DMA_MAYBE_COHERENT just guards two early init options now. Just
> enable them unconditionally for CONFIG_DMA_NONCOHERENT.
>
> Signed-off-by: Christoph Hellwig
> ---
> arch/mi
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