Add Synopsys DesignWare xData IP driver to Kconfig.
This driver enables/disables the PCIe traffic generator module
pertain to the Synopsys DesignWare prototype.
Signed-off-by: Gustavo Pimentel
---
drivers/misc/Kconfig | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers
:
V2: Rework driver according to Greg Kroah-Hartman feedback
Gustavo Pimentel (5):
misc: Add Synopsys DesignWare xData IP driver
misc: Add Synopsys DesignWare xData IP driver to Makefile
misc: Add Synopsys DesignWare xData IP driver to Kconfig
Documentation: misc-devices: Add Documentation
Add Synopsys xData IP driver maintainer.
This driver aims to support Synopsys xData IP and is normally distributed
along with Synopsys PCIe EndPoint IP as a PCIe traffic generator (depends
of the use and licensing agreement).
Signed-off-by: Gustavo Pimentel
---
MAINTAINERS | 7 +++
1 file
Add Synopsys DesignWare xData IP driver. This driver enables/disables
the PCI traffic generator module pertain to the Synopsys DesignWare
prototype.
Signed-off-by: Gustavo Pimentel
---
drivers/misc/dw-xdata-pcie.c | 390 +++
1 file changed, 390 insertions
On Mon, Nov 2, 2020 at 14:27:9, Vidya Sagar wrote:
>
>
> On 11/2/2020 7:45 PM, Rob Herring wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Thu, Oct 29, 2020 at 12:40 AM Vidya Sagar wrote:
> >>
> >> DesignWare core has a TLP digest (TD) override bit in one o
On Mon, Nov 2, 2020 at 21:16:52, Rob Herring wrote:
> On Mon, Nov 2, 2020 at 9:12 AM Gustavo Pimentel
> wrote:
> >
> > On Mon, Nov 2, 2020 at 14:27:9, Vidya Sagar wrote:
> >
> > >
> > >
> > > On 11/2/2020 7:45 PM, Rob Herring wrote:
&
_fixup)
> + if (pci->ops && pci->ops->cpu_addr_fixup)
> cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
>
> if (pci->iatu_unroll_enabled) {
> @@ -470,7 +470,7 @@ int dw_pcie_link_up(struct dw_pcie *pci)
> {
> u32 val;
>
> - if (pci->ops->link_up)
> + if (pci->ops && pci->ops->link_up)
> return pci->ops->link_up(pci);
>
> val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);
> --
> 2.17.1
Looks good to me.
Acked-by: Gustavo Pimentel
to_dw_pcie_from_pp(pp);
> + struct device *dev = pci->dev;
> + dma_unmap_page(dev, pp->msi_data, PAGE_SIZE, DMA_FROM_DEVICE);
> __free_page(pp->msi_page);
> + }
> }
>
> void dw_pcie_msi_init(struct pcie_port *pp)
> --
> 2.28.0
Acked-by: Gustavo Pimentel
}
> +
> pp->msi_data = dma_map_page(dev, pp->msi_page, 0, PAGE_SIZE,
> DMA_FROM_DEVICE);
> if (dma_mapping_error(dev, pp->msi_data)) {
> --
> 2.28.0
Acked-by: Gustavo Pimentel
i_host_init) {
> num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
>
> /* Initialize IRQ Status array */
> --
> 2.28.0
Acked-by: Gustavo Pimentel
void dw_pcie_setup_rc(struct pcie_port *pp);
> int dw_pcie_host_init(struct pcie_port *pp);
> void dw_pcie_host_deinit(struct pcie_port *pp);
> @@ -386,7 +386,7 @@ static inline void dw_pcie_msi_init(struct pcie_port *pp)
> {
> }
>
> -static inline void dw_pcie_free_msi(struct pcie_port *pp)
> +static inline void dw_pcie_msi_deinit(struct pcie_port *pp)
> {
> }
>
> --
> 2.28.0
Acked-by: Gustavo Pimentel
PCIe 5.0 allows an effective 32.0 GT/s speed per lane.
Currently if you read a PCIe 5.0 EP link data rate through sysfs, the
resulting output will be "Unknown speed" instead of "32.0 GT/s" as we
would be expect.
Signed-off-by: Gustavo Pimentel
---
Changes:
v1 -> v2
- Reb
Hi,
On Mon, Jun 17, 2019 at 14:16:45, Arnd Bergmann wrote:
> Putting large constant data on the stack causes unnecessary overhead
> and stack usage:
>
> drivers/dma/dw-edma/dw-edma-v0-debugfs.c:285:6: error: stack frame size of
> 1376 bytes in function 'dw_edma_v0_debugfs_on' [-Werror,-Wframe-
e63d79d1ffcd ("dmaengine: Add Synopsys eDMA IP core driver")
> CC: Gustavo Pimentel
> Signed-off-by: kbuild test robot
> ---
>
> tree:
> https://urldefense.proofpoint.com/v2/url?u=https-3A__git.kernel.org_pub_scm_linux_kernel_git_next_linux
Hi,
On Mon, Jun 17, 2019 at 14:17:47, Arnd Bergmann wrote:
> When building with 'make C=1', sparse reports an endianess bug:
I didn't know that option.
>
> drivers/dma/dw-edma/dw-edma-v0-debugfs.c:60:30: warning: cast removes address
> space of expression
> drivers/dma/dw-edma/dw-edma-v0-deb
On Mon, Jun 17, 2019 at 14:18:43, Arnd Bergmann wrote:
> The new driver mixes up dma_addr_t and __iomem pointers, which results
> in warnings on some 32-bit architectures, like:
>
> drivers/dma/dw-edma/dw-edma-v0-core.c: In function '__dw_regs':
> drivers/dma/dw-edma/dw-edma-v0-core.c:28:9: erro
On Fri, Jun 21, 2019 at 9:51:13, Andy Shevchenko
wrote:
> On Fri, Jun 21, 2019 at 11:43 AM Gustavo Pimentel
> wrote:
> >
> > Hi,
> >
> > On Mon, Jun 17, 2019 at 14:17:47, Arnd Bergmann wrote:
> >
> > > When building with 'make C=1', spar
On Fri, Jun 21, 2019 at 10:1:1, Arnd Bergmann wrote:
> On Fri, Jun 21, 2019 at 10:53 AM Gustavo Pimentel
> wrote:
>
> > >
> > > static struct dentry *base_dir;
> > > static struct dw_edma*dw;
On Fri, Jun 21, 2019 at 9:55:11, Arnd Bergmann wrote:
> On Fri, Jun 21, 2019 at 10:42 AM Gustavo Pimentel
> wrote:
> > On Mon, Jun 17, 2019 at 14:17:47, Arnd Bergmann wrote:
> >
> > > When building with 'make C=1', sparse reports an endianess b
On Wed, Jun 17, 2020 at 19:56:34, Vidya Sagar wrote:
>
>
> On 02-Jun-20 10:37 PM, Gustavo Pimentel wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Tue, Jun 2, 2020 at 11:9:38, Vidya Sagar wrote:
> >
> >&
could give you go/not go flag. Sorry the delay...
Regards,
Gustavo
On 18/12/2017 15:57, Lorenzo Pieralisi wrote:
> Hi Gustavo,
>
> On Thu, Dec 14, 2017 at 12:38:04PM +0000, Gustavo Pimentel wrote:
>> Ok. I will compile and test it now.
> Have you managed to retrieve the patch
Hi Niklas and Lorenzo,
I'm going to work on PCI software development now as told by João and I will
test your code now.
I was retrieving the patches through the patchwork
https://patchwork.ozlabs.org/project/linux-pci/list/?submitter=65580 and I
notice that its missing the patch 13 and 17, is thi
Ok. I will compile and test it now.
Thanks.
On 14/12/2017 12:22, Lorenzo Pieralisi wrote:
> On Thu, Dec 14, 2017 at 12:16:38PM +0000, Gustavo Pimentel wrote:
>> Hi Niklas and Lorenzo,
>>
>> I'm going to work on PCI software development now as told by Joao and I
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