PCIe 5.0 allows an effective 32.0 GT/s speed per lane.
Currently if you read a PCIe 5.0 EP link data rate through sysfs, the
resulting output will be "Unknown speed" instead of "32.0 GT/s" as we
would be expect.
Cc: Bjorn Helgaas
Cc: Lorenzo Pieralisi
Cc: Joao Pinto
Si
Hi Alan,
This patch implementation is very HW implementation dependent and
requires the DMA to exposed through PCIe BARs, which aren't always the
case. Besides, you are defining some control bits on
include/linux/pci-epc.h that may not have any meaning to other types of
DMA.
I don't think thi
On Fri, May 24, 2019 at 20:42:43, Alan Mikhak
wrote:
Hi Alan,
> On Fri, May 24, 2019 at 1:59 AM Gustavo Pimentel
> wrote:
> >
> > Hi Alan,
> >
> > This patch implementation is very HW implementation dependent and
> > requires the DMA to exposed throug
The reset-simple driver can be now used on DesignWare IPs by
default by selecting the following compatible strings:
- snps,dw-high-reset for active high resets inputs
- snps,dw-low-reset for active low resets inputs
Signed-off-by: Gustavo Pimentel
Signed-off-by: Luis Oliveira
---
drivers
This patch series adds a reset-simple compatible string for DesignWare
IPs allowing active high and low resets inputs.
Also adds the corresponding documentation.
Gustavo Pimentel (2):
reset: Add DesignWare IP support to simple reset
dt-bindings: Document the DesignWare IP reset bindings
This adds documentation of device tree bindings for the
DesignWare IP reset controller.
Signed-off-by: Gustavo Pimentel
Signed-off-by: Luis Oliveira
---
.../devicetree/bindings/reset/snps,dw-reset.txt| 30 ++
1 file changed, 30 insertions(+)
create mode 100644
#x27;/home/acme/git/perf/tools/pci'
> $ ls -la /tmp/build/pci/pcitest
> -rwxrwxr-x. 1 acme acme 27152 May 13 13:52 /tmp/build/pci/pcitest
> $ /tmp/build/pci/pcitest
> can't open PCI Endpoint Test device: No such file or directory
> $
>
>
On Mon, Apr 22, 2019 at 8:54:32, Jisheng Zhang
wrote:
> On Wed, 17 Apr 2019 09:56:33 +0000 Gustavo Pimentel wrote:
>
> >
> > On Tue, Apr 16, 2019 at 20:27:18, Vidya Sagar wrote:
> >
> > > Remove multiple write enable and disable sequences of dbi registers as
i_res);
> + if (IS_ERR(pci->dbi_base)) {
> + dev_err(dev, "couldn't remap dbi base %pR\n", dbi_res);
> + return PTR_ERR(pci->dbi_base);
> + }
> +
> + ecam_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
> + if (!ecam_res) {
> + dev_err(dev, "couldn't find 'config' reg in DT\n");
> + return -ENOENT;
> + }
> + al_pcie->ecam_size = resource_size(ecam_res);
> +
> + controller_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> + "controller");
> + al_pcie->controller_base = devm_ioremap_resource(dev, controller_res);
> + if (IS_ERR(al_pcie->controller_base)) {
> + dev_err(dev, "couldn't remap controller base %pR\n",
> + controller_res);
> + return PTR_ERR(al_pcie->controller_base);
> + }
> +
> + dev_dbg(dev, "From DT: dbi_base: %pR, controller_base: %pR\n",
> + dbi_res, controller_res);
> +
> + platform_set_drvdata(pdev, al_pcie);
> +
> + ret = al_add_pcie_port(&pci->pp, pdev);
> +
> + return ret;
> +}
> +
> +static const struct of_device_id al_pcie_of_match[] = {
> + { .compatible = "amazon,al-pcie",
> + },
> + {},
> +};
> +
> +static struct platform_driver al_pcie_driver = {
> + .driver = {
> + .name = "al-pcie",
> + .of_match_table = al_pcie_of_match,
> + .suppress_bind_attrs = true,
> + },
> + .probe = al_pcie_probe,
> +};
> +builtin_platform_driver(al_pcie_driver);
> +
> +#endif /* CONFIG_PCIE_AL*/
> --
> 2.17.1
Reviewed-by: Gustavo Pimentel
0031 device id is reused for other non Root Port device types,
> + * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
> + */
> +DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
> + PCI_CLASS_BRIDGE_PCI, 8, quirk_al_vpd_release);
> +
> #endif
> --
> 2.17.1
Seems ok.
Reviewed-by: Gustavo Pimentel
@@ static const struct pci_dev_acs_enabled {
> { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
> { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
> { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
> + /* Amazon Annapurna Labs */
> + { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
> { 0 }
> };
>
> --
> 2.17.1
Seems ok.
Reviewed-by: Gustavo Pimentel
On Thu, Jul 18, 2019 at 10:47:16, Jonathan Chocron
wrote:
> This driver is DT based and utilizes the DesignWare APIs.
> It allows using a smaller ECAM range for a larger bus range -
> usually an entire bus uses 1MB of address space, but the driver
> can use it for a larger number of buses.
>
>
ie_host_init(struct pcie_port *pp)
> }
> }
>
> + hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
> + if (hdr_type != PCI_HEADER_TYPE_BRIDGE) {
> + dev_err(pci->dev, "PCIe controller is not set to bridge type
> (hdr_type: 0x%x)!\n",
> + hdr_type);
> + return -EIO;
> + }
> +
> pp->mem_base = pp->mem->start;
>
> if (!pp->va_cfg0_base) {
> --
> 2.17.1
It doesn't harm.
Thanks.
Acked-by: Gustavo Pimentel
dev->no_msi = 1;
> + pci_warn(dev, "Disabling MSI-X\n");
> +}
> +DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
> + PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
> #endif /* CONFIG_PCI_MSI */
>
> /*
> --
> 2.17.1
Reviewed-by: Gustavo Pimentel
On Sun, Jul 21, 2019 at 16:8:18, Chocron, Jonathan
wrote:
> On Fri, 2019-07-19 at 08:55 +0000, Gustavo Pimentel wrote:
> > On Thu, Jul 18, 2019 at 10:47:16, Jonathan Chocron > >
> > wrote:
> >
> > > This driver is DT based and utilizes the DesignWare A
e[24];
> + const char *name;
> dma_addr_t *reg;
> };
>
> --
> 2.20.0
Acked-by: Gustavo Pimentel
->id, ch_control1,
> (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE));
> /* Linked list - low, high */
> - llp = cpu_to_le64(chunk->ll_region.paddr);
> - SET_CH(dw, chan->dir, chan->id, llp_low, lower_32_bits(llp));
> - SET_CH(dw, chan->dir, chan->id, llp_high, upper_32_bits(llp));
> + SET_CH(dw, chan->dir, chan->id, llp_low,
> +lower_32_bits(chunk->ll_region.paddr));
> + SET_CH(dw, chan->dir, chan->id, llp_high,
> +upper_32_bits(chunk->ll_region.paddr));
> }
> /* Doorbell */
> SET_RW(dw, chan->dir, doorbell,
> --
> 2.20.0
Acked-by: Gustavo Pimentel
Hi Hanjie,
On 21/09/2018 07:03, Hanjie Lin wrote:
> From: Yue Wang
>
> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
> PCI core. This patch adds the driver support for Meson PCIe controller.
>
> Signed-off-by: Yue Wang
> Signed-off-by: Hanjie Lin
> ---
> drivers/
On 25/09/2018 17:14, Lorenzo Pieralisi wrote:
> [+Gustavo, please have a look at INTX/MSI management]
>
> On Thu, Sep 06, 2018 at 06:40:32PM +0900, Kunihiko Hayashi wrote:
>> This introduces specific glue layer for UniPhier platform to support
>> PCIe host controller that is based on the DesignWar
Hi Jia,
On 02/09/2018 04:38, Jia-Ju Bai wrote:
> The driver may sleep with holding a spinlock and in an interupt handler.
>
> The function call paths (from bottom to top) in Linux-4.16 are:
>
> [FUNC] usleep_range
> drivers/pci/dwc/pcie-designware.c, 181:
> usleep_range in dw_pcie_prog_ou
Hi Kishon,
On 16/04/2018 10:29, Kishon Vijay Abraham I wrote:
> Hi Gustavo,
>
> On Tuesday 10 April 2018 10:44 PM, Gustavo Pimentel wrote:
>> Changes the pcie_raise_irq function signature, namely the interrupt_num
>> variable type from u8 to u16 to accommodate the MSI-X max
Hi Alan,
On 24/04/2018 07:48, Alan Douglas wrote:
> Hi Gustavo,
>
> On 10 April 2018 18:15 Gustavo Pimentel wrote:
>> This patch set depends the following series:
>> https://urldefense.proofpoint.com/v2/url?u=https-3A__lkml.org_lkml_2018_4_10_421&d=DwIFAg&c=DPL6_X
Hi Kishon,
On 24/04/2018 08:07, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Monday 23 April 2018 03:06 PM, Gustavo Pimentel wrote:
>> Hi Kishon,
>>
>> On 16/04/2018 10:29, Kishon Vijay Abraham I wrote:
>>> Hi Gustavo,
>>>
>>> On Tuesday 10 Apr
Hi Kishon,
On 24/04/2018 08:19, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 17 April 2018 11:08 PM, Gustavo Pimentel wrote:
>> Hi Kishon,
>>
>> On 17/04/2018 11:33, Kishon Vijay Abraham I wrote:
>>> Hi,
>>>
>>> On Tuesday 10 April 2018
Hi Alan,
On 24/04/2018 07:59, Alan Douglas wrote:
> Hi Gustavo,
>
> On 10 April 2018 18:15 Gustavo Pimentel wrote:
>>
>> Adds the MSI-X support and updates driver documentation accordingly.
>>
>> Changes the driver parameter in order to allow the interruption ty
On 24/04/2018 10:15, Alan Douglas wrote:
> Hi,
>
> On 10 April 2018 18:15 Gustavo Pimentel wrote:
>> Changes the pcie_raise_irq function signature, namely the interrupt_num
>> variable type from u8 to u16 to accommodate the MSI-X maximum interrupts
>> of 2048.
>>
efine
that helps the human compreension.
- Replaces a division by 2 by a simple right shift rotation of 1 bit.
- Fixes all first letter characters on comments and debug messages to
upper case to maintain coherency.
Gustavo Pimentel (9):
bindings: PCI: designware: Example update
PCI: dwc
-by: Gustavo Pimentel
Acked-by: Joao Pinto
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.
Changes v3->v4:
- Nothing changed, just to follow the patch set version.
Changes v4->v5
Adds the designware EP device ID entry to pci_endpoint_test driver table
to allow this device to be recognize and handle by the pci_endpoint_test
driver.
Signed-off-by: Gustavo Pimentel
Acked-by: Kishon Vijay Abraham I
---
Change v1->v2:
- Changed device id following Kishon's su
Replaces lower into upper case characters in comments and debug printks.
This is an attempt to keep the messages coherent within the designware
driver.
Also fixed code style on dw_pcie_irq_domain_free function.
Signed-off-by: Gustavo Pimentel
Acked-by: Jingoo Han
Acked-by: Joao Pinto
Replace magic numbers by a well known define in order to make the code
human readable and also facilitate the code reusability.
Signed-off-by: Gustavo Pimentel
Acked-by: Jingoo Han
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing c
it by the equivalent operation in this case, the shift
rotation.
Signed-off-by: Gustavo Pimentel
Acked-by: Jingoo Han
Acked-by: Joao Pinto
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.
Adds a seconds entry on the pci_epf_test_ids structure that disables the
linkup_notifier parameter on driver for the designware EP.
This allows designware EPs that doesn't have linkup notification signal
to work with pcitest.
Updates the binding documentation accordingly.
Signed-off-by: Gu
Add device tree binding documentation for the Endpoint in PCIe Designware
driver.
Signed-off-by: Gustavo Pimentel
Reviewed-by: Rob Herring
---
Change v1->v2:
- Add a missing log description.
- Add "snps,dw-pcie" compatible string following Kishon's suggestion.
Change v
The PCIe controller dual mode is capable of operating in host mode as well
as endpoint mode by configuration, therefore this patch aims to add
endpoint mode support to the designware driver.
Signed-off-by: Gustavo Pimentel
Acked-by: Kishon Vijay Abraham I
---
Change v1->v2:
- Remo
Replaces "ctrlreg" reg-name by "dbi" to be coherent with similar drivers,
however it still be compatible with any previous DT that uses the old
reg-name.
Replaces the PCIe base address example by a real PCIe base address in use.
Signed-off-by: Gustavo Pimentel
Revi
Hi Lorenzo and Kishon,
On 03/05/2018 07:33, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> On Wednesday 02 May 2018 10:21 PM, Lorenzo Pieralisi wrote:
>> On Wed, May 02, 2018 at 11:39:00AM +0100, Gustavo Pimentel wrote:
>>> Hi Lorenzo,
>>>
>>> On
Hi Fabio,
On 15/04/2018 14:09, Fabio Estevam wrote:
> Hi Gustavo,
>
> On Wed, Apr 11, 2018 at 4:40 AM, Gustavo Pimentel
> wrote:
>
>> Can be this one?
>>
>> Probably any recent and decent compiler does this kind of substitution
>> in order to improv
Hi Rob,
On 13/04/2018 22:34, Rob Herring wrote:
> On Tue, Apr 10, 2018 at 01:58:33PM +0100, Gustavo Pimentel wrote:
>> Replaces "ctrlreg" reg-name by "dbi" to be coherent with similar drivers,
>> however it still be compatible with any previous DT that uses the
Hi Jingoo,
On 11/04/2018 20:37, Jingoo Han wrote:
> On Wednesday, April 11, 2018 3:40 AM, Gustavo Pimentel wrote:
>>
>> Hi Jingoo,
>>
>> On 11/04/2018 01:01, Jingoo Han wrote:
>>> On Monday, April 9, 2018 5:41 AM, Gustavo Pimentel wrote:
>>>>
>&
efine
that helps the human compreension.
- Replaces a division by 2 by a simple right shift rotation of 1 bit.
- Fixes all first letter characters on comments and debug messages to
upper case to maintain coherency.
Gustavo Pimentel (10):
bindings: PCI: designware: Example update
PCI: dwc
Replaces lower into upper case characters in comments and debug printks.
This is an attempt to keep the messages coherent within the designware
driver.
Also fixed code style on dw_pcie_irq_domain_free function.
Signed-off-by: Gustavo Pimentel
Acked-by: Jingoo Han
---
Change v1->v2:
- Added
it by the equivalent operation in this case, the shift
rotation.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.
Changes v3->v4:
- Added a small explicat
Replace magic numbers by a well known define in order to make the code
human readable and also facilitate the code reusability.
Signed-off-by: Gustavo Pimentel
Acked-by: Jingoo Han
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed
Add device tree binding documentation for the Endpoint in PCIe Designware
driver.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Add a missing log description.
- Add "snps,dw-pcie" compatible string following Kishon's suggestion.
Change v2->v3:
- Reverted pcie_ep nam
Adds the designware EP device ID entry to pci_endpoint_test driver table
to allow this device to be recognize and handle by the pci_endpoint_test
driver.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Changed device id following Kishon's suggestion.
Change v2->v3:
- Nothing ch
The PCIe controller dual mode is capable of operating in host mode as well
as endpoint mode by configuration.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Register new device id following Kishon's suggestion.
Change v2->v3:
- Nothing changed, just to follow the patch set versi
-by: Gustavo Pimentel
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.
Changes v3->v4:
- Nothing changed, just to follow the patch set version.
drivers/pci/dwc/pcie-designware-plat.c | 6
Replaces "ctrlreg" reg-name by "dbi" to be coherent with similar drivers,
however it still be compatible with any previous DT that uses the old
reg-name.
Replaces the PCIe base address example by a real PCIe base address in use.
Signed-off-by: Gustavo Pimentel
---
Changes v1
Adds a seconds entry on the pci_epf_test_ids structure that disables the
linkup_notifier parameter on driver.
This allows EPs that doesn't have linkup notification signal to work
with pcitest.
Signed-off-by: Gustavo Pimentel
---
Change v2->v3:
- Added second entry in pci_epf_test_ids s
The PCIe controller dual mode is capable of operating in host mode as well
as endpoint mode by configuration, therefore this patch aims to add
endpoint mode support to the designware driver.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Removed dw_plat_pcie_stop_link empty funct
Hi Rob,
On 16/04/2018 22:43, Rob Herring wrote:
> On Mon, Apr 16, 2018 at 03:37:52PM +0100, Gustavo Pimentel wrote:
>> Add device tree binding documentation for the Endpoint in PCIe Designware
>> driver.
>>
>> Signed-off-by: Gustavo Pimentel
>> ---
>>
Hi Rob,
On 16/04/2018 22:39, Rob Herring wrote:
> On Mon, Apr 16, 2018 at 03:37:49PM +0100, Gustavo Pimentel wrote:
>> Replaces "ctrlreg" reg-name by "dbi" to be coherent with similar drivers,
>> however it still be compatible with any previous DT that uses the
Hi Alan,
Sorry for the delay on the response, I only have time to proper analyze this
now.
On 24/04/2018 10:15, Alan Douglas wrote:
> Hi,
>
> On 10 April 2018 18:15 Gustavo Pimentel wrote:
>> Changes the pcie_raise_irq function signature, namely the interrupt_num
>> var
-by: Gustavo Pimentel
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.
Changes v3->v4:
- Nothing changed, just to follow the patch set version.
Changes v4->v5:
- Nothing changed, ju
Replace magic numbers by a well known define in order to make the code
human readable and also facilitate the code reusability.
Signed-off-by: Gustavo Pimentel
Acked-by: Jingoo Han
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing c
The PCIe controller dual mode is capable of operating in host mode as well
as endpoint mode by configuration.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Register new device id following Kishon's suggestion.
Change v2->v3:
- Nothing changed, just to follow the patch
Adds the designware EP device ID entry to pci_endpoint_test driver table
to allow this device to be recognize and handle by the pci_endpoint_test
driver.
Signed-off-by: Gustavo Pimentel
Acked-by: Kishon Vijay Abraham I
---
Change v1->v2:
- Changed device id following Kishon's su
Add device tree binding documentation for the Endpoint in PCIe Designware
driver.
Signed-off-by: Gustavo Pimentel
Reviewed-by: Rob Herring
---
Change v1->v2:
- Add a missing log description.
- Add "snps,dw-pcie" compatible string following Kishon's suggestion.
Change v
it by the equivalent operation in this case, the shift
rotation.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.
Changes v3->v4:
- Added a small explicat
The PCIe controller dual mode is capable of operating in host mode as well
as endpoint mode by configuration, therefore this patch aims to add
endpoint mode support to the designware driver.
Signed-off-by: Gustavo Pimentel
Acked-by: Kishon Vijay Abraham I
---
Change v1->v2:
- Remo
Replaces lower into upper case characters in comments and debug printks.
This is an attempt to keep the messages coherent within the designware
driver.
Also fixed code style on dw_pcie_irq_domain_free function.
Signed-off-by: Gustavo Pimentel
Acked-by: Jingoo Han
---
Change v1->v2:
- Ad
Replaces "ctrlreg" reg-name by "dbi" to be coherent with similar drivers,
however it still be compatible with any previous DT that uses the old
reg-name.
Replaces the PCIe base address example by a real PCIe base address in use.
Signed-off-by: Gustavo Pimentel
---
Changes v1
Adds a seconds entry on the pci_epf_test_ids structure that disables the
linkup_notifier parameter on driver for the designware EP.
This allows designware EPs that doesn't have linkup notification signal
to work with pcitest.
Updates the binding documentation accordingly.
Signed-off-by: Gu
efine
that helps the human compreension.
- Replaces a division by 2 by a simple right shift rotation of 1 bit.
- Fixes all first letter characters on comments and debug messages to
upper case to maintain coherency.
Gustavo Pimentel (10):
bindings: PCI: designware: Example update
PCI: dwc
Hi Kishon,
On 17/04/2018 11:24, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 10 April 2018 10:44 PM, Gustavo Pimentel wrote:
>> Implements the generic method for calling the get/set callbacks.
>>
>> Adds the PCI_EPC_IRQ_MSIX type.
>>
>> Adds th
Hi Kishon,
On 17/04/2018 11:33, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 10 April 2018 10:44 PM, Gustavo Pimentel wrote:
>> Adds the MSI-X support and updates driver documentation accordingly.
>>
>> Changes the driver parameter in order to allow the int
Add device tree binding documentation for the Endpoint in PCIe Designware
driver.
Signed-off-by: Gustavo Pimentel
Reviewed-by: Rob Herring
---
Change v1->v2:
- Add a missing log description.
- Add "snps,dw-pcie" compatible string following Kishon's suggestion.
Change v
Adds a seconds entry on the pci_epf_test_ids structure that disables the
linkup_notifier parameter on driver for the designware EP.
This allows designware EPs that doesn't have linkup notification signal
to work with pcitest.
Updates the binding documentation accordingly.
Signed-off-by: Gu
Replaces "ctrlreg" reg-name by "dbi" to be coherent with similar drivers,
however it still be compatible with any previous DT that uses the old
reg-name.
Replaces the PCIe base address example by a real PCIe base address in use.
Signed-off-by: Gustavo Pimentel
Revi
efine
that helps the human compreension.
- Replaces a division by 2 by a simple right shift rotation of 1 bit.
- Fixes all first letter characters on comments and debug messages to
upper case to maintain coherency.
Gustavo Pimentel (9):
bindings: PCI: designware: Example update
PCI: dwc
Replaces lower into upper case characters in comments and debug printks.
This is an attempt to keep the messages coherent within the designware
driver.
Also fixed code style on dw_pcie_irq_domain_free function.
Signed-off-by: Gustavo Pimentel
Acked-by: Jingoo Han
Acked-by: Joao Pinto
Replace magic numbers by a well known define in order to make the code
human readable and also facilitate the code reusability.
Signed-off-by: Gustavo Pimentel
Acked-by: Jingoo Han
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing c
Adds the designware EP device ID entry to pci_endpoint_test driver table
to allow this device to be recognize and handle by the pci_endpoint_test
driver.
Signed-off-by: Gustavo Pimentel
Acked-by: Kishon Vijay Abraham I
---
Change v1->v2:
- Changed device id following Kishon's su
it by the equivalent operation in this case, the shift
rotation.
Signed-off-by: Gustavo Pimentel
Acked-by: Jingoo Han
Acked-by: Joao Pinto
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.
The PCIe controller dual mode is capable of operating in host mode as well
as endpoint mode by configuration, therefore this patch aims to add
endpoint mode support to the designware driver.
Signed-off-by: Gustavo Pimentel
Acked-by: Kishon Vijay Abraham I
---
Change v1->v2:
- Remo
-by: Gustavo Pimentel
Acked-by: Joao Pinto
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.
Changes v3->v4:
- Nothing changed, just to follow the patch set version.
Changes v4->v5
On Mon, Jul 13, 2020 at 13:22:18, Saheed O. Bolarinwa
wrote:
> Remove unnecessary check for 0.
>
> Signed-off-by: "Saheed O. Bolarinwa"
> ---
> This patch depends on PATCH 05/35
>
> drivers/pci/controller/dwc/pci-meson.c| 2 +-
> drivers/pci/controller/dwc/pcie-designware-host.c
> Hi Rob,
> > >
> > > Thanks a lot for your comments!
> > >
> > > > -Original Message-
> > > > From: Rob Herring
> > > > Sent: 2020年9月18日 23:28
> > > > To: Z.q. Hou
> > > > Cc: linux-kernel@vger.kerne
; #define PCIE_ATU_UNR_UPPER_TARGET0x18
> +#define PCIE_ATU_UNR_UPPER_LIMIT 0x20
>
> /*
> * The default address offset between dbi_base and atu_base. Root controller
> --
> 2.7.4
Acked-by: Gustavo Pimentel
Hi Lorenzo,
On Tue, May 5, 2020 at 11:29:33, Lorenzo Pieralisi
wrote:
> On Wed, Apr 01, 2020 at 04:58:13PM -0700, Alan Mikhak wrote:
> > From: Alan Mikhak
> >
> > Function dw_pcie_prog_outbound_atu_unroll() does not program the upper
> > 32-bit ATU limit register. Since ATU programming functi
truct platform_device *pdev)
> goto err_pm_runtime_put;
> }
>
> - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
> - pcie->parf = devm_ioremap_resource(dev, res);
> + pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
> if (IS_ERR(pcie->parf)) {
> ret = PTR_ERR(pcie->parf);
> goto err_pm_runtime_put;
> @@ -1372,8 +1371,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
> goto err_pm_runtime_put;
> }
>
> - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
> - pcie->elbi = devm_ioremap_resource(dev, res);
> + pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi");
> if (IS_ERR(pcie->elbi)) {
> ret = PTR_ERR(pcie->elbi);
> goto err_pm_runtime_put;
> diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c
> b/drivers/pci/controller/dwc/pcie-uniphier.c
> index a5401a0b1e58..3a7f403b57b8 100644
> --- a/drivers/pci/controller/dwc/pcie-uniphier.c
> +++ b/drivers/pci/controller/dwc/pcie-uniphier.c
> @@ -416,8 +416,7 @@ static int uniphier_pcie_probe(struct platform_device
> *pdev)
> if (IS_ERR(priv->pci.dbi_base))
> return PTR_ERR(priv->pci.dbi_base);
>
> - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "link");
> - priv->base = devm_ioremap_resource(dev, res);
> + priv->base = devm_platform_ioremap_resource_byname(pdev, "link");
> if (IS_ERR(priv->base))
> return PTR_ERR(priv->base);
>
> --
> 2.25.0
Reviewed-by: Gustavo Pimentel
Tegra194 and what I heard from our HW
> engineers is that it should generally be true for any DWC based implementation
> also.
> Hence, I request Synopsys folks (Jingoo Han & Gustavo Pimentel ??) to confirm
> the same so that this particular patch won't cause any regressions for o
);
> + PCI_IRQ_MSI_TYPES);
> if (nr_irqs < 1) {
> pci_err(pdev, "fail to alloc IRQ vector (number of IRQs=%u)\n",
> nr_irqs);
> --
> 2.17.2
Acked-by: Gustavo Pimentel
nd detects that the interrupt is from AER,
> and invoke AER interrupts related to MSI.
>
> Cc: Marc Zyngier
> Cc: Jingoo Han
> Cc: Gustavo Pimentel
> Signed-off-by: Kunihiko Hayashi
> ---
> drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++
> drivers/pci/contro
Hi Kunihiko,
On Fri, May 15, 2020 at 10:59:2, Kunihiko Hayashi
wrote:
> This gets iATU register area from reg property. In Synopsis DWC version
s/Synopsis/Synopsys
in all patches
> 4.80 or later, since iATU register area is separated from core register
> area, this area is necessary to get fr
[+cc Marc; IRQ DOMAINS (IRQ NUMBER MAPPING LIBRARY) maintainer]
On Fri, May 15, 2020 at 10:58:59, Kunihiko Hayashi
wrote:
> This adds msi_host_isr() callback function support to describe
> SoC-dependent service triggered by MSI.
>
> For example, when AER interrupt is triggered by MSI, the call
[+cc Marc; IRQ DOMAINS (IRQ NUMBER MAPPING LIBRARY) maintainer]
On Fri, May 15, 2020 at 10:59:0, Kunihiko Hayashi
wrote:
> The misc interrupts consisting of PME, AER, and Link event, is handled
> by INTx handler, however, these interrupts should be also handled by
> MSI handler.
>
> This adds
The 1-bit shift rotation to the left on x variable located on
4 last if statement can be removed because the computed value is will
not be used afront.
Signed-off-by: Gustavo Pimentel
---
arch/arc/include/asm/bitops.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch
this case
BAR_5.
Signed-off-by: Gustavo Pimentel
---
drivers/misc/pci_endpoint_test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index e060796..b86f9f7 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b
Add Synopsys DesignWare xData IP driver to Makefile.
This driver enables/disables the PCIe traffic generator module
pertain to the Synopsys DesignWare prototype.
Signed-off-by: Gustavo Pimentel
---
drivers/misc/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/Makefile
the PCIe link
throughput speed and check is the prototype solution has some limitation
or not.
Cc: Derek Kiernan
Cc: Dragan Cvetic
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Cc: Jonathan Corbet
Cc: linux-...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Gustavo
Add Synopsys DesignWare xData IP driver. This driver enables/disables
the PCI traffic generator module pertain to the Synopsys DesignWare
prototype.
Signed-off-by: Gustavo Pimentel
---
drivers/misc/dw-xdata-pcie.c | 395 +++
1 file changed, 395 insertions
Add Documentation for dw-xdata-pcie driver.
Signed-off-by: Gustavo Pimentel
---
Documentation/misc-devices/dw-xdata-pcie.rst | 43
1 file changed, 43 insertions(+)
create mode 100644 Documentation/misc-devices/dw-xdata-pcie.rst
diff --git a/Documentation/misc
Add Synopsys DesignWare xData IP driver to Kconfig.
This driver enables/disables the PCIe traffic generator module
pertain to the Synopsys DesignWare prototype.
Signed-off-by: Gustavo Pimentel
---
drivers/misc/Kconfig | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/misc
Add Synopsys xData IP driver maintainer.
This driver aims to support Synopsys xData IP and is normally distributed
along with Synopsys PCIe EndPoint IP as a PCIe traffic generator (depends
of the use and licensing agreement).
Signed-off-by: Gustavo Pimentel
---
Documentation/misc-devices/dw
Hi Greg,
On Mon, Nov 9, 2020 at 17:31:8, Greg Kroah-Hartman
wrote:
> On Thu, Oct 29, 2020 at 08:13:36PM +0100, Gustavo Pimentel wrote:
> > Add Synopsys DesignWare xData IP driver. This driver enables/disables
> > the PCI traffic generator module pertain to the Synopsys DesignWar
On Tue, Nov 10, 2020 at 17:30:5, Greg Kroah-Hartman
wrote:
> On Tue, Nov 10, 2020 at 03:17:54PM +0000, Gustavo Pimentel wrote:
> > Hi Greg,
> >
> > On Mon, Nov 9, 2020 at 17:31:8, Greg Kroah-Hartman
> > wrote:
> >
> > > On Thu, Oct 29, 2020 a
Add Synopsys DesignWare xData IP driver to Makefile.
This driver enables/disables the PCIe traffic generator module
pertain to the Synopsys DesignWare prototype.
Signed-off-by: Gustavo Pimentel
---
drivers/misc/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/Makefile
Add Documentation for dw-xdata-pcie driver.
Signed-off-by: Gustavo Pimentel
---
Documentation/misc-devices/dw-xdata-pcie.rst | 40
1 file changed, 40 insertions(+)
create mode 100644 Documentation/misc-devices/dw-xdata-pcie.rst
diff --git a/Documentation/misc
401 - 500 of 523 matches
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