Change {cdns, dra7xx, artpec6, dw, rockchip}_pcie_ep_raise_irq() and
pci_epc_raise_irq() signature, namely the interrupt_num variable type
from u8 to u16 to accommodate 2048 maximum MSI-X interrupts.
Signed-off-by: Gustavo Pimentel
Acked-by: Alan Douglas
---
Change v1->v2:
- Nothing chan
by calling mdelay() instead.
Makes sense. Thanks.
Acked-by: Gustavo Pimentel
Regards,
Gustavo
>
> Signed-off-by: Jisheng Zhang
> ---
>
> Since v1
> - use mdelay() instead of udelay() to avoid __bad_udelay()
>
> drivers/pci/controller/dwc/pcie-designware.c | 8 -
Fix compilation warnings:
- remove unused variables
- change function return from int to void, since it's not used
Signed-off-by: Gustavo Pimentel
---
tools/pci/pcitest.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/tools/pci/pcitest.c b/tools/pci/pcitest.c
: Gustavo Pimentel
Acked-by: Kishon Vijay Abraham I
---
Change v8->v9:
- Created patch file.
Change v9->v10:
- Nothing changed, just to follow the patch set version.
Change v10->v11:
- Missed Kishon acknowledge.
Change v11->v12:
- Nothing changed, just to follow the patch set version
Cleanup PCI_ENDPOINT_TEST memspace (by moving the interrupt number away
from command section).
Add IRQ_TYPE register to identify the triggered ID interrupt required
for the READ/WRITE/COPY tests and raise IRQ test commands.
Update documentation accordingly.
Signed-off-by: Gustavo Pimentel
Add MSI-X support and update driver documentation accordingly.
Signed-off-by: Gustavo Pimentel
Acked-by: Kishon Vijay Abraham I
---
Change v2->v3:
- New patch file created base on the previous patch
"misc: pci_endpoint_test: Add MSI-X support" patch file following
Kishon's
Change {cdns, dra7xx, artpec6, dw, rockchip}_pcie_ep_raise_irq() and
pci_epc_raise_irq() signature, namely the interrupt_num variable type
from u8 to u16 to accommodate 2048 maximum MSI-X interrupts.
Signed-off-by: Gustavo Pimentel
Acked-by: Alan Douglas
Acked-by: Shawn Lin
Acked-by: Jesper
Add PCIe config space capability search function.
Add sysfs set/get interface to allow the change of EP MSI-X maximum number.
Add EP MSI-X callback for triggering interruptions.
Signed-off-by: Gustavo Pimentel
Acked-by: Kishon Vijay Abraham I
---
Change v1->v2:
- Nothing changed, just
Hi Alan,
On 17/07/2018 21:42, Alan Douglas wrote:
> Hi Gustavo,
>
> On 17 July 2018 11:26, Gustavo Pimentel wrote:
>> Add MSI-X support and update driver documentation accordingly.
>>
>> Add 2 new IOCTL commands:
>> - Allow to reconfigure driver IRQ type in
s EPF devices for probing
> */
> struct pci_epf_driver {
> @@ -82,7 +82,7 @@ struct pci_epf_driver {
> struct device_driverdriver;
> struct pci_epf_ops *ops;
> struct module *owner;
> - struct config_group *group;
> + struct list_headepf_group;
> const struct pci_epf_device_id *id_table;
> };
>
>
Works like a charm. :)
Tested-by: Gustavo Pimentel
Hi Jingoo,
On 11/04/2018 01:01, Jingoo Han wrote:
> On Monday, April 9, 2018 5:41 AM, Gustavo Pimentel wrote:
>>
>> Replaces a simple division by 2 to a right shift rotation of 1 bit.
>
> It looks good. However, would you add a simple reason to the commit
> message?
The PCIe controller dual mode is capable of operating in host mode as well
as endpoint mode by configuration.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Register new device id following Kishon's suggestion.
include/linux/pci_ids.h | 1 +
1 file changed, 1 insertion(+)
diff
Replaces "ctrlreg" reg-name by "dbi" to be coherent with similar drivers,
however it still be compatible with any previous DT that uses the old
reg-name.
Replaces the PCIe base address example by a real PCIe base address in use.
Signed-off-by: Gustavo Pimentel
---
Changes v1
Add device tree binding documentation for the Endpoint in PCIe Designware
driver.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Add a missing log description.
- Add "snps,dw-pcie" compatible string following Kishon's suggestion.
Documentation/devicetree/bindi
Replace magic numbers by a well known define in order to make the code
human readable and also facilitate the code reusability.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
drivers/pci/dwc/pcie-designware-host.c |
that helps the human compreension.
- Replaces a division by 2 by a simple right shift rotation of 1 bit.
- Fixes all first letter characters on comments and debug messages to
upper case to maintain coherency.
Gustavo Pimentel (9):
bindings: PCI: designware: Example update
PCI: dwc: Add su
Replaces lower into upper case characters in comments and debug printks.
This is an attempt to keep the messages coherent within the designware
driver.
Also fixed code style on dw_pcie_irq_domain_free function.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Added an extra log descript
Replaces a simple division by 2 to a right shift rotation of 1 bit.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
drivers/pci/dwc/pcie-designware-host.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --gi
-by: Gustavo Pimentel
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
drivers/pci/dwc/pcie-designware-plat.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/dwc/pcie-designware-plat.c
b/drivers/pci/dwc/pcie-designware-plat.c
index 5382
The PCIe controller dual mode is capable of operating in host mode as well
as endpoint mode by configuration, therefore this patch aims to add
endpoint mode support to the designware driver.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Removed dw_plat_pcie_stop_link empty funct
Adds the designware EP device ID entry to pci_endpoint_test driver table
to allow this device to be recognize and handle by the pci_endpoint_test
driver.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Changed device id following Kishon's suggestion.
drivers/misc/pci_endpoint_te
Hi Joe,
On 09/04/2018 11:25, Joe Perches wrote:
> On Mon, 2018-04-09 at 10:41 +0100, Gustavo Pimentel wrote:
>> Replaces lower into upper case characters in comments and debug printks.
>>
>> This is an attempt to keep the messages coherent within the designware
>> d
Hi Lorenzo,
On 09/04/2018 17:03, Lorenzo Pieralisi wrote:
> On Mon, Apr 09, 2018 at 10:41:15AM +0100, Gustavo Pimentel wrote:
>> Adds a callback that defines the maximum number of vectors that can be use
>> by the Root Complex.
>>
>> Since this is a parameter associ
Hi Kishon,
On 10/04/2018 06:12, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Monday 09 April 2018 03:11 PM, Gustavo Pimentel wrote:
>> The PCIe controller dual mode is capable of operating in host mode as well
>> as endpoint mode by configuration, therefore this patch aims to
Hi Rob,
On 09/04/2018 20:12, Rob Herring wrote:
> On Wed, Mar 28, 2018 at 12:38:33PM +0100, Gustavo Pimentel wrote:
>> Signed-off-by: Gustavo Pimentel
>> ---
>> Documentation/devicetree/bindings/pci/designware-pcie.txt | 13 +
>> 1 file changed, 13 inser
Adds the designware EP device ID entry to pci_endpoint_test driver table
to allow this device to be recognize and handle by the pci_endpoint_test
driver.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Changed device id following Kishon's suggestion.
Change v2->v3:
- Nothing ch
-by: Gustavo Pimentel
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.
drivers/pci/dwc/pcie-designware-plat.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/dw
The PCIe controller dual mode is capable of operating in host mode as well
as endpoint mode by configuration.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Register new device id following Kishon's suggestion.
Change v2->v3:
- Nothing changed, just to follow the patch
The PCIe controller dual mode is capable of operating in host mode as well
as endpoint mode by configuration, therefore this patch aims to add
endpoint mode support to the designware driver.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Removed dw_plat_pcie_stop_link empty funct
Add device tree binding documentation for the Endpoint in PCIe Designware
driver.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Add a missing log description.
- Add "snps,dw-pcie" compatible string following Kishon's suggestion.
Change v2->v3:
- Reverted
Adds a seconds entry on the pci_epf_test_ids structure that disables the
linkup_notifier parameter on driver.
This allows EPs that doesn't have linkup notification signal to work
with pcitest.
Signed-off-by: Gustavo Pimentel
---
Change v2->v3:
- Added second entry in pci_epf_test_ids s
Replaces "ctrlreg" reg-name by "dbi" to be coherent with similar drivers,
however it still be compatible with any previous DT that uses the old
reg-name.
Replaces the PCIe base address example by a real PCIe base address in use.
Signed-off-by: Gustavo Pimentel
---
Changes v1
Replaces a simple division by 2 to a right shift rotation of 1 bit.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.
drivers/pci/dwc/pcie-designware-host
Replace magic numbers by a well known define in order to make the code
human readable and also facilitate the code reusability.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the
Replaces lower into upper case characters in comments and debug printks.
This is an attempt to keep the messages coherent within the designware
driver.
Also fixed code style on dw_pcie_irq_domain_free function.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Added an extra log descript
that helps the human compreension.
- Replaces a division by 2 by a simple right shift rotation of 1 bit.
- Fixes all first letter characters on comments and debug messages to
upper case to maintain coherency.
Gustavo Pimentel (10):
bindings: PCI: designware: Example update
PCI: dwc: Add su
Adds in pci_epc_set_msi function a maximum number of 32 interrupts
validation.
Removes duplicate defines located on pcie-designware.h file. Uses now
the defines available on /include/uapi/linux/pci-regs.h file.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/pcie-designware-ep.c | 46
on pcitest tool. Also updates the pcitest
script with the new test set applied to this new feature.
Gustavo Pimentel (10):
PCI: dwc: Add MSI-X callbacks handler
PCI: cadence: Update cdns_pcie_ep_raise_irq function signature
PCI: endpoint: Add MSI-X interfaces
PCI: dwc: MSI callbacks handler
Changes the cdns_pcie_ep_raise_irq function signature, namely the
interrupt_num variable type from u8 to u16 to accommodate the MSI-X maximum
interrupts of 2048.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/cadence/pcie-cadence-ep.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Adds MSI-X support to the pcitest tool and modified the pcitest.sh script
to accomodate this new type of interruption test.
Signed-off-by: Gustavo Pimentel
---
include/uapi/linux/pcitest.h | 1 +
tools/pci/pcitest.c | 18 +-
tools/pci/pcitest.sh | 25
Adds the MSI-X support and updates driver documentation accordingly.
Changes the driver parameter in order to allow the interruption type
selection.
Signed-off-by: Gustavo Pimentel
---
Documentation/misc-devices/pci-endpoint-test.txt | 3 +
drivers/misc/pci_endpoint_test.c
Replaces lower into upper case characters in comments and debug printks.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/endpoint/functions/pci-epf-test.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/endpoint/functions/pci-epf
Replaces lower into upper case characters in comments and debug printks.
Signed-off-by: Gustavo Pimentel
---
drivers/misc/pci_endpoint_test.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc
Adds driver's MSI-X support.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/endpoint/functions/pci-epf-test.c | 87 +--
1 file changed, 69 insertions(+), 18 deletions(-)
diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c
b/drivers/pci/endpoint/function
Implements the generic method for calling the get/set callbacks.
Adds the PCI_EPC_IRQ_MSIX type.
Adds the MSI-X callbacks signatures to the ops structure.
Adds sysfs interface for altering the number of MSI-X entries.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/endpoint/pci-ep-cfs.c
Adds a legacy interrupt callback handler. Currently Designware IP doesn't
allow triggering the legacy interrupt.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/pcie-designware-ep.c | 10 ++
drivers/pci/dwc/pcie-designware-plat.c | 3 +--
drivers/pci/dwc/pcie-designw
more
generic and flexible.
Implements MSI-X set/get functions for sysfs interface in order to change
the EP entries number.
Implements EP MSI-X interface for triggering interruptions.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/pci-dra7xx.c | 2 +-
drivers/pci/dwc/pcie-artpec6
@@ -148,15 +148,22 @@ struct pcie_port {
> u64 cfg1_base;
> void __iomem*va_cfg1_base;
> u32 cfg1_size;
> + u32 cfg_idx;
> resource_size_t io_base;
> phys_addr_t io_bus_addr;
> u32 io_size;
> + u32 io_idx;
> u64 mem_base;
> phys_addr_t mem_bus_addr;
> u64 mem_size;
> + u64 mem_perf_base;
> + phys_addr_t mem_perf_bus_addr;
> + u64 mem_perf_size;
> + u32 mem_wins;
> struct resource *cfg;
> struct resource *io;
> struct resource *mem;
> + struct resource *mem_perf;
> struct resource *busn;
> int irq;
> const struct dw_pcie_host_ops *ops;
>
Hi,
It worked perfectly in my setup, however my current configuration have
non-prefetchable memory less than 4Gb. In overall the code seems good.
Acked-by: Gustavo Pimentel
Regards,
Gustavo
Hi Alan,
On 10/07/2018 11:10, Alan Douglas wrote:
> On 09 July 2018 18:43 Gustavo Pimentel wrote:
>> Add MSI-X support and update driver documentation accordingly.
>>
>> Add 2 new IOCTL commands:
>> - Allow to reconfigure driver IRQ type in runtime.
>> - All
Add the DesignWare EP device ID entry to pci_endpoint_test driver table.
Allow the device to be recognize and handle by the pci_endpoint_test
driver.
Signed-off-by: Gustavo Pimentel
Acked-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 1 +
1 file changed, 1 insertion
Add device tree binding documentation for the EP in PCIe DesignWare driver.
Signed-off-by: Gustavo Pimentel
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/pci/designware-pcie.txt | 12
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings
The PCIe controller dual mode is capable of operating in RC mode as well
as EP mode by configuration option. Till now only RC mode was supported,
with this patch is add EP support to the DesignWare driver.
Gustavo Pimentel (4):
bindings: PCI: designware: Example update
PCI: dwc: Add support
Replace "ctrlreg" reg-name by "dbi" to be coherent with similar drivers,
however it still be compatible with any previous DT that uses the old
reg-name.
Replace the PCIe base address example by a real PCIe base address in use.
Signed-off-by: Gustavo Pimentel
Revi
accordingly to the controller specific requirements.
Signed-off-by: Gustavo Pimentel
Acked-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/Kconfig | 41 +--
drivers/pci/dwc/pcie-designware-ep.c | 3 +
drivers/pci/dwc/pcie-designware-plat.c| 149
on EP DesignWare IP driver.
Add a new input parameter (msix) to pcitest tool to test MSI-X feature.
Update the pcitest.sh script to support MSI-X feature tests.
Gustavo Pimentel (10):
PCI: endpoint: Add MSI-X interfaces
PCI: dwc: Add MSI-X callbacks handler
PCI: Update xxx_pcie_ep_raise_irq(
Hi Geert,
On 19/06/2018 18:19, Geert Uytterhoeven wrote:
> PCIE_DW_PLAT_HOST does not have any platform dependency, so it should
> not default to yes.
That's right, thanks.
Regards,
Gustavo
Acked-by: Gustavo Pimentel
>
> Fixes: 1d906b22076e12cf ("PCI: dwc: Add support
Hi,
Just a gentle reminder.
Thanks.
On 21/06/2018 17:01, Gustavo Pimentel wrote:
> Patch series made against Lorenzo's master branch.
>
> Add MSI-X support on pcitest tool.
>
> Add new callbacks methods and handlers to trigger the MSI-X interrupts
> on the EP DesignWar
-by: Gustavo Pimentel
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
drivers/pci/endpoint/pci-ep-cfs.c | 24 +++
drivers/pci/endpoint/pci-epc-core.c | 59 -
include/linux/pci-epc.h | 13 ++--
incl
Change cdns_pcie_ep_raise_irq() signature, namely the interrupt_num
variable type from u8 to u16 to accommodate 2048 maximum MSI-X
interrupts.
Signed-off-by: Gustavo Pimentel
Acked-by: Alan Douglas
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
drivers/
Remove duplicate defines located on pcie-designware.h file already
available on /include/uapi/linux/pci-regs.h file.
Add pci_epc_set_msi() maximum 32 interrupts validation.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
drivers/
rk on set/get and triggering MSI methods on EP DesignWare IP driver.
Add a new input parameter (msix) to pcitest tool to test MSI-X feature.
Update the pcitest.sh script to support MSI-X feature tests.
Gustavo Pimentel (7):
PCI: endpoint: Add MSI-X interfaces
PCI: dwc: Add MSI-X callbacks ha
Add MSI-X support to pcitest tool.
Add 2 new IOCTL commands:
- Allow to reconfigure driver IRQ type in runtime.
- Allow to retrieve current driver IRQ type configured.
Modify pcitest.sh script to accommodate MSI-X interrupt tests.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Al
triggering interruptions.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
drivers/pci/dwc/pci-dra7xx.c | 2 +-
drivers/pci/dwc/pcie-artpec6.c | 2 +-
drivers/pci/dwc/pcie-designware-ep.c |
process, by having in a BAR:
- Interrupt type triggered (added).
- Interrupt ID number (moved from the command section).
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Allow IRQ type driver reconfiguring in runtime, follwing Kishon's
suggestion.
Documentation/misc-devices/pci-
Add a legacy interrupt callback handler. Currently DesignWare IP don't
allow trigger legacy interrupts.
Signed-off-by: Gustavo Pimentel
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
drivers/pci/dwc/pcie-designware-ep.c | 10 ++
drivers/pci/
l)
> {
> - if ((uintptr_t)addr & (size - 1))
> + if (!IS_ALIGNED((uintptr_t)addr, size))
> return PCIBIOS_BAD_REGISTER_NUMBER;
>
> if (size == 4)
>
Sounds good.
Acked-by: Gustavo Pimentel
int size, u32 val);
> int (*host_init)(struct pcie_port *pp);
> - void (*msi_set_irq)(struct pcie_port *pp, int irq);
> - void (*msi_clear_irq)(struct pcie_port *pp, int irq);
> - phys_addr_t (*get_msi_addr)(struct pcie_port *pp);
> - u32 (*get_msi_data)(struct pcie_port *pp, int pos);
> void (*scan_bus)(struct pcie_port *pp);
> void (*set_num_vectors)(struct pcie_port *pp);
> int (*msi_host_init)(struct pcie_port *pp);
> - void (*msi_irq_ack)(int irq, struct pcie_port *pp);
> };
>
> struct pcie_port {
>
Acked-by: Gustavo Pimentel
Regards,
Gustavo
> struct irq_domain *irq_domain;
> struct irq_domain *msi_domain;
> dma_addr_t msi_data;
> + struct irq_chip *msi_irq_chip;
> u32 num_vectors;
> u32 irq_status[MAX_MSI_CTRLS];
> raw_spinlock_t lock;
>
Acked-by: Gustavo Pimentel
Regards,
Gustavo
4, ~0);
> + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE +
> + (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
> + 4, ~0);
> + pp->irq_status[ctrl] = 0;
> + }
> }
>
> /* Setup RC BARs */
>
Acked-by: Gustavo Pimentel
Regards,
Gustavo
size, val);
> - if (pci->num_viewport <= 2)
> - dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
> - PCIE_ATU_TYPE_IO, pp->io_base,
> - pp->io_bus_addr, pp->io_size);
> -
> - return ret;
> + return dw_pcie_access_other_conf(pp, bus, devfn, where, size, &val,
> + true);
> }
>
> static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus,
>
Nice!
Acked-by: Gustavo Pimentel
Regards,
Gustavo
Hi,
On 02/01/2019 18:28, Andrey Smirnov wrote:
> On Wed, Dec 26, 2018 at 7:19 AM Gustavo Pimentel
> wrote:
>>
>> Hi,
>>
>> On 21/12/2018 07:27, Andrey Smirnov wrote:
>>> Avoid using explicit left shifts and convert various definitions to
>>>
PCIE_ATU_TYPE_CFG1 (0x5 << 0)
> +#define PCIE_ATU_TYPE_MEM0x0
> +#define PCIE_ATU_TYPE_IO 0x2
> +#define PCIE_ATU_TYPE_CFG0 0x4
> +#define PCIE_ATU_TYPE_CFG1 0x5
> #define PCIE_ATU_CR2 0x908
> #define PCIE_ATU_ENABLE BIT(31)
> #define PCIE_ATU_BAR_MODE_ENABLE BIT(30)
>
Agree.
Acked-off-by: Gustavo Pimentel
Thanks.
& 0xff) << 24)
> -#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
> -#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
> +#define PCIE_ATU_BUS(x) FIELD_PREP(GENMASK(31, 24), x)
> +#define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x)
> +#define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x)
> #define PCIE_ATU_UPPER_TARGET0x91C
>
> #define PCIE_MISC_CONTROL_1_OFF 0x8BC
>
I wasn't aware of the existence of FIELD_PREP(), seems to be quite handy :)
Acked-by: Gustavo Pimentel
Thanks.
Hi,
On 21/12/2018 07:27, Andrey Smirnov wrote:
> Avoid using explicit left shifts and convert various definitions to
> use BIT() instead. No functional change intended.
>
> Cc: Lorenzo Pieralisi
> Cc: Bjorn Helgaas
> Cc: Fabio Estevam
> Cc: Chris Healy
> Cc: Lucas Stach
> Cc: Leonard Crestez
Hi,
On 21/12/2018 07:26, Andrey Smirnov wrote:
> Everyone:
>
> This is the series containing various small improvements that I made
> while reading the code and researching commit history of pci-imx6.c
> and pcie-designware*.c files. All changes are optional, so commits
> that don't seem like an
0;
>
> error:
> + pci_free_resource_list(&bridge->windows);
> pci_free_host_bridge(bridge);
> return ret;
> }
>
Thanks for the memory leak fix. :)
Acked-by: Gustavo Pimentel
ci);
> void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
> int type, u64 cpu_addr, u64 pci_addr,
> -u32 size);
> +u64 size);
> int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
>u64 cpu_addr, enum dw_pcie_as_type as_type);
> void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
>
Nice catch! :)
Acked-by: Gustavo Pimentel
Cleanup PCI_ENDPOINT_TEST memspace (by moving the interrupt number away
from command section).
Add IRQ_TYPE register to identify the triggered ID interrupt required
for the READ/WRITE/COPY tests and raise IRQ test commands.
Update documentation accordingly.
Signed-off-by: Gustavo Pimentel
Change {cdns, dra7xx, artpec6, dw, rockchip}_pcie_ep_raise_irq() and
pci_epc_raise_irq() signature, namely the interrupt_num variable type
from u8 to u16 to accommodate 2048 maximum MSI-X interrupts.
Signed-off-by: Gustavo Pimentel
Acked-by: Alan Douglas
Acked-by: Shawn Lin
Acked-by: Jesper
Add new driver parameter to allow interruption type selection.
Signed-off-by: Gustavo Pimentel
Acked-by: Kishon Vijay Abraham I
---
Change v2->v3:
- New patch file created base on the previous patch
"misc: pci_endpoint_test: Add MSI-X support" patch file following
Kishon's
> - return err;
> + goto err_free_irq;
> }
>
> /* Saving data structure reference */
> pci_set_drvdata(pdev, chip);
>
> return 0;
> +
> +err_free_irq:
> + pci_free_irq_vectors(pdev);
> + return err;
> }
>
> static void dw_edma_pcie_remove(struct pci_dev *pdev)
> --
> 2.25.0
Acked-by: Gustavo Pimentel
On Wed, Apr 7, 2021 at 7:17:12, Greg Kroah-Hartman
wrote:
> On Tue, Apr 06, 2021 at 11:17:48PM +0200, Gustavo Pimentel wrote:
> > Fixes indentation issues reported by doing *make htmldocs* as well some
> > text formatting.
> >
> > Besides these fixes, there wa
Cc: Greg Kroah-Hartman
Cc: Jonathan Corbet
Cc: Bjorn Helgaas
Cc: Krzysztof Wilczy??ski
Cc: Stephen Rothwell
Gustavo Pimentel (2):
dw-xdata-pcie: Fix documentation build warns and update outdated info
misc-device: Add dw-xdata-pcie to toctree(index)
Documentation/misc-devices/dw-xdata-pci
xdata-pcie driver")
Link:
https://lore.kernel.org/linux-next/20210406214615.40cf3...@canb.auug.org.au/
Reported-by: Stephen Rothwell
Signed-off-by: Gustavo Pimentel
---
Documentation/misc-devices/dw-xdata-pcie.rst | 62 +++-
1 file changed, 43 insertions(+), 19
bbc3c ("Documentation: misc-devices: Add Documentation for
dw-xdata-pcie driver")
Link:
https://lore.kernel.org/linux-next/20210406214615.40cf3...@canb.auug.org.au/
Reported-by: Stephen Rothwell
Signed-off-by: Gustavo Pimentel
---
Documentation/misc-devices/index.rst | 1 +
1 file chang
On Wed, Apr 7, 2021 at 18:35:16, Greg Kroah-Hartman
wrote:
> On Wed, Apr 07, 2021 at 03:57:31PM +0000, Gustavo Pimentel wrote:
> > On Wed, Apr 7, 2021 at 7:17:12, Greg Kroah-Hartman
> > wrote:
> >
> > > On Tue, Apr 06, 2021 at 11:17:48PM +0200, Gustavo
Hi Kishon,
On 02/04/2018 06:36, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Wednesday 28 March 2018 05:08 PM, Gustavo Pimentel wrote:
>> Adds the designware EP device ID entry to pci_endpoint_test driver table
>> to allow this device to be recognize and handle by the pci_en
Hi Kishon,
On 02/04/2018 06:23, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Wednesday 28 March 2018 05:08 PM, Gustavo Pimentel wrote:
>> Changes the IP registers size to accommodate the ATU unroll space.
>>
>> Replaces "ctrlreg" reg-name by &quo
Hi Kishon,
On 02/04/2018 06:35, Kishon Vijay Abraham I wrote:
>
>
> On Wednesday 28 March 2018 05:08 PM, Gustavo Pimentel wrote:
>> Signed-off-by: Gustavo Pimentel
>
> Please add a commit message.
Ok. I'll add. Thanks for noticing it.
>> ---
>>
Hi Kishon,
On 03/04/2018 11:53, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 03 April 2018 04:22 PM, Kishon Vijay Abraham I wrote:
>>
>>
>> On Tuesday 03 April 2018 04:03 PM, Gustavo Pimentel wrote:
>>> Hi Kishon,
>>>
>>> On 0
Hi Kishon,
On 03/04/2018 11:55, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 03 April 2018 04:13 PM, Gustavo Pimentel wrote:
>> Hi Kishon,
>>
>> On 02/04/2018 06:35, Kishon Vijay Abraham I wrote:
>>>
>>>
>>> On Wednesday 28 March 201
On 02/04/2018 06:34, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Wednesday 28 March 2018 05:08 PM, Gustavo Pimentel wrote:
>> The PCIe controller dual mode is capable of operating in host mode as well
>> as endpoint mode by configuration, therefore this patch aims to add
>
Hi Lorenzo,
On 04/04/2018 12:50, Lorenzo Pieralisi wrote:
> On Wed, Mar 28, 2018 at 12:38:33PM +0100, Gustavo Pimentel wrote:
>
> Please always write a commit log even if it is trivial.
Ok, Kishon has also refered that. On next patch version it'll contain a log
description
Adds the designware EP device ID entry to pci_endpoint_test driver table
to allow this device to be recognize and handle by the pci_endpoint_test
driver.
Signed-off-by: Gustavo Pimentel
---
drivers/misc/pci_endpoint_test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc
Signed-off-by: Gustavo Pimentel
---
Documentation/devicetree/bindings/pci/designware-pcie.txt | 13 +
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 6300762
Replace magic numbers by a well known define in order to make the code
human readable and also facilitate the code reusability.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/pcie-designware-host.c | 34 --
drivers/pci/dwc/pcie-designware.h | 1 +
2
that helps the human compreension.
- Replaces a division by 2 by a simple right shift rotation of 1 bit.
- Fixes all first letter characters on comments and debug messages to
upper case to maintain coherency.
Gustavo Pimentel (8):
bindings: PCI: designware: Example update
PCI: dwc: desig
Changes the IP registers size to accommodate the ATU unroll space.
Replaces "ctrlreg" reg-name by "dbi" to be coherent with similar drivers.
Replaces the pcie base address example by a real pcie base address in use.
Signed-off-by: Gustavo Pimentel
---
Documentation/dev
-by: Gustavo Pimentel
---
drivers/pci/dwc/pcie-designware-plat.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/dwc/pcie-designware-plat.c
b/drivers/pci/dwc/pcie-designware-plat.c
index 921ab07..11271bb 100644
--- a/drivers/pci/dwc/pcie-designware-plat.c
+++ b/drivers/pci
Replaces lower into upper case characters in comments and debug printks.
This is an attempt to keep the messages coherent within the designware
driver.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/pcie-designware-ep.c | 16
drivers/pci/dwc/pcie-designware-host.c | 35
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