- Dt-bindings doc for gx6605s SOC's system timer.
Signed-off-by: Guo Ren
Reviewed-by: Rob Herring
---
.../bindings/timer/csky,gx6605s-timer.txt | 42 ++
1 file changed, 42 insertions(+)
create mode 100644
Documentation/devicetree/bindings/timer/csky,gx
Changelog:
- Add License and Copyright
- Use timer-of framework
- Change name with upstream feedback
- Use clksource_mmio framework
Signed-off-by: Guo Ren
---
drivers/clocksource/Kconfig | 8 ++
drivers/clocksource/Makefile| 1 +
drivers/clocksource/timer-gx6605s.c | 150
- Dt-bindings doc about C-SKY Multi-processors interrupt controller.
Signed-off-by: Guo Ren
---
.../bindings/interrupt-controller/csky,mpintc.txt | 40 ++
1 file changed, 40 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/csky
Guo Ren (2):
irqchip: add C-SKY APB bus interrupt controller
dt-bindings: interrupt-controller: C-SKY APB intc
.../interrupt-controller/csky,apb-intc.txt | 70 ++
drivers/irqchip/Kconfig| 8 +
drivers/irqchip/Makefile | 1
- Dt-bindings doc about C-SKY apb bus interrupt controller.
Signed-off-by: Guo Ren
---
.../interrupt-controller/csky,apb-intc.txt | 70 ++
1 file changed, 70 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
rq-pending
- remove CSKY_VECIRQ_LEGENCY
- change to generic irq chip framework
- add License and Copyright
- use irq_domain_add_linear instead of leagcy
Signed-off-by: Guo Ren
---
drivers/irqchip/Kconfig | 8 ++
drivers/irqchip/Makefile| 1 +
drivers/irqchip/irq-c
& private_irq space
- add License and Copyright
- support set_affinity for irq balance in SMP
Signed-off-by: Guo Ren
---
drivers/irqchip/Kconfig | 16
drivers/irqchip/Makefile | 2 +
drivers/irqchip/irq-csky-mpintc.c | 196 ++
3 f
Guo Ren (2):
irqchip: add C-SKY SMP interrupt controller
dt-bindings: interrupt-controller: C-SKY SMP intc
.../bindings/interrupt-controller/csky,mpintc.txt | 40 +
drivers/irqchip/Kconfig| 16 ++
drivers/irqchip/Makefile | 2
On Tue, Sep 18, 2018 at 05:56:50PM -0700, Rob Herring wrote:
> > > but does need a vendor prefix.
> > vendor prefix? Em ... it's just used in fpga now.
>
> What I mean is make it: csky,support-pulse-signal
Ok. no problem.
Best Regards
Guo Ren
Sorry, I missed people on the list.
F.Y.I
Waiman Long
Boqun Feng
Here is Link:
https://lore.kernel.org/linux-riscv/20231225125847.2778638-1-guo...@kernel.org/
On Mon, Dec 25, 2023 at 8:59 PM wrote:
>
> From: Guo Ren
>
> patch[1 - 8]: Native qspinlock
> patch[9 -14]: Par
On Mon, Feb 19, 2024 at 11:40 PM Anna-Maria Behnsen
wrote:
>
> CSKY selects GENERIC_TIME_VSYSCALL. GENERIC_TIME_VSYSCALL dependent
> ifdeffery is superfluous. Clean it up.
>
> Signed-off-by: Anna-Maria Behnsen
> Cc: Guo Ren
> Cc: linux-c...@vger.kernel.org
> ---
> a
On Mon, Feb 19, 2024 at 11:40 PM Anna-Maria Behnsen
wrote:
>
> There is already a generic union definition for vdso_data_store in vdso
> datapage header.
>
> Use this definition to prevent code duplication.
>
> Signed-off-by: Anna-Maria Behnsen
> Cc: Guo Ren
> Cc:
> CPU out of idle, as opposed to setting TIF_NEED_RESCHED previously. This
> avoids spurious calls to schedule_idle() in cases where an IPI does not
> necessarily wake up a task on the idle CPU.
>
> Cc: Guo Ren
> Cc: "Rafael J. Wysocki"
> Cc: Daniel Lezcano
> Cc: I
;< PAGE_SHIFT);
Oh, that's a terrible bug; Thx for fixing it.
Reviewed-by: Guo Ren
> }
> #define pfn_to_virt pfn_to_virt
>
> --
> 2.17.1
>
--
Best Regards
Guo Ren
h/csky/include/asm/page.h
> @@ -84,7 +84,7 @@ static inline unsigned long virt_to_pfn(const void *kaddr)
>
> static inline void * pfn_to_virt(unsigned long pfn)
> {
> - return (void *)((unsigned long)__va(pfn) << PAGE_SHIFT);
> + return __va(pfn << PAGE_
On Fri, Mar 08, 2024 at 05:18:21PM +0800, Andy Chiu wrote:
> Hi Puranjay,
>
> On Fri, Mar 8, 2024 at 3:53 AM Puranjay Mohan wrote:
> >
> > Hi Björn,
> >
> > On Thu, Mar 7, 2024 at 8:27 PM Björn Töpel wrote:
> > >
> > > Puranjay!
> > >
> > > Puranjay Mohan writes:
> > >
> > > > This patch enable
On Mon, Oct 9, 2023 at 8:42 PM Masahiro Yamada wrote:
>
> You cannot run this code because arch/csky/Makefile does not define the
> vdso_install target.
>
> It appears that this code was blindly copied from another architecture.
Yes, I do that. Thx for pointing it out.
Ac
; -endef
> -
> -vdso_img_insttargets := $(vdso_img_sodbg:%.dbg=install_%)
> -
> -$(MODLIB)/vdso: FORCE
> - @mkdir -p $(MODLIB)/vdso
> -
> -$(vdso_img_insttargets): install_%: $(obj)/%.dbg $(MODLIB)/vdso
> - $(call cmd,vdso_install)
> -
> -PHONY += vdso_install $(vdso_img_insttargets)
> -vdso_install: $(vdso_img_insttargets)
> -
> clean-files := vdso32.so vdso32.so.dbg vdso64* vdso-image-*.c vdsox32.so*
> diff --git a/scripts/Makefile.vdsoinst b/scripts/Makefile.vdsoinst
> new file mode 100644
> index ..1022d9fdd976
> --- /dev/null
> +++ b/scripts/Makefile.vdsoinst
> @@ -0,0 +1,45 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +# ==
> +# Install unstripped copies of vDSO
> +# ==
> +
> +PHONY := __default
> +__default:
> + @:
> +
> +include $(srctree)/scripts/Kbuild.include
> +
> +install-dir := $(MODLIB)/vdso
> +
> +define gen_install_rules
> +
> +src := $$(firstword $$(subst :,$(space),$(1)))
> +dest := $(install-dir)/$$(or $$(word 2,$$(subst
> :,$(space),$(1))),$$(patsubst %.dbg,%,$$(notdir $(1
> +
> +__default: $$(dest)
> +$$(dest): $$(src) FORCE
> + $$(call cmd,install)
> +
> +# Some architectures create .build-id symlinks
> +ifneq ($(filter arm sparc x86, $(SRCARCH)),)
> +link := $(install-dir)/.build-id/$$(shell $(READELF) -n $$(src) | sed -n
> 's@^.*Build ID: \(..\)\(.*\)@\1/\2@p')
> +
> +__default: $$(link)
> +$$(link): $$(dest) FORCE
> + $$(call cmd,symlink)
> +endif
> +
> +endef
> +
> +$(foreach x, $(sort $(INSTALL_FILES)), $(eval $(call
> gen_install_rules,$(x
> +
> +quiet_cmd_install = INSTALL $@
> + cmd_install = mkdir -p $(dir $@); cp $< $@
> +
> +quiet_cmd_symlink = SYMLINK $@
> + cmd_symlink = mkdir -p $(dir $@); ln -sf --relative $< $@
> +
> +PHONY += FORCE
> +FORCE:
> +
> +.PHONY: $(PHONY)
> --
> 2.39.2
>
--
Best Regards
Guo Ren
On Wed, Oct 11, 2023 at 8:53 PM Masahiro Yamada wrote:
>
> On Wed, Oct 11, 2023 at 11:24 AM Guo Ren wrote:
> >
> > On Mon, Oct 9, 2023 at 8:42 PM Masahiro Yamada wrote:
>
> > > --- a/arch/riscv/Makefile
> > > +++ b/arch/riscv/Makefile
> > > @@ -13
On Sun, Oct 15, 2023 at 01:20:42AM +0200, Alejandro Colomar wrote:
> Hi Guo,
>
> On Tue, Nov 24, 2020 at 08:07:07PM +0800, Guo Ren wrote:
>
> Huh, 3 years already! I've had this in my head for all this time; just
> didn't find the energy to act on it.
&g
On Mon, Oct 16, 2023 at 2:00 AM Alejandro Colomar wrote:
>
> Hi Guo,
>
> On Sun, Oct 15, 2023 at 11:07:32AM -0400, guo...@kernel.org wrote:
> > From: Guo Ren
> >
> > C-SKY only needs set_thread_area, no need for get_thread_area, the
> > same as MIPS.
> &
may I keep current design for abiv1&abiv2?
In abiv3, we will take your advice seriously.
Best Regards
Guo Ren
On Tue, Mar 27, 2018 at 09:48:23AM +0200, Arnd Bergmann wrote:
> On Tue, Mar 27, 2018 at 4:21 AM, Guo Ren wrote:
> > On Mon, Mar 26, 2018 at 03:16:31PM +0200, Arnd Bergmann wrote:
>
> >> > +CONFIG_CFG80211=y
> >> > +CONFIG_CFG80211_DEBUGFS=y
> >> >
ble at the kernel level.
Best Regards
Guo Ren
use I know USER & GLOBAL are conceptually very different, but
there are only 10 attribute-bits for riscv (In fact we've wasted two bits
to support huge RV32-pfn :P). So I think it is time to merge these two bits
before hardware supports GLOBAL. Reserve them for future!
Best Regards
Guo Ren
Hypervisor use 2-stages TLB translation in hardware and shadow page
tables is for stage 2 translation. Shadow page tables care vmid not
asid.
If hardware don't support H-extension (MMU 2-stages translation), it's
hard to accept for virtualization performance.
I don't think hypervisor is a real scene for GLOBAL in PTE.
Are there other scene for GLOBAL in PTE?
Best Regards
Guo Ren
PERF_REG_CSKY_##r); \
> + val;\
> +})
> +
> + dwarf_regs[0] = REG(R0);
> + dwarf_regs[1] = REG(R1);
> + dwarf_regs[2] = REG(R2);
> + dwarf_regs[3] = REG(R3);
> + dwarf_regs[4] = REG(R4);
> + dwarf_regs[5] = REG(R5);
> + dwarf_regs[6] = REG(R6);
> + dwarf_regs[7] = REG(R7);
> + dwarf_regs[8] = REG(R8);
> + dwarf_regs[9] = REG(R9);
> + dwarf_regs[10] = REG(R10);
> + dwarf_regs[11] = REG(R11);
> + dwarf_regs[12] = REG(R12);
> + dwarf_regs[13] = REG(R13);
> + dwarf_regs[14] = REG(SP);
> + dwarf_regs[15] = REG(LR);
> + dwarf_regs[16] = REG(R16);
> + dwarf_regs[17] = REG(R17);
> + dwarf_regs[18] = REG(R18);
> + dwarf_regs[19] = REG(R19);
> + dwarf_regs[20] = REG(R20);
> + dwarf_regs[21] = REG(R21);
> + dwarf_regs[22] = REG(R22);
> + dwarf_regs[23] = REG(R23);
> + dwarf_regs[24] = REG(R24);
> + dwarf_regs[25] = REG(R25);
> + dwarf_regs[26] = REG(R26);
> + dwarf_regs[27] = REG(R27);
> + dwarf_regs[28] = REG(R28);
> + dwarf_regs[29] = REG(R29);
> + dwarf_regs[30] = REG(R30);
> + dwarf_regs[31] = REG(TLS);
> + dwarf_regs[32] = REG(PC);
> + dwfl_thread_state_register_pc(thread, dwarf_regs[32]);
> +
> + return dwfl_thread_state_registers(thread, 0, PERF_REG_CSKY_MAX,
> +dwarf_regs);
> +}
Try LIBUNWIND__ARCH_REG_ID, see:
tools/perf/arch/arm64/util/unwind-libunwind.c
Best Regards
Guo Ren
> are not implemented on SiFive Unleashed board so we don't see any change
> in performance.
Can you tell me what is the test case ?
Best Regards
Guo Ren
Hi Daniel,
On Wed, Feb 10, 2021 at 4:26 AM Daniel Lezcano
wrote:
>
> On 09/02/2021 17:02, Guo Ren wrote:
> > Hi Daniel,
> >
> > On Sun, Feb 7, 2021 at 5:29 PM Daniel Lezcano
> > wrote:
> >>
> >> On 07/02/2021 04:31, Guo Ren wrote:
> >&g
remove the conflict.
> (although e1000 is also a 2-line change)
>
> Not tested: I don't have a build toolchain for CSKY.
>
> Signed-off-by: Randy Dunlap
> Reported-by: kernel test robot
> Cc: Jesse Brandeburg
> Cc: Tony Nguyen
> Cc: intel-wired-...@lists.os
Thx Marc,
On Wed, Feb 3, 2021 at 11:44 PM Marc Zyngier wrote:
>
> On 2021-02-03 13:48, guo...@kernel.org wrote:
> > From: Guo Ren
> >
> > The irq-csky-mpintc.c only could support CPU_CK860 and it will
> > compile error with CPU_CK610.
> >
> > Si
if (hwirq == 0)
> - return 0;
> + return false;
>
> handle_domain_irq(root_domain, irq_base + __fls(hwirq), regs);
>
> - return 1;
> + return true;
> }
>
> /* gx6605s 64 irqs interrupt controller */
> --
> 1.8.3.1
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
Hi Daniel,
On Sun, Feb 7, 2021 at 5:29 PM Daniel Lezcano wrote:
>
> On 07/02/2021 04:31, Guo Ren wrote:
> > Hi Daniel,
> >
> > On Thu, Feb 4, 2021 at 4:48 PM Daniel Lezcano
> > wrote:
> >>
> >> On 04/02/2021 08:46, guo...@kernel.org wrote:
>
Thx Arnd,
I'm very glad to see C-SKY & RISC-V features updated.
Signed-off-by: Guo Ren
On Thu, Feb 25, 2021 at 10:29 PM Arnd Bergmann wrote:
>
> From: Arnd Bergmann
>
> Run the update script to document the recent feature additions
> on riscv, mips and csky.
>
&
Reviewed-by: Guo Ren
On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote:
>
> From: Guo Ren
>
> This patch is used to detect vector support status of CPU and use
> riscv_vsize to save the size of all the vector registers. It assumes
> all harts has the same capabili
tioned above, vxrm and vxsat are thread storage duration.
When timer 's interrupt coming, we still need to save them in context_switch.
On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote:
>
> From: Guo Ren
>
> Follow the riscv vector spec to add new csr number.
>
> [greentim
Hi Greentime,
On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote:
>
> From: Guo Ren
>
> This patch adds sigcontext save/restore for vector. The vector registers
> will be saved in datap pointer. The datap pointer will be allocaed
> dynamically when the task needs in kerne
Hi Greentime,
On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote:
>
> From: Guo Ren
>
> This patch adds task switch support for vector. It supports lazy
> save and restore mechanism. It also supports all lengths of vlen.
>
> [greentime...@sifive.com: add support
typo "vecotr, fstate_save->vstate_save".
> - Fixup wrong saved registers' length in vector.S.
> - Seperate unrelated patches from this one.
>
> Greentime Hu (1):
> ptrace: Use regset_size() for dynamic regset size.
>
> Guo Ren (11):
> riscv: Separate patch
only need switch_context or sigcontext vector when the flag is set.
On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote:
>
> From: Guo Ren
>
> This patch adds task switch support for vector. It supports lazy
> save and restore mechanism. It also supports all lengths of vlen.
On Mon, Jun 1, 2020 at 4:15 PM Greentime Hu wrote:
>
> Guo Ren 於 2020年5月31日 週日 上午9:56寫道：
> >
> > Hi Greentime,
> >
> > Why remove vxrm and xstat ?
> >
> > > Appendix B: Calling Convention
> > > In the RISC-V psABI, the vector registers v
Since it has been redesigned with new version spec, please change the
first-author :)
And add me as Co-developed.
On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote:
>
> From: Guo Ren
>
> Follow the riscv vector spec to add new csr number.
>
> [greentime...@sifive.com: update
Since it has been redesigned with new version spec, please change the
first-author :)
And add me as Co-developed.
On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote:
>
> From: Guo Ren
>
> Add vector state context struct in struct thread and asm-offsets.c
> definitions.
>
>
Since it has been redesigned with new version spec, please change the
first-author :)
And add me as Co-developed.
On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote:
>
> From: Guo Ren
>
> This patch adds task switch support for vector. It supports lazy
> save and restore mec
Since it has been redesigned with new version spec, please change the
first-author :)
And add me as Co-developed.
On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote:
>
> From: Guo Ren
>
> This patch adds sigcontext save/restore for vector. The vector registers
> will be saved i
Since it has been redesigned with new version spec, please change the
first-author :)
And add me as Co-developed.
On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote:
>
> From: Guo Ren
>
> This patch is used to detect vector support status of CPU and use
> riscv_vsize to save
Since it has been redesigned with new version spec, please change the
first-author :)
And add me as Co-developed.
On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote:
>
> From: Guo Ren
>
> This patch adds ptrace support for riscv vector. The vector registers will
> be saved in d
BTW, PLIC does not handle MSI and does not have virtualization support
> pass-through interrupts. We will most likely see a new RISC-V interrupt
> controller spec for these capabilities.
>
> Also, the PLIC spec is now owned by RISC-V foundation (not SiFive) so
> we will have to rename the driver to "irq-riscv-plic" and will have a new
> generic compatible string "riscv,plic-1.0.0". One of us (me or Palmer) will
> send separate patches for this renaming. I hope you will be fine with this??
> (Refer, https://github.com/riscv/riscv-plic-spec)
That's great, we follow riscv-plic in hardware, but don't want to use
sifive string in dts.
Acked & Thx for the job.
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
On Tue, Jun 2, 2020 at 10:21 AM Greentime Hu wrote:
>
> Guo Ren 於 2020年5月31日 週日 下午11:52寫道：
> >
> > Hi Greentime & Vincent,
> >
> > Thx for the dynamic vlen implementation. I've two suggestions:
> > - Please give out glibc patches mail URL, we ne
Hi Guenter,
> 在 2020年5月18日，上午1:52，Guenter Roeck 写道：
>
> Hi,
>
> On Wed, May 13, 2020 at 03:15:25PM +0800, Guo Ren wrote:
>> The implementation of show_stack will panic with wrong fp:
>>
>> addr= *fp++;
>>
>> because the fp isn't check
edded scenario, qspinlock seems a bit heavy, are any
tickets-like comm spinlock infrastructures in the plan?
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
Acked-by: Guo Ren
On Thu, Aug 6, 2020 at 3:55 AM wrote:
>
> On Wed, Aug 05, 2020 at 12:41:46PM +0200, pet...@infradead.org wrote:
> > Hi,
> >
> > While doing an audit of smp_mb__after_spinlock, I found that csky
> > defines it, why?
> >
> > C
On Thu, Aug 6, 2020 at 11:48 PM Steven Rostedt wrote:
>
> On Thu, 6 Aug 2020 14:50:54 +
> guo...@kernel.org wrote:
>
> > From: Guo Ren
> >
> > The function ftrace_process_locs() will modify text code, so we
> > should give a text_mutex lock. Because so
On Fri, Aug 7, 2020 at 12:01 PM Steven Rostedt wrote:
>
> On Fri, 7 Aug 2020 10:59:16 +0800
> Guo Ren wrote:
> > >
> > > This looks like a bug in the lockdep_assert_held() in whatever arch
> > > (riscv) is running.
> > Seems you think it's a bug of
not.
> + if (!csky_insn_reg_get_val(regs, tmp, &val)) {
> instruction_pointer_set(regs,
> addr + sign_extend32((opcode & 0x) >> 15,
> 15));
> } else
> --
> 2.17.1
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
Hi Zhengzhong,
I'll take it, thx.
On Wed, Dec 23, 2020 at 10:31 AM Zhenzhong Duan
wrote:
>
> On Wed, Sep 23, 2020 at 12:52 PM Al Viro wrote:
> >
> > On Wed, Sep 23, 2020 at 10:37:31AM +0800, Guo Ren wrote:
> >
> > > > What's going on there? The
On Tue, Jan 12, 2021 at 4:18 PM Atish Patra wrote:
>
> On Mon, Jan 11, 2021 at 6:38 PM wrote:
> >
> > From: Guo Ren
> >
> > PAGE_KERNEL_EXEC has been defined above.
> >
> > Signed-off-by: Guo Ren
> > Cc: Palmer Dabbelt
> > Cc: Pekka Enb
odes could be
> > re-used directly.
> >
> > if HAVE_TCM
> >
>
> LGTM. Thanks.
> Reviewed-by: Randy Dunlap
>
> --
> ~Randy
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
_unlock(arch_spinlock_t *lock)
> > {
> > + smp_store_release(&lock->tickets.owner, lock->tickets.owner + 1);
> > + /* FIXME - we need ipi/sev here to notify above */
> > }
>
> Urgh, are you saying your WFE requires an explicit SEV like on ARM ? The
Yes, I'm considering that kind of code.
> ARM64 model is far superious IMO, and then you can use
> smp_cond_load_acquire() in arch_spin_lock() and call it a day.
Great tip, thx. I'll follow that.
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
On Wed, Mar 24, 2021 at 7:16 PM Vitaly Wool wrote:
>
>
>
> On Wed, Mar 24, 2021, 11:16 AM wrote:
>>
>> From: Guo Ren
>>
>> This patch introduces a ticket lock implementation for riscv, along the
>> same lines as the implementation for arch/arm &am
qspinlock *lock)
> 59fb586b4a07b4 Will Deacon2018-04-26 195 {
> 59fb586b4a07b4 Will Deacon2018-04-26 196
> atomic_andnot(_Q_PENDING_VAL, &lock->val);
> 59fb586b4a07b4 Will Deacon2018-04-26 197 }
> 59fb586b4a07b4 Will Deacon2018-04-26 198
>
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
uot; slliw %0, %0, 16 \n" \
- " srliw %0, %0, 16 \n" \
+ __ASM_SLLIW"%0, %0, 16 \n" \
+ __ASM_SRLIW"%0, %0, 16 \n"
On Tue, Mar 30, 2021 at 3:12 PM Arnd Bergmann wrote:
>
> On Tue, Mar 30, 2021 at 4:26 AM Guo Ren wrote:
> > On Mon, Mar 29, 2021 at 9:56 PM Arnd Bergmann wrote:
> > > On Mon, Mar 29, 2021 at 2:52 PM Guo Ren wrote:
> > > > On Mon, Mar 29, 2021 at 7:31
Hi Arnd
On Wed, Mar 31, 2021 at 12:18 PM Guo Ren wrote:
>
> On Tue, Mar 30, 2021 at 3:12 PM Arnd Bergmann wrote:
> >
> > On Tue, Mar 30, 2021 at 4:26 AM Guo Ren wrote:
> > > On Mon, Mar 29, 2021 at 9:56 PM Arnd Bergmann wrote:
> > > > On Mon,
On Tue, Mar 30, 2021 at 10:09 PM Waiman Long wrote:
>
> On 3/29/21 11:13 PM, Guo Ren wrote:
> > On Mon, Mar 29, 2021 at 8:50 PM Peter Zijlstra wrote:
> >> On Mon, Mar 29, 2021 at 08:01:41PM +0800, Guo Ren wrote:
> >>> u32 a = 0x55aa66bb;
>
.
>
> > The common code can then build cmpxchg16()/xchg16() on top of
> > either the 16-bit or the 32-bit primitives, and build the cmpxchg()/xchg()
> > wrapper around those (or alternatively we can decide to have them
> > only deal with fixed-32-bit and long/pointer sized atomics).
>
> Yeah, that was the idea.
>
> -Stafford
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
On Mon, Mar 29, 2021 at 8:50 PM Peter Zijlstra wrote:
>
> On Mon, Mar 29, 2021 at 08:01:41PM +0800, Guo Ren wrote:
> > u32 a = 0x55aa66bb;
> > u16 *ptr = &a;
> >
> > CPU0 CPU1
> > = ==
anged, 1 deletion(-)
>
> diff --git a/arch/csky/kernel/entry.S b/arch/csky/kernel/entry.S
> index c1bd7a6b4ab6..00e3c8ebf9b8 100644
> --- a/arch/csky/kernel/entry.S
> +++ b/arch/csky/kernel/entry.S
> @@ -9,7 +9,6 @@
> #include
> #include
> #include
> -#include
>
On Mon, Mar 29, 2021 at 3:50 PM Peter Zijlstra wrote:
>
> On Sat, Mar 27, 2021 at 06:06:38PM +, guo...@kernel.org wrote:
> > From: Guo Ren
> >
> > Some architectures don't have sub-word swap atomic instruction,
> > they only have the full word's one
On Mon, Mar 29, 2021 at 7:26 PM Peter Zijlstra wrote:
>
> On Mon, Mar 29, 2021 at 07:19:29PM +0800, Guo Ren wrote:
> > On Mon, Mar 29, 2021 at 3:50 PM Peter Zijlstra wrote:
> > >
> > > On Sat, Mar 27, 2021 at 06:06:38PM +, guo...@kernel.org wrote:
> > >
egardless of success or failure, executing an SC.W instruction
*invalidates any reservation held by this hart*.
More details, ref:
https://github.com/riscv/riscv-isa-manual
> And what if you double loop it like cmpxchg() ?
Can you give a code snippet?
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
On Mon, Mar 29, 2021 at 9:56 PM Arnd Bergmann wrote:
>
> On Mon, Mar 29, 2021 at 2:52 PM Guo Ren wrote:
> >
> > On Mon, Mar 29, 2021 at 7:31 PM Peter Zijlstra wrote:
> > >
> > > On Mon, Mar 29, 2021 at 01:16:53PM +0200, Peter Zijlstra wrote:
> > &
On Mon, Mar 29, 2021 at 8:50 PM Peter Zijlstra wrote:
>
> On Mon, Mar 29, 2021 at 08:01:41PM +0800, Guo Ren wrote:
> > u32 a = 0x55aa66bb;
> > u16 *ptr = &a;
> >
> > CPU0 CPU1
> > = ==
On Tue, Mar 30, 2021 at 1:51 PM Anup Patel wrote:
>
> On Tue, Mar 30, 2021 at 7:56 AM Guo Ren wrote:
> >
> > On Mon, Mar 29, 2021 at 9:56 PM Arnd Bergmann wrote:
> > >
> > > On Mon, Mar 29, 2021 at 2:52 PM Guo Ren wrote:
> > > >
> &
On Tue, Mar 30, 2021 at 12:54 PM Anup Patel wrote:
>
>
>
> > -Original Message-----
> > From: Guo Ren
> > Sent: 30 March 2021 08:44
> > To: Peter Zijlstra
> > Cc: linux-riscv ; Linux Kernel Mailing List
> > ; linux-c...@vger.kernel.org; linu
On Sun, Mar 28, 2021 at 2:43 AM Waiman Long wrote:
>
> On 3/27/21 2:06 PM, guo...@kernel.org wrote:
> > From: Guo Ren
> >
> > Some architectures don't have sub-word swap atomic instruction,
> > they only have the full word's one.
> >
> >
Thx Arnd,
On Sun, Mar 28, 2021 at 5:25 AM Arnd Bergmann wrote:
>
> On Sat, Mar 27, 2021 at 7:06 PM wrote:
> >
> > From: Guo Ren
> >
> > To reduce assembly codes, let's merge duplicate codes into one
> > (xchg_acquire, xchg_release, cmpxchg_release).
&g
On Sun, Mar 28, 2021 at 7:14 PM Christophe Leroy
wrote:
>
>
>
> Le 28/03/2021 à 08:30, guo...@kernel.org a écrit :
> > From: Guo Ren
> >
> > We don't have native hw xchg16 instruction, so let qspinlock
> > generic code to deal with it.
>
> We ha
t; ATOMIC_OPS(and, and, i)
> > ATOMIC_OPS( or, or, i)
> > ATOMIC_OPS(xor, xor, i)
> > +ATOMIC_OPS(andnot, and, -i)
>
> ~i, surely.
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
or, i)
> > ATOMIC_OPS(xor, xor, i)
> > +ATOMIC_OPS(andnot, and, -i)
>
> ~i, surely.
Thx for correct me. I'll fix it in the next version patch.
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
Abandoned, it has duplicated definition export in gen-atomic-instrumented.sh
On Sat, Apr 17, 2021 at 10:57 AM wrote:
>
> From: Guo Ren
>
> Current GENERIC_ATOMIC64 in atomic-arch-fallback.h is broken. When a 32-bit
> arch use atomic-arch-fallback.h will cause compile error.
>
Acked-by: Guo Ren
It's a fallthrough is for BCACHE, but affects ICACHE with more
expensive. I'll fix up it later.
}
On Mon, Apr 12, 2021 at 12:41 AM Randy Dunlap wrote:
>
> This case of the switch statement falls through to the following case.
> This appears t
load_acquire_reserved(lock);
> if (l.owner != l.next)
> return 0;
> l.next++;
> success = __smp_store_release_conditional(lock, l.v32);
It's a new semantics v.s cmpxchg, and cmpxchg is come from CAS
instruction to solve some complex scenario.
The primitiv
; method readb() uses. Having the offset equal to the resource means that
> the '(void *)0' start is correct.
>
> As this leaves only two others, I checked those as well:
>
> csky does not actually have a PCI host bridge driver at the moment, so
> we don't care about breaki
an exclusive store,
since it may result in having to retry the transaction.
This patch prefixes our {spin,read,write}_[try]lock implementations with
pldw instructions (on CPUs which support them) to try and grab the line
in exclusive state from the start. arch_rwlock_t is changed to avoid
using a volatile member, since this generates compiler warnings when
falling back on the __builtin_prefetch intrinsic which expects a const
void * argument.
Acked-by: Nicolas Pitre
Signed-off-by: Will Deacon
In the end, I want to conclude my suggestions here:
- Using ticket-lock as default
- Using ARCH_USE_QUEUED_SPINLOCKS_XCHG32 for riscv qspinlock
- Disable xhg16/cmxchg16 and any sub-word atomic primitive in riscv
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
gt; void unlock(atomic_t *lock)
> > {
> > u16 *ptr = (u16 *)lock + (!!__BIG_ENDIAN__);
> > u32 val = atomic_read(lock);
> >
> > smp_store_release(ptr, (u16)val + 1);
> > }
> >
> > That's _almost_ as simple as a test-and-set :-) It
.
>
> David
>
> -
> Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1
> 1PT, UK
> Registration No: 1397386 (Wales)
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
perfer:
return !arch_spin_value_unlocked(READ_ONCE(*lock));
> +}
> +
> +static __always_inline int ticket_is_contended(arch_spinlock_t *lock)
> +{
> + u32 val = atomic_read(lock);
> +
> + return (s16)((val >> 16) - (val & 0x)) > 1;
How big-endian ?
return (tickets.next - tickets.owner) > 1;
> +}
> +
> +static __always_inline int ticket_value_unlocked(arch_spinlock_t lock)
> +{
> + return !ticket_is_locked(&lock);
Are you sure to let ticket_is_locked->atomic_read(lock) again, the
lock has contained all information?
return lock.tickets.owner == lock.tickets.next;
> +}
> +
> +#define arch_spin_lock(l) ticket_lock(l)
> +#define arch_spin_trylock(l) ticket_trylock(l)
> +#define arch_spin_unlock(l)ticket_unlock(l)
> +#define arch_spin_is_locked(l) ticket_is_locked(l)
> +#define arch_spin_is_contended(l) ticket_is_contended(l)
> +#define arch_spin_value_unlocked(l)ticket_value_unlocked(l)
> +
> +#endif /* __ASM_GENERIC_TICKET_LOCK_H */
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
y it with a separate patch.
>
> x86 uses an inline function here instead of the macro. This would also
> be my preference, but it may add complexity to avoid circular header
> dependencies.
>
> The rest of this patch looks good to me.
>
> Arnd
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
On Wed, Mar 31, 2021 at 10:32 PM wrote:
>
> From: Guo Ren
>
> - Using smp_cond_load_acquire in arch_spin_lock by Peter's
>advice.
> - Using __smp_acquire_fence in arch_spin_trylock
> - Using smp_store_release in arch_spin_unlock
>
> All above are just cod
On Wed, Mar 31, 2021 at 10:32 PM wrote:
>
> From: Guo Ren
>
> This patch introduces a ticket lock implementation for riscv, along the
> same lines as the implementation for arch/arm & arch/csky.
>
> We still use qspinlock as default.
>
> Signed-off-by: Guo Ren
&
On Mon, Apr 12, 2021 at 12:02 AM Guo Ren wrote:
>
> On Wed, Mar 31, 2021 at 10:32 PM wrote:
> >
> > From: Guo Ren
> >
> > This patch introduces a ticket lock implementation for riscv, along the
> > same lines as the implementation for arch/arm & arch
On Wed, Mar 31, 2021 at 10:32 PM wrote:
>
> From: Guo Ren
>
> This patch introduces a ticket lock implementation for riscv, along the
> same lines as the implementation for arch/arm & arch/csky.
>
> We still use qspinlock as default.
>
> Signed-off-by: Guo Ren
&
Hi Paul,
Thx for the explanation, here is my comment.
On Wed, Mar 31, 2021 at 1:33 PM Paul Campbell wrote:
>
> On Wednesday, 31 March 2021 5:18:56 PM NZDT Guo Ren wrote:
> > > > [1]
> > > > https://github.com/c-sky/csky-linux/commit/e837aad231485427717
On Wed, Mar 31, 2021 at 12:08 AM Peter Zijlstra wrote:
>
> On Tue, Mar 30, 2021 at 11:13:55AM +0800, Guo Ren wrote:
> > On Mon, Mar 29, 2021 at 8:50 PM Peter Zijlstra wrote:
> > >
> > > On Mon, Mar 29, 2021 at 08:01:41PM +0800, Guo Ren wrote:
> > > >
On Tue, Mar 30, 2021 at 10:09 PM Waiman Long wrote:
>
> On 3/29/21 11:13 PM, Guo Ren wrote:
> > On Mon, Mar 29, 2021 at 8:50 PM Peter Zijlstra wrote:
> >> On Mon, Mar 29, 2021 at 08:01:41PM +0800, Guo Ren wrote:
> >>> u32 a = 0x55aa66bb;
>
dma-mapping.c b/arch/csky/mm/dma-mapping.c
> index c3a775a..8244702 100644
> --- a/arch/csky/mm/dma-mapping.c
> +++ b/arch/csky/mm/dma-mapping.c
> @@ -9,7 +9,6 @@
> #include
> #include
> #include
> -#include
> #include
>
> static inline void cache_op(phys_addr_t paddr, size_t size,
> --
> 1.8.3.1
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
gt; wrapper around those (or alternatively we can decide to have them
> only deal with fixed-32-bit and long/pointer sized atomics).
I think these emulation codes are suitable for some architectures but not riscv.
We shouldn't export xchg16/cmpxchg16(emulated by lr.w/sc.w) in riscv,
We sh
;d change
> > - #elif defined __mips__
> > + #elif defined(__mips__ || __csky__)
> >
> > and then change the rest of the text to add csky when appropriate.
> > Am I correct?
>
> AFAICT, you are correct. I think the reason that csky is missing is
> that the architecture was added after this manual pages was added.
>
> Thanks,
>
> Michael
>
>
> --
> Michael Kerrisk
> Linux man-pages maintainer; http://www.kernel.org/doc/man-pages/
> Linux/UNIX System Programming Training: http://man7.org/training/
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
\
> > case 4: \
> > __asm__ __volatile__ ( \
> > " amoswap.w %0, %2, %1\n" \
>
> I'm pretty sure there's a handfull of implementations like this out
> there... if only we could share.
Michael has sent qspinlock before, ref to Link below. He reused mips' code.
Link:
https://lore.kernel.org/linux-riscv/20190211043829.30096-1-michaeljcl...@mac.com/
Which short xchg implementation do you prefer (Mine or his)?
>
> Anyway, this too should be an independent patch.
Ok, I'll separate it into two patches,
1. implement short xchg
2. qspinlock enabled based on Michael's patch
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
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