o DRAM by opening default window to 4GB
space with specific attribute.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree/bindings/dma/mv-xor.txt | 3 +-
drivers/dma/mv_xor.c | 56 +---
2 files changed, 51 i
Armada 3700 SoC uses the mv_xor driver but don't select anymore the
PLAT_ORION symbol. This commit extends the dependency of the mv_xor
driver to the more modern SoCs only compatible with ARCH_MVEBU, which
allows using it with the Armada 3700 SoC.
Signed-off-by: Gregory CLEMENT
---
driver
From: Marcin Wojtas
Armada 3700 SoC comprise one dual-channel XOR engine and this
patch adds its according representation.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 13 +
1 file changed, 13 insertions(+)
diff
Fix two warnings which appear when building for 64 bits target.
Signed-off-by: Gregory CLEMENT
---
drivers/dma/mv_xor.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index 3922a5d56806..a6ec82776cbc 100644
--- a/drivers/dma
Armada 3700 SoC uses the mv_xor driver but don't select anymore the
PLAT_ORION symbol. This commit extends the dependency of the mv_xor
driver to the more modern SoCs only compatible with ARCH_MVEBU, which
allows using it with the Armada 3700 SoC.
Signed-off-by: Gregory CLEMENT
---
driver
o DRAM by opening default window to 4GB
space with specific attribute.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/dma/mv-xor.txt | 5 ++-
drivers/dma/mv_xor.c | 56
in commit log of patch 3
- Reformatting to 1 compatible string per line in
Documentation/devicetree/bindings/dma/mv-xor.txt
- Added Acked-by from Rob in patch 3
Gregory CLEMENT (3):
dmaengine: mv_xor: make the code 64 bits compliant
dmaengine: mv_xor: use SoC type instead of directly
, and then depending to the type the engine setup will be
selected.
Signed-off-by: Gregory CLEMENT
---
drivers/dma/mv_xor.c | 40
drivers/dma/mv_xor.h | 1 +
2 files changed, 29 insertions(+), 12 deletions(-)
diff --git a/drivers/dma/mv_xor.c b/drivers
Hi Jason,
On mar., avril 12 2016, Jason Cooper wrote:
> On Tue, Apr 12, 2016 at 08:19:17PM +0200, Gregory CLEMENT wrote:
>> Armada 3700 SoC uses the mv_xor driver but don't select anymore the
>> PLAT_ORION symbol. This commit extends the dependency of the mv_xor
>>
.
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 150 ++
1 file changed, 115 insertions(+), 35 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 20a2363f9e40..c38326b848f9 100644
This patch add the support for the RSS related ethtool
function. Currently it only use one entry in the indirection table which
allows associating an mveneta interface to a given CPU.
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 114
static.
I really would like to have some feedback before going further and
then going in the wring direction.
Thanks,
Gregory CLEMENT (2):
net: mvneta: Associate RX queues with each CPU
net: mvneta: Add naive RSS support
drivers/net/ethernet/marvell/mvneta.c | 264 +++
ruct mvneta_pcpu_port *pcpu_port =
>> + per_cpu_ptr(pp->ports, cpu);
>> +
>> + napi_enable(&pcpu_port->napi);
>> + }
>> +
>
> rxq_def changed, but txq vs CPU mapping remained as in the beginning -
> is it intent
On the Armada 375/38x/39x SoCs, in standby mode the SoCs stay powered
and it is possible to wake-up from any interrupt sources. This patch
adds flag to the GIC irqchip driver to let linux know this.
Signed-off-by: Gregory CLEMENT
---
arch/arm/mach-mvebu/board-v7.c | 7 +++
1 file changed, 7
sing rtcwake or by setting the serial line as a
wake-up source through the sysfs interface.
Thanks,
Gregory
Gregory CLEMENT (4):
ARM: mvebu: Use __init for the PM initialization functions
ARM: mvebu: Add standby support
ARM: mvebu: Allow using the GIC for wakeup in standby mode
ARM: mv
370, 38x, 39x and XP SoCs. There are issues
with the Armada 375, and the support would be added (if possible) in a
future patch.
Signed-off-by: Gregory CLEMENT
---
arch/arm/mach-mvebu/common.h | 5 ++--
arch/arm/mach-mvebu/pm-board.c | 17 -
arch/arm/mach-mvebu/pm.c | 57
mvebu_pm_init and mvebu_armada_pm_init are only called during boot, so
flag them with __init and save some memory.
Signed-off-by: Gregory CLEMENT
---
arch/arm/mach-mvebu/pm-board.c | 2 +-
arch/arm/mach-mvebu/pm.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch
mode, the wake-up sources won't be taken into consideration.
Signed-off-by: Gregory CLEMENT
---
arch/arm/mach-mvebu/pm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-mvebu/pm.c b/arch/arm/mach-mvebu/pm.c
index 264073a777d8..4402dcfa7c56 100644
--- a/arch/arm/mach-mvebu
Since u-boot 2015_T1.0p6 there are new requency settings available.
Based on a patch from Nadav Haklai
Signed-off-by: Gregory CLEMENT
---
drivers/clk/mvebu/armada-38x.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/mvebu/armada-38x.c b/drivers/clk
Hi Andrew,
thanks for your prompt review
On 02/07/2015 22:04, Andrew Lunn wrote:
> On Thu, Jul 02, 2015 at 09:42:38PM +0200, Gregory CLEMENT wrote:
>> Since u-boot 2015_T1.0p6 there are new requency settings available.
>
> Hi Gregory
>
> Missing f in f_requency.
it must
order to activate this
feature.
This is still an RFC because there is still some stability issue to
fix with the current code.The solution has been found but still need
time to write it properly. As most of the code is already there your
feedback is very welcome.
Thanks,
Gregory
Gregory CLEMENT (5
be done at
pmsu level: this unit must not wait for the second CPU when the
frequency is modified.
Signed-off-by: Gregory CLEMENT
---
arch/arm/mach-mvebu/pmsu.c | 67 +-
1 file changed, 61 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-mvebu
In order to support dynamic frequency scaling:
- the cpuclk Device Tree node must be added
- the clock property of the CPUs must be filled including the
clock-latency property.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-380.dtsi | 3 +++
arch/arm/boot/dts/armada-385.dtsi
In preparation to support cpufreq for Armada 38x:
- rename the function to be more generic.
- move masking interrupt to the _dfs_request_local function in order
to be use by both SoCs.
- add stubs allowing registering the support for a new SoC
Signed-off-by: Gregory CLEMENT
---
arch/arm
The register definition were too verbose. Shorten them in order to
have something more readable and avoiding having most of the
instruction on two lines.
Signed-off-by: Gregory CLEMENT
---
arch/arm/mach-mvebu/pmsu.c | 102 +++--
1 file changed, 52
This patch first shortens the registers definition and also introduces
difference between Armada XP value and Armada 38x value.
Then it adds specific functions for Armada 38x in order to support cpu
freq on these SoCs.
Signed-off-by: Gregory CLEMENT
---
.../devicetree/bindings/clock/mvebu-cpu
Hi Thomas,
On 01/07/2015 17:54, Thomas Petazzoni wrote:
> Dear Gregory CLEMENT,
>
> On Tue, 30 Jun 2015 19:18:59 +0200, Gregory CLEMENT wrote:
>
>> static void __init mvebu_init_irq(void)
>> {
>> +if (of_machine_is_compatible("marvell,armada375")
Thanks,
Gregory
On 01/07/2015 18:04, Thomas Petazzoni wrote:
> Hello,
>
> On Tue, 30 Jun 2015 19:19:00 +0200, Gregory CLEMENT wrote:
>> On the Armada 370/XP/38x/39x SoCs when the suspend to ram feature is
>> supported, the SoC is shutdown and will be waken up by an externa
doesn't seem to be
the good default behavior. That's why I was looking for a way to let the
use configure it according to his needs.
Please correct me if I am wrong somewhere, because currently I don't
find a good solution for it.
Thanks,
Gregory
--
Gregory Clement, Free Elect
40 -> val=0x600
> load_level=0
> [ 14.916424] clk_pm_cpu_set_parent old=2E004840 -> val=0x600 load_level=1
> [ 14.923315] clk_pm_cpu_set_parent old=8880A8C0 -> val=0x600
> load_level=2
> [ 14.930572] clk_pm_cpu_set_parent old=8E80A8C0 -> val=0x600 load_level=3
Wolfram Sang writes:
> On Tue, Aug 13, 2019 at 09:09:13AM +0300, Denis Efremov wrote:
>> Update MAINTAINERS record to reflect the file move
>> from i2c-mv64xxx.txt to marvell,mv64xxx-i2c.yaml.
>>
>> Cc: Maxime Ripard
>> Cc: Gregory CLEMENT
>>
> Add cpu clock node on AP
>
> Signed-off-by: Gregory CLEMENT
Applied on mvebu/dt64
Gregory
> ---
> arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 4
> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 7 +++
> 2 files changed, 11 insertions(+)
>
&
ork on the ts219 board
Uwe Kleine-König (1):
ARM: dts: kirkwood: ts219: disable the SoC's RTC
arch/arm/boot/dts/kirkwood-ts219.dtsi | 8
1 file changed, 8 insertions(+)
--
Gregory Clement, Bootlin
Embedded L
- Add cpu clock node needed for CPU freq on Armada 7K/8K
- Enhance CP110 COMPHY support used by PCIe, USB3 and SATA
Gregory CLEMENT (1):
arm64: dts: marvell: Add cpu clock node on Armada 7K/8K
Marek Behún (1):
arm64
ars:
"BUG: sleeping function called from invalid context at
kernel/locking/mutex.c:909"
[1]: https://www.spinics.net/lists/alsa-devel/msg71286.html
Signed-off-by: Gregory CLEMENT
---
sound/soc/atmel/atmel_ssc_dai.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/sound/soc/atm
Hi Alex,
> On 18/09/2019 11:41:14+0200, Gregory CLEMENT wrote:
>> A potential bug was reported in the email "[BUG] atmel_ssc_dai: a
>> possible sleep-in-atomic bug in atmel_ssc_shutdown"[1]
>>
>> Indeed in the function atmel_ssc_shutdown() free_irq() was call
ars:
"BUG: sleeping function called from invalid context at
kernel/locking/mutex.c:909"
[1]: https://www.spinics.net/lists/alsa-devel/msg71286.html
Reviewed-by: Alexandre Belloni
Signed-off-by: Gregory CLEMENT
---
Changelog:
v1 -> v2:
- Removed the spinlock from the atmel_ssc_inf
compatible = "ricoh,rs5c372a";
> reg = <0x32>;
> };
>
> --
> 2.20.1
>
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infrad
compatible = "mmio-sram";
> reg = <0xe000 0x800>;
> clocks = <&gate_clk 15>;
> --
> 2.17.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
| 2 +-
> 4 files changed, 12 insertions(+), 2 deletions(-)
>
> --
> 2.23.0
>
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
ad;
> + };
> +};
> +
> +/* Exported on the micro USB connector J5 through an FTDI */
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_pins>;
> + status = "okay";
> +};
> +
> +/*
> + * Connector J17 and J18 expose a number of different features. Some pins are
> + * multiplexed. This is the case for instance for the following features:
> + * - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example
> of
> + * how to enable it. Beware that the signals are 1.8V TTL.
> + * - I2C
> + * - SPI
> + * - MMC
> + */
> +
> +/* J7 */
> +&usb3 {
> + status = "okay";
> +};
> +
> +/* J8 */
> +&usb2 {
> + status = "okay";
> +};
> +
> +&mdio {
> + switch0: switch0@1 {
> + compatible = "marvell,mv88e6085";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + dsa,member = <0 0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + label = "cpu";
> + ethernet = <ð0>;
> + phy-mode = "rgmii-id";
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + label = "wan";
> + phy-handle = <&switch0phy0>;
> + };
> +
> + port@2 {
> + reg = <2>;
> + label = "lan0";
> + phy-handle = <&switch0phy1>;
> + };
> +
> + port@3 {
> + reg = <3>;
> + label = "lan1";
> + phy-handle = <&switch0phy2>;
> + };
> +
> + };
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + switch0phy0: switch0phy0@11 {
> + reg = <0x11>;
> + };
> + switch0phy1: switch0phy1@12 {
> + reg = <0x12>;
> + };
> + switch0phy2: switch0phy2@13 {
> + reg = <0x13>;
> + };
> + };
> + };
> +};
> +
> +ð0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
> + phy-mode = "rgmii-id";
> + status = "okay";
> +
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> +};
> --
> 2.21.0
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
e been reversed,
>>
>> ESPRESSObin V7 with soldered eMMC.
>>
>> Since most of elements are the same, one common dtsi is created and
>> referenced in each dts of particular variant.
>>
>> Signed-off-by: Tomasz Maciej Nowak
>
>
> Applied on mvebu
;
>> Fixes: eb6c2eb6c7fb ("usb: host: xhci-plat: Prevent an abnormally
>>
>
> This is weird, in the patch I sent the tag ends there with ...")
Truncating the commit title was wrong and checkpatch complained about it
so I fixed on the fly, but unfortunately it was splitted i
is no more limitation for the number of
gpio CS we can use.
Fixes: 754ce4f29937 ("[PATCH] SPI: atmel_spi driver")
Cc: sta...@vger.kernel.org
Signed-off-by: Gregory CLEMENT
---
drivers/spi/spi-atmel.c | 44 ++---
1 file changed, 33 insertions(+), 11
AV32 support has been from the kernel a few release ago, but there was
still some specific macro for this architecture in this driver. Lets
remove it.
Signed-off-by: Gregory CLEMENT
---
drivers/spi/spi-atmel.c | 24
1 file changed, 24 deletions(-)
diff --git a/drivers
ession on this side.
But after going further in the details of the driver, this patch could
cause a regression for on the old controllers.
I also found other issues in this driver in the chip select
management. So I will send a new series fixing all of it.
Gregory
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
Hi Eric,
> Hi Gregory,
>
> On 7/11/19 4:31 PM, Gregory CLEMENT wrote:
>> The VFIO reset hook is called every time a platform device is passed
>> to a guest or removed from a guest.
>>
>> When the XHCI device is unbound from the host, the host driver
>> disa
Warn the upper layer when n_gms is ready to receive data
again. Without this the associated virtual tty remain blocked
indefinitely.
Fixes: 96fd7ce58ffb ("TTY: create drivers/tty and move the tty core files
there")
Signed-off-by: Gregory CLEMENT
---
drivers/tty/n_
an make it optional.
Fixes: 96fd7ce58ffb ("TTY: create drivers/tty and move the tty core files
there")
Signed-off-by: Gregory CLEMENT
---
drivers/tty/n_gsm.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/tty/n_gsm.c b/drivers/tty/n_gsm.
Warn the upper layer when n_gms is ready to receive data
again. Without this the associated virtual tty remain blocked
indefinitely.
Fixes: 96fd7ce58ffb ("TTY: create drivers/tty and move the tty core files
there")
Signed-off-by: Gregory CLEMENT
---
drivers/tty/n_
observed on the LE910 but should benefit
to all the modem. We observed that pretty quickly the transfer done
using the virtual tty were blocked. We found that it was due of a
wakeup to the real tty. Without this fix, the real tty wait for
indefinitely.
Gregory
Gregory CLEMENT (3):
tty: n_gsm
Use appropriate print helpers for debug messages.
Signed-off-by: Gregory CLEMENT
---
drivers/tty/n_gsm.c | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/drivers/tty/n_gsm.c b/drivers/tty/n_gsm.c
index d77ed82a4840..4965e39e0223 100644
--- a/drivers/tty
Since CSAAT functionality support has been added. Some comments become
wrong. Fix them to match the current driver behavior.
Signed-off-by: Gregory CLEMENT
---
drivers/spi/spi-atmel.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-atmel.c b
Since the conversion to GPIO descriptor, the GPIO used as chip select,
can be directly access from the spi_device struct. So there is no need
to keep the field npcs_pin.
Signed-off-by: Gregory CLEMENT
---
drivers/spi/spi-atmel.c | 17 ++---
1 file changed, 6 insertions(+), 11
limited to have only 4 CS managed, now it is possible to have
in the same time until 3 internal CS and no more limit for the CS
GPIO.
Signed-off-by: Gregory CLEMENT
---
drivers/spi/spi-atmel.c | 74 -
1 file changed, 66 insertions(+), 8 deletions(-)
diff --git
Thanks to the recent change in this driver, it is now possible to
prevent using the CS0 with GPIO during setup. It then allows to remove
the special handling of this case in the cs_activate() and
cs_deactivate() functions.
Signed-off-by: Gregory CLEMENT
---
drivers/spi/spi-atmel.c | 15
Instead of setting up the GPIO configuration for the whole controller,
do it at CS level. It will allow to mix internal CS and GPIO CS, which
is not possible with the current implementation.
Signed-off-by: Gregory CLEMENT
---
drivers/spi/spi-atmel.c | 32
1 file
possible to mix native and GPIO
CS as expected by the SPI binding.
In the end even managment of the specific use case for CS0 on
AT91RM9200 has been simplified.
Gregory
Gregory CLEMENT (7):
spi: atmel: Remove and fix erroneous comments
spi: atmel: Fix CS high support
spi: atmel: Configure
r
infernal CS.
This patch fixes the test to match the hardware capabilities.
Fixes: 4820303480a1 ("spi: atmel: add support for the internal chip-select of
the spi controller")
Cc:
Signed-off-by: Gregory CLEMENT
---
drivers/spi/spi-atmel.c | 6 ++
1 file changed, 2 insertions(+),
This driver is now only used through the device tree. Simplify code
by explicitly depend on device tree.
Signed-off-by: Gregory CLEMENT
---
drivers/spi/Kconfig | 1 +
drivers/spi/spi-atmel.c | 16 ++--
2 files changed, 3 insertions(+), 14 deletions(-)
diff --git a/drivers/spi
setup automatically.
With this patch the setting is done only for the CS that will use a
GPIO as CS
Fixes: f3186dd87669 ("spi: Optionally use GPIO descriptors for CS GPIOs")
Cc:
Signed-off-by: Gregory CLEMENT
---
drivers/spi/spi.c | 18 +-
1 file changed, 9 insert
e SPI framework
queue")
Signed-off-by: Mans Rullgard
Acked-by: Nicolas Ferre
Signed-off-by: Gregory CLEMENT
---
Hello,
This patch was first submitted 2 years[1] but was never applied while it
has received the acked-by from Nicolas, and I don't see any review
against it on the mailing li
pmac = kzalloc(sizeof(*pmac) + 6, GFP_KERNEL);
> if (!pmac)
> goto eth_fixup_no_mem;
> --
> 2.20.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
Hi Miquel,
On mar., janv. 08 2019, Miquel Raynal wrote:
> The error message should state that the driver failed to get the
> parent clock, not the opposite.
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> drivers/clk/mvebu/arm
ucture here will create a link between the 4 TBG
> clocks (registered by this driver) and:
> * their parent clock: XTAL,
> * their child clocks: several 'periph' clock.
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> driver
ucture here will create a link between the XTAL
> clock (this one) and the four TBG clocks that are derived from it.
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> drivers/clk/mvebu/armada-37xx-xtal.c | 3 ++-
> 1 file changed, 2 inser
d
> try something different (and if yes, what?).
>
> Signed-off-by: Marek Behún
> Cc: Rob Herring
> Cc: linux-kernel@vger.kernel.org
> Cc: Gregory CLEMENT
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: Andrew Lunn
> ---
> .../arm/marvell/armada-3720-turris-mox.txt
remains unchanged with
> this commit.
>
> Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
>
> We also delete the MODULE_LICENSE tag etc. since all that information
> is already contained at the top of the file in the comments.
>
> Cc: Kishon Vijay Abrah
Adopt the SPDX license identifier headers to ease license compliance
management.
Signed-off-by: Gregory CLEMENT
---
drivers/phy/marvell/phy-armada375-usb2.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/phy/marvell/phy-armada375-usb2.c
b/drivers/phy/marvell
.org/pipermail/linux-arm-kernel/2019-January/623885.html
>
> Thanks,
> Miquèl
>
>
> Changes since v2:
> =
> * Minor patches reordering.
> * Added pinctrl patches from Gregory Clement fixing the PCIe pins. His
> changes implied modifications in the DT/bindings patches adding
r the peripheral (e.g. UARTs, I2C, SPI).
>
> Signed-off-by: Alexandre Belloni
Tested-by: Gregory CLEMENT
Gregory
> ---
> arch/arm/boot/dts/lpc32xx.dtsi | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.
; num-lanes = <4>;
> num-viewport = <8>;
> reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
> + ranges = <0x8100 0x0 0xf901 0x0 0xf901 0x0 0x10000
> + 0x8200 0x0 0xc000 0x0 0xc000 0x0 0x2000>;
> status = "okay";
> };
>
> --
> 2.20.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
> On 5/17/19 10:08 PM, Gregory CLEMENT wrote:
>> Hi Heinrich Schuchardt,
>>
>>> Running a graphics adapter on the MACCHIATObin fails due to an
>>> insufficently sized memory window.
>> I think "insufficient" is enough or I miss something.
&
While there was a git repository used for the mvebu subsystem since many
years, it was not documented. let's add it.
Signed-off-by: Gregory CLEMENT
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9cc6767e1b12..c50a975dd5ab 100644
tml
> [2] https://spdx.org/licenses/MIT.html
>
> Signed-off-by: Alexandre Belloni
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> arch/arm/boot/dts/at91-vinco.dts | 39 +---
> 1 file changed, 1 insertion(+), 38 deletions(-)
>
> diff --git a/arc
Hi Rob,
On jeu., mars 28 2019, Rob Herring wrote:
> On Mon, Mar 25, 2019 at 01:47:58PM +0100, Gregory CLEMENT wrote:
>> Document the device tree binding for the cluster clock controllers found
>> in the Armada 7K/8K SoCs.
>>
>> Signed-off-by: Gregory CLEMENT
>&
tatic void __init i2c_quirk(void)
>
> of_update_property(np, new_compat);
> }
> - return;
> }
>
> static void __init mvebu_dt_init(void)
> --
> 2.1.4
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
> + mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID
> and r0, r0, #15
> add r1, r1, r0
> mov r0, #0x0
> --
> 2.21.0
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
interrupts-extended = <&gic GIC_SPI 64
> IRQ_TYPE_LEVEL_HIGH>,
> + <&gic GIC_SPI 9
> IRQ_TYPE_LEVEL_HIGH>;
> };
>
> cpurst: cpurst@20800 {
> --
> 2.21.0
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
issing of_node_put;
> acquired a node pointer with refcount incremented on line 88, but without a
> corresponding object release within this functio
>
> Signed-off-by: Wen Yang
> Cc: Jason Cooper
> Cc: Andrew Lunn
> Cc: Gregory Clement
> Cc: Sebastian Hesselbart
Hi Chris,
> On 20/02/19 4:14 AM, Gregory CLEMENT wrote:
>> Hi Chris,
>>
>> On lun., févr. 18 2019, Chris Packham
>> wrote:
>>
>>> Kirkwood has always had the ability to retrieve the local-mac-address
>>> from the hardware (usually
Document the device tree binding for the cluster clock controllers found
in the Armada 7K/8K SoCs.
Signed-off-by: Gregory CLEMENT
---
.../arm/marvell/ap806-system-controller.txt | 26 +++
1 file changed, 26 insertions(+)
diff --git
a/Documentation/devicetree/bindings/arm
ad of it for cluster member of the ap_cpu_clk struct
- Use clk_hw instead of clk
- Use regmap_read_poll_timeout
- Use for_each_of_cpu_node
- Remove unnecessary WARN_ON()
- Remove headers from armada_ap_cp_helper.h
- Few other minor cleanup
Gregory CLEMENT (6):
dt-bindings: ap806: add the cluste
This commit makes sure the driver for the Armada 7K/8K CPU clock is
enabled.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/Kconfig.platforms | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 70498a033cf5..b68b89e7bcb4 100644
Clock drivers for Armada AP and Armada CP use the same function to
generate unique clock name. A third drivers is coming with the same
need, so it's time to move this function in a common file.
Signed-off-by: Gregory CLEMENT
---
drivers/clk/mvebu/Kconfig | 5
driver
The CPU frequency is managed at the AP level for the Armada 7K/8K. The
CPU frequency is modified by cluster: the CPUs of the same cluster have
the same frequency.
This patch adds the clock driver that will be used by CPUFreq, it is
based on the work of Omri Itach .
Signed-off-by: Gregory CLEMENT
Add cpu clock node on AP
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 4
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 7 +++
2 files changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
b/arch
Actually, the clocks exposed for the cluster are not the CPU clocks, but
the PLL clock used as entry clock for the CPU clocks. The CPU clock will
be managed by a driver submitting in the following patches.
Signed-off-by: Gregory CLEMENT
---
drivers/clk/mvebu/ap806-system-controller.c | 4
Actually, the clocks exposed for the cluster are not the CPU clocks, but
the PLL clock used as entry clock for the CPU clocks. The CPU clock will
be managed by a driver submitting in the following patches.
Signed-off-by: Gregory CLEMENT
---
drivers/clk/mvebu/ap806-system-controller.c | 4
inor cleanup
Gregory CLEMENT (6):
dt-bindings: ap806: add the cluster clock node in the syscon file
clk: mvebu: add helper file for Armada AP and CP clocks
clk: mvebu: add CPU clock driver for Armada 7K/8K
clk: mvebu: ap806: Fix clock name for the cluster
arm64: marvell: enable the Arma
The CPU frequency is managed at the AP level for the Armada 7K/8K. The
CPU frequency is modified by cluster: the CPUs of the same cluster have
the same frequency.
This patch adds the clock driver that will be used by CPUFreq, it is
based on the work of Omri Itach .
Signed-off-by: Gregory CLEMENT
This commit makes sure the driver for the Armada 7K/8K CPU clock is
enabled.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/Kconfig.platforms | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 70498a033cf5..b68b89e7bcb4 100644
Add cpu clock node on AP
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 4
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 7 +++
2 files changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
b/arch
Document the device tree binding for the cluster clock controllers found
in the Armada 7K/8K SoCs.
Signed-off-by: Gregory CLEMENT
---
.../arm/marvell/ap806-system-controller.txt | 26 +++
1 file changed, 26 insertions(+)
diff --git
a/Documentation/devicetree/bindings/arm
Clock drivers for Armada AP and Armada CP use the same function to
generate unique clock name. A third drivers is coming with the same
need, so it's time to move this function in a common file.
Signed-off-by: Gregory CLEMENT
---
drivers/clk/mvebu/Kconfig | 5
driver
implementation uses the VFIO reset hook to enable the
XHCI clocks/phys on behalf of the guest.
Ported from Marvell LSP code originally written by Yehuda Yitschak
Signed-off-by: Gregory CLEMENT
---
drivers/vfio/platform/reset/Kconfig | 8 +++
drivers/vfio/platform/reset/Makefile
Add IOMMU node for Marvell AP806 based SoCs.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
L6030
allows this but needs to be aware of it and this configuration should
also be shared with the bootloader.
This is the purpose of this new property: ti,retain-on-reset
Signed-off-by: Gregory CLEMENT
---
.../devicetree/bindings/regulator/twl-regulator.txt| 7 +++
1 file chang
ure itself, I made
a separate patch for it.
The last patch adds the feature in the driver.
Gregory
Gregory CLEMENT (3):
dt-bindings: regulator: twl6030: Add retain-on-reset property
regulator: twl6030: use variable for device node
regulator: twl6030: workaround the VMMC reset behavior
..
he SD
card doesn't reach a undefined reset stage.
Actually this behavior is available for all the LDO regulator, so the
driver will also allow to use it with any of these regulator.
Signed-off-by: Gregory CLEMENT
---
drivers/regulator/twl6030-regulator.c | 15 ++-
1 file c
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