> Changelog:
> v1 -> v2
>
> - Add at least one line of commit log entry for those patches, which
> contained only commit title.
>
> Suggested by Andrew Lunn and Gregory Clement.
>
> - Drop patch "ARM: mvebu: enable E1000E in mvebu_v7_defconfig", since it
>
the last time."
>>
>
> If you use the ordering by address as main argument for the revert there
> will be nothing to argue about.
>
>> To be blunt, I think our best path forward is to just hold our noses
>> and let it stand as is. Some will fix their userspace to adapt,
>> others will carry a patch. It's more important at this point to be
>> consistent moving forward. It's better to hear "Yeah, it fucking
>> changed once." rather than "I don't know what to expect, it changes
>> every few releases."
>>
>> thx,
>>
>> Jason.
>>
>>
>> [1] CDO: OCD with the letters neatly arranged in alphabetical order.
>
> Thanks for sharing your thoughts
>
> Regards
> Ralph
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
rupt-cells = <1>;
> + interrupt-controller;
> + interrupts = ;
> + };
> +
> xor@40 {
> compatible = "marvell,armada-7k-xor",
> "marvell,xor-v2";
> reg = <0x40 0x1000>,
> --
> 2.7.4
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
marvell,function = "dev";
> + };
> +
> uart0_pins: uart-pins-0 {
> marvell,pins = "mpp0", "mpp1";
> marvell,function = "ua0";
> --
> 2.9.2.518.ged577c6.dirty
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Hi Stephen,
On mar., juin 20 2017, Stephen Boyd wrote:
> On 06/19, Gregory CLEMENT wrote:
>>
>> Hi Mike, Stephen,
>>
>> This time I turned the series in a pull request so I removed the
>> device tree binding part which will be in an other series for Rob
>
Hi,
On jeu., juin 01 2017, Gregory CLEMENT
wrote:
> The *-clock-output-names of the cp110-system-controller0 node are not
> used anymore, so remove them.
>
> Reviewed-by: Thomas Petazzoni
> Signed-off-by: Gregory CLEMENT
Applied on mvebu/dt64
Thanks,
Gregory
> ---
Hi,
On jeu., juin 01 2017, Gregory CLEMENT
wrote:
> The new binding for the system controller on cp110 moved the clock
> controller into a subnode. This preliminary step will allow to add gpio
> and pinctrl subnodes.
>
> Reviewed-by: Thomas Petazzoni
> Signed-off-b
Hi,
On lun., juin 12 2017, Gregory CLEMENT
wrote:
> Enable pinctrl support for CP and AP on the Armada 7K/8K SoCs.
>
> The CP master being different between Armada 7k and Armada 8k. This
> commit introduces the intermediates files armada-70x0.dtsi and
> armada-80x0.dtsi.
>
Hi,
On lun., juin 12 2017, Gregory CLEMENT
wrote:
> Enable gpio support for CP and AP on the Marvell Armada 7K/8K SoCs.
>
> The Armada 8K has two CP110 blocks, each having two GPIO controllers.
> However, in each CP110 block, one of the GPIO controller cannot be
> used: in t
IRQ_TYPE_EDGE_RISING
> | IRQ_TYPE_LEVEL_HIGH)>,
> - ,
> - ,
> - ,
> - ,
> -
Hi Thomas,
On mar., juin 20 2017, Thomas Petazzoni
wrote:
> Hello,
>
> On Tue, 20 Jun 2017 16:56:35 +0200, Gregory CLEMENT wrote:
>
>> > +#include
>>
>> With this line you created a dependency with the patch "irqchip:
>> irq-mvebu-icu: new dri
Hi Linus,
On ven., juin 16 2017, Linus Walleij wrote:
> On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
> wrote:
>
>> This commit makes sure the drivers for the Armada 7K/8K pin controllers
>> are enabled.
>>
>> Reviewed-by: Thomas Petazzoni
>> Signe
should take the first four patches, and Grégory takes the
> last two ones. But I'll let Grégory confirm.
Indeed it makes more sens to merge the patch 4 through the arm-soc
subsystem.
Thanks,
Gregory
>
> Once again, thanks a lot for your help on this series, it's in a much
> b
s = (IRQ_TYPE_EDGE_RISING
> | IRQ_TYPE_LEVEL_HIGH)>,
> - ,
> - ,
> - ,
> - ,
> -
> @@ -106,6 +106,8 @@ config ARCH_MVEBU
> select ARMADA_AP806_SYSCON
> select ARMADA_CP110_SYSCON
> select ARMADA_37XX_CLK
> + select MVEBU_GICP
> + select MVEBU_ICU
> select MVEBU_ODMI
> select MVEBU_PIC
> help
> --
> 2.9.4
>
Hi Marc,
On mer., juin 21 2017, Marc Zyngier wrote:
> On 21/06/17 16:42, Gregory CLEMENT wrote:
>> Hi Marc and Thomas,
>>
>> On mer., juin 21 2017, Thomas Petazzoni
>> wrote:
>>
>>> Hello,
>>>
>>> On Wed, 21 Jun 2017 16:14
and A counter when id==0.
>
> Tested on clearfog-pro (Marvell 88F6828)
>
> Signed-off-by: Richard Genoud
Looks good for me:
Reviewed-by: Gregory CLEMENT
I thinks this one should go to v4.12-rc as it is a fix.
As I modified the same part of the code in my series, I think I will
Hi again,
On mar., mai 30 2017, Gregory CLEMENT
wrote:
> Hi Richard,
>
> On mar., mai 30 2017, Richard Genoud wrote:
>
>> The blink counter A was always selected because 0 was forced in the
>> blink select counter register.
>> The variable 'set
nfusing.
Besides that I agree that mvpwm->chip.base must be initialized and here
again for adding mor context to this patch, we could add:
Fixes: 757642f9a584 ("gpio: mvebu: Add limited PWM support")
Gregory
>
> spin_lock_init(&mvpwm->lock);
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
are still in
my mvebu branch.
Thanks,
Gregory
>> * Update and merge documentation patch
>> * Update MAINTAINERS]
>> Signed-off-by: Ralph Sennhauser
>> Tested-by: Andrew Lunn
>> Acked-by: Thierry Reding
>> Acked-by: Rob Herring
>
> Patch applied.
>
> Yours,
> Linus Walleij
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Hi Ard,
On mar., oct. 31 2017, Ard Biesheuvel wrote:
> On 31 October 2017 at 12:47, Russell King - ARM Linux
> wrote:
>> On Mon, Oct 30, 2017 at 04:38:17PM +, Russell King - ARM Linux wrote:
>>> On Mon, Oct 30, 2017 at 05:24:34PM +0100, Gregory CLEMENT wrote:
-gicp: Add new driver for Marvell
> GICP")
> Signed-off-by: Antoine Tenart
You could add the "Cc: sta...@vger.kernel.org" flag so the previous
kernels can also benefit of this fix.
Besides this this patch looks obviously correct.
Reviewed-by: Gregory CLEMENT
Thanks,
by also
applying the value received as parameter.
Cc: sta...@vger.kernel.org
Fixes: 5715092a458c ("pinctrl: armada-37xx: Add gpio support")
Reported-by: Alexandre Belloni
Signed-off-by: Gregory CLEMENT
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 13 +++--
1 file c
From: Ken Ma
Current edge both type gpio irqs which need to swap polarity in each
interrupt are not supported, this patch adds edge both type gpio irq
support.
Signed-off-by: Ken Ma
Signed-off-by: Gregory CLEMENT
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 64
Hi Andrew,
On jeu., oct. 19 2017, Andrew Lunn wrote:
> On Thu, Oct 19, 2017 at 03:10:03PM +0200, Gregory CLEMENT wrote:
>> From: Ken Ma
>>
>> Current edge both type gpio irqs which need to swap polarity in each
>> interrupt are not supported, this patch a
nclude
> +# include
> +# define get_unaligned __get_unaligned_le
> +# define put_unaligned __put_unaligned_le
> +#elif defined(__BIG_ENDIAN)
> +# include
> +# include
> +# include
> +# define get_unaligned __get_unaligned_be
> +# define put_unaligned __put_unaligned_be
> +#else
> +# error need to define endianess
> +#endif
> +
> +#endif /* __ASM_ARM_UNALIGNED_H */
> --
> 2.9.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Hi Russell,
On ven., oct. 27 2017, Russell King - ARM Linux wrote:
> On Fri, Oct 27, 2017 at 05:19:55PM +0200, Gregory CLEMENT wrote:
>> Hi Arnd,
>>
>> On ven., oct. 20 2017, Arnd Bergmann wrote:
>>
>> > The asm-generic/unaligned.h header provides tw
Hi Ard,
On lun., oct. 30 2017, Ard Biesheuvel wrote:
> On 30 October 2017 at 13:48, Gregory CLEMENT
> wrote:
>> Hi Russell,
>>
>> On ven., oct. 27 2017, Russell King - ARM Linux
>> wrote:
>>
>>> On Fri, Oct 27, 2017 at 05:19:55PM +0200, Grego
Hi Ard,
On lun., oct. 30 2017, Ard Biesheuvel wrote:
> On 30 October 2017 at 15:05, Gregory CLEMENT
> wrote:
>> Hi Ard,
>>
>> On lun., oct. 30 2017, Ard Biesheuvel wrote:
>>
> ...
>>>
>>> Could you please share the output of &#x
Hi Ard,
On lun., oct. 30 2017, Ard Biesheuvel wrote:
> On 30 October 2017 at 15:09, Gregory CLEMENT
> wrote:
>> Hi Ard,
>>
>> On lun., oct. 30 2017, Ard Biesheuvel wrote:
>>
>>> On 30 October 2017 at 15:05, Gregory CLEMENT
>>> wrote:
&g
Hi Ard,
On lun., oct. 30 2017, Ard Biesheuvel wrote:
> On 30 October 2017 at 15:33, Gregory CLEMENT
> wrote:
>> Hi Ard,
>>
>> On lun., oct. 30 2017, Ard Biesheuvel wrote:
>>
>>> On 30 October 2017 at 15:09, Gregory CLEMENT
>>> wrote:
&g
Hi Russell King,
On lun., oct. 30 2017, Russell King - ARM Linux wrote:
> On Mon, Oct 30, 2017 at 02:48:02PM +0100, Gregory CLEMENT wrote:
>> Hi Russell,
>>
>> So I tested the branch fixes in your git tree.
>>
>> After doing a "make multi_v7_defc
Hi Russell,
On lun., oct. 30 2017, Russell King - ARM Linux wrote:
> On Mon, Oct 30, 2017 at 04:33:07PM +0100, Gregory CLEMENT wrote:
>> Humm no, actually it was with the wrong branch. If I have the patch
>> "ARM: verify size of zImage" then arch/arm/boot/com
Hi Russell King,
On lun., oct. 30 2017, Russell King - ARM Linux wrote:
> On Mon, Oct 30, 2017 at 05:01:44PM +0100, Gregory CLEMENT wrote:
>> Hi Russell King,
>>
>> On lun., oct. 30 2017, Russell King - ARM Linux
>> wrote:
>>
>> > On Mon,
t;
> Signed-off-by: Nadav Haklai
> Signed-off-by: Marcin Wojtas
> Cc: # v4.2
Seems OK.
Reviewed-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> drivers/mmc/host/sdhci-pxav3.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mmc/host/sdhci-pxav3.c b/driv
for high speed
> MMC and might cause timing violation.
>
> Signed-off-by: Nadav Haklai
> Cc: # v4.2
Seems OK too.
Reviewed-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> drivers/mmc/host/sdhci-pxav3.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/mmc
t | 5 +
> arch/arm/boot/dts/armada-388-gp.dts| 3 +-
> drivers/mmc/host/sdhci-pxav3.c | 101
> -
> drivers/mmc/host/sdhci.c | 14 ++-
> drivers/mmc/host/sdhci.h |
Hi Marcin,
On mar., oct. 06 2015, Marcin Wojtas wrote:
> In case of armada_38x_quirks error, all clocks should be cleaned-up, same
> as after mv_conf_mbus_windows failure.
>
> Signed-off-by: Marcin Wojtas
> Cc: # v4.2
Good catch.
Reviewed-by: Gregory CLEMENT
T
it cleaner to not rely on the device tree outise the probe
function. What about just testing pxa->mbus_win_regs ? As it is set only
if we need it, it should be a good test.
Thanks,
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, tr
at if we modify the dts, then the old board won't work with the
new kernel. So maybe creating a armada-388-gp-v1.5.dts could be the best
option.
What do you think of it?
Thanks,
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, c
Hi Felipe,
On ven., août 21 2015, Gregory CLEMENT
wrote:
>> According to the OTG specification after a timeout of
>> OTG_TIME_A_WAIT_VRISE (the maximum value is 100ms) the driver must
>> move from the state a_wait_vrise to the state a_wait_bcon. However,
>> the dsps
ock, 32, timer_clk);
> + sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk,
> + NULL);
>
> clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
> "armada_370_xp_clocksource",
For the time-arm
};
> +
> + ethernet@7 {
> + status = "okay";
> + phy = <&phy0>;
> + phy-mode = "rgmii-id";
> + };
> +
&g
gt;> +phy1: ethernet-phy@1 { /* Marvell 88E1318 */
>> + reg = <1>;
>> +};
>> +};
>> +
>> +ethernet@7 {
>> +
rtc@10300 {
> + status = "disabled";
> + };
> +
> /* Two rear eSATA ports */
> sata@a {
> nr-ports = <2>;
> --
> 2.5.3
>
>
e_IRQ to use
__handle_domain_irq") on this branch.
Thanks,
Gregory
>
> Ben.
>
> --
> Ben Hutchings
> Who are all these weirdos? - David Bowie, reading IRC for the first time
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, c
/ {
> model = "Marvell Armada 385 Access Point Development Board";
> - compatible = "marvell,a385-db-ap", "marvell,armada385",
> "marvell,armada38x";
> + compatible = "marvell,a385-db-ap", "marvell,armada385&quo
The second macb is present on all sama5d4 soc. Let's add a node
reflecting it in the device tree.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/at91-vinco.dts | 5 +
arch/arm/boot/dts/sama5d4.dtsi | 30 ++
2 files changed, 31 insertions(+), 4 dele
Hi all,
please ignore this patch, some garbage slipt in it.
I will send a proper one in a few minute
Sorry for the noise
Gregory
On ven., oct. 16 2015, Gregory CLEMENT
wrote:
> The second macb is present on all sama5d4 soc. Let's add a node
> reflecting it in the device tree.
The second macb is present on all the sama5d4 SoCs. Let's add a node
reflecting it in the device tree.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/sama5d4.dtsi | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arc
+ * 'dat3-cd;'
> + * 'cd-inverted;'
> + */
> + broken-cd;
> wp-inverted;
> bus-width = <8&g
data = irq_get_irq_data(virq);
> - if (!irqd_irq_disabled(data))
> - armada_370_xp_irq_unmask(data);
> + /*
> + * Re-enable on the current CPU,
> + * armada_xp_mpic_secondary_init() will take
> +
t; which registers are relative to "per_cpu_int_base".
>
> Signed-off-by: Thomas Petazzoni
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> drivers/irqchip/irq-armada-370-xp.c | 21 ++---
> 1 file changed, 10 insertions(+), 11 deletions(-)
>
>
r implements on top of that.
It was really needed!
>
> Signed-off-by: Thomas Petazzoni
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> drivers/irqchip/irq-armada-370-xp.c | 80
> +
> 1 file changed, 80 insertions(+)
>
> diff --
ff-by: Thomas Petazzoni
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> drivers/irqchip/irq-armada-370-xp.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/irqchip/irq-armada-370-xp.c
> b/drivers/irqchip/irq-armada-370-xp.c
> i
as I got an interrupt when I connected it).
Note that I applied this patch instead of the "usb: musb: dsps: handle
the otg_state_a_wait_vrise_timeout case", is what you had in mind ?
Gregory
>
> [1] http://www.ti.com/lit/ug/spruh73l/spruh73l.pdf
>
> --
> balbi
--
Gr
s per GPIO chip
>> gpio: mvebu: Allow to use non-default PWM counter
>>
>> drivers/gpio/gpio-mvebu.c | 111
>> ++++++
>> 1 file changed, 92 insertions(+), 19 deletions(-)
>>
>> --
>> 2.7.4
>>
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
be very grateful for a nod from the PWM maintainer that
> this is OK with him.
>
> Yours,
> Linus Walleij
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
d() function once.
This improvement should go to net-next. Besides this patch looks nice:
Reviewed-by: Gregory CLEMENT
Thanks,
Gregory
>
> Signed-off-by: Jisheng Zhang
> ---
> drivers/net/ethernet/marvell/mvneta.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff
Hi Alexandre,
On mer., août 29 2018, Alexandre Belloni wrote:
> Unfortunately, the Jaguar2 CPU_SYSTEM_CTRL register set has a different
> layout than the Ocelot one. Handle that while keeping most of the code
> common.
>
> Signed-off-by: Alexandre Belloni
Reviewed-by:
sfp = <&sfp>;
> + phy-mode = "sgmii";
> + managed = "in-band-status";
> + status = "disabled";
> + };
> + };
> + };
> +
> + switch2@2 {
> + compatible = "marvell,mv88e6085";
> + reg = <0x2 0>;
> + dsa,member = <0 2>;
> + interrupt-parent = <&gpiosb>;
> + interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
> + status = "disabled";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + switch2phy1_topaz: switch2phy1@11 {
> + reg = <0x11>;
> + };
> +
> + switch2phy2_topaz: switch2phy2@12 {
> + reg = <0x12>;
> + };
> +
> + switch2phy3_topaz: switch2phy3@13 {
> + reg = <0x13>;
> + };
> +
> + switch2phy4_topaz: switch2phy4@14 {
> + reg = <0x14>;
> + };
> + };
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <0x1>;
> + label = "lan17";
> + phy-handle = <&switch2phy1_topaz>;
> + };
> +
> + port@2 {
> + reg = <0x2>;
> + label = "lan18";
> + phy-handle = <&switch2phy2_topaz>;
> + };
> +
> + port@3 {
> + reg = <0x3>;
> + label = "lan19";
> + phy-handle = <&switch2phy3_topaz>;
> + };
> +
> + port@4 {
> + reg = <0x4>;
> + label = "lan20";
> + phy-handle = <&switch2phy4_topaz>;
> + };
> +
> + port@5 {
> + reg = <0x5>;
> + label = "dsa";
> + phy-mode = "2500base-x";
> + link = <&switch1port10 &switch0port10>;
> + };
> + };
> + };
> +
> +};
> +
> +&sdhci0 {
> + wp-inverted;
> + bus-width = <4>;
> + cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
> + vqmmc-supply = <&vsdc_reg>;
> + marvell,pad-type = "sd";
> + status = "okay";
> +};
> +
> +&sdhci1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdio0_pins &sdio_sb_pins>;
> + non-removable;
> + bus-width = <4>;
> + marvell,pad-type = "sd";
> + vqmmc-supply = <&vsdio_reg>;
> + status = "okay";
> +};
> +
> +&spi0 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
> + assigned-clocks = <&nb_periph_clk 7>;
> + assigned-clock-parents = <&tbg 1>;
> + assigned-clock-rates = <2000>;
> +
> + spi-flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <200>;
> +
> + partition@0 {
> + label = "u-boot";
> + reg = <0x0 0x3f>;
> + };
> +
> + partition@3f {
> + label = "u-boot-env";
> + reg = <0x18 0x1>;
> + };
> +
> + partition@40 {
> + label = "Rescue system";
> + reg = <0x19 0x67>;
> + };
> + };
> +
> + moxtet@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "cznic,moxtet";
> + reg = <1>;
> + devrst-gpio = <&gpiosb 2 GPIO_ACTIVE_LOW>;
> + spi-max-frequency = <100>;
> + spi-cpol;
> + spi-cpha;
> +
> + moxtet_sfp: moxtet-sfp@0 {
> + compatible = "cznic,moxtet-gpio";
> + gpio-controller;
> + #gpio-cells = <2>;
> + reg = <0>;
> + moxtet,id = <1>;
> + moxtet,input-mask = <0x7>;
> + moxtet,output-mask = <0x3>;
> + status = "disabled";
> + };
> + };
> +};
> +
> +&usb3 {
> + status = "okay";
> + usb-phy = <&usb3_phy>;
> +};
> --
> 2.16.4
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
Fixes: 9818a7a4fd10 ("clk: mvebu: armada-37xx-periph: prepare cpu clk to
be used with DVFS")
Signed-off-by: Gregory CLEMENT
---
drivers/clk/mvebu/armada-37xx-periph.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c
b/drivers/clk/mvebu/a
00 {
> - compatible = "inside-secure,safexcel-eip97";
> + compatible = "inside-secure,safexcel-eip97ies";
> reg = <0x9 0x2>;
> interrupts =
; - compatible = "inside-secure,safexcel-eip197";
> + compatible = "inside-secure,safexcel-eip197b";
> reg = <0x80 0x20>;
> interrupts = ,
>
ype]
> line 527: warning: cast to restricted __le32
>
> This is solved by removing endian-converson functions, since the
> converted values are going through readl/writel anyway, which take care
> of the conversion.
>
These changes look good for me:
Reviewed-by: Gregory CLEMEN
by: Maxime Chevallier
As for the previous patch:
Reviewed-by: Gregory CLEMENT
Thanks,
Gregory> ---
> drivers/spi/spi-armada-3700.c | 13 ++---
> 1 file changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/spi/spi-armada-3700.c b/drivers/spi/spi-armada-3700.c
Hi Chris,
On mer., janv. 10 2018, Chris Packham
wrote:
> On 10/01/18 21:31, Gregory CLEMENT wrote:
>> Hi Chris,
>>
>> On mar., janv. 09 2018, Chris Packham
>> wrote:
>>
>>> The Armada-38x uses an SDRAM controller that is compatible with th
rch/arm/boot/dts/armada-xp-98dx3236.dtsi | 2 +-
> arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 5 +
> arch/arm/boot/dts/armada-xp.dtsi | 2 +-
> 4 files changed, 12 insertions(+), 2 deletions(-)
>
> --
> 2.15.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
.
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree/bindings/spi/spi-orion.txt | 9 +
drivers/spi/spi-orion.c | 14 ++
2 files changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/spi-orion.txt
b/Documentation
Hi Chris,
On jeu., janv. 11 2018, Chris Packham
wrote:
> On 11/01/18 22:14, Gregory CLEMENT wrote:
>> Hi Chris,
>>
>> On jeu., janv. 11 2018, Chris Packham
>> wrote:
>>
>>> I've split this off from my earlier series[1] this is just th
'orion_spi_probe()' is called.
>
> Add a new label to clean what needs to be cleaned and rename another
> label to improve the names used.
>
> Fixes: 92ae112e477a ("spi: orion: Fix clock resource by adding an optional
> bus clock")
> Signed-off-
tree change
even if the driver is not merged yet. But I would like to have an
acked-by on this new property by either a device tree maintainer or at
least the EDAC maintainer, of course having both acked-by would be
perfect ! :)
Thanks,
Gregory
> +};
> +
> &devbus_bootcs {
>
t; +
> L2: cache-controller@8000 {
> compatible = "arm,pl310-cache";
> reg = <0x8000 0x1000>;
> --
> 2.15.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Hi Alexandre,
On jeu., mars 22 2018, Alexandre Belloni wrote:
> Bits have to be cleared in DEVCPU_GCB:GPIO:GPIO_OE for input and set for
> output. ocelot_gpio_set_direction() got it wrong and this went unnoticed
> when the driver was reworked.
>
> Reported-by: Gregory Clement
1}, {0, 1}, {0, 1},
> {1, 2}, {0, 1}, {0, 1}, {0, 1},
> - {1, 2}, {0, 1}, {0, 1}, {0, 1},
> + {1, 2}, {0, 1}, {0, 1}, {7, 15},
> {0, 1}, {0, 1}, {0, 1}, {0, 1},
> {0, 1}, {0, 1}, {0, 1}, {0, 1},
> {0, 1}, {0, 1}, {0, 1}, {0, 1},
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
Hi,
On jeu., mars 08 2018, Gregory CLEMENT wrote:
> Hi Richard,
>
> On jeu., mars 08 2018, Richard Genoud wrote:
>
>> Clearfog boards can come with a CPU clocked at 1600MHz (commercial)
>> or 1333MHz (industrial).
>>
>> They have also some dip-switc
Hi Richard,
On mar., mars 13 2018, Richard Genoud wrote:
> On 08/03/2018 14:23, Gregory CLEMENT wrote:
>> Hi,
>>
>> On jeu., mars 08 2018, Gregory CLEMENT wrote:
>>
>>> Hi Richard,
>>>
>>> On jeu., mars 08 2018, Richard Genou
Hi,
On mer., févr. 28 2018, Gregory CLEMENT wrote:
> Thanks to new documentation, we have a better view of the clock tree.
> There were few mistakes in the first version of this driver, the main one
> being the parental link between the clocks. Actually the tree is more
> flat th
rupt-names = "tx-cpu0", "tx-cpu1",
> "tx-cpu2",
> - "tx-cpu3", "rx-shared", "link";
> + interrupt-names = "hif0", "hif1", "hif2",
> + "hif3", "hif4", "link";
> port-id = <2>;
> gop-port-id = <3>;
> status = "disabled";
> --
> 2.17.1
>
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
"hif3", "hif4", "link";
> + "hif3", "hif4", "hif5", "hif6", "hif7",
> + "hif8", "link";
> port-id = <2>;
> gop-port-id = <3>;
> status = "disabled";
> --
> 2.17.1
>
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
Hi Stephen,
On mer., oct. 17 2018, Stephen Boyd wrote:
> Quoting Gregory CLEMENT (2018-09-22 11:17:07)
>> Actually, the clocks exposed for the cluster are not the CPU clocks, but
>> the PLL clock used as entry clock for the CPU clocks. The CPU clock will
>> be managed b
Hi Stephen,
On ven., oct. 12 2018, Stephen Boyd wrote:
> +Rob
>
> Quoting Gregory CLEMENT (2018-09-22 11:17:09)
>> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
>> b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
>> index 4a65e4e830aa..27c840e91abe 1006
Hi Stephen,
On ven., nov. 16 2018, Gregory CLEMENT wrote:
>>> +static int ap_cpu_clock_probe(struct platform_device *pdev)
>>> +{
>>> + int ret, nclusters = 0, cluster_index = 0;
>>> + struct device *dev = &pdev->dev;
>>>
Hi Stephen,
On mer., oct. 17 2018, Stephen Boyd wrote:
> Quoting Gregory CLEMENT (2018-09-22 11:17:06)
>> diff --git a/drivers/clk/mvebu/ap-cpu-clk.c b/drivers/clk/mvebu/ap-cpu-clk.c
>> new file mode 100644
>> index ..1b498cfe9191
>> --- /dev/null
>&g
Clock drivers for Armada AP and Armada CP use the same function to
generate unique clock name. A third drivers is coming with the same
need, so it's time to move this function in a common file.
Signed-off-by: Gregory CLEMENT
---
drivers/clk/mvebu/Kconfig | 5
driver
The CPU frequency is managed at the AP level for the Armada 7K/8K. The
CPU frequency is modified by cluster: the CPUs of the same cluster have
the same frequency.
This patch adds the clock driver that will be used by CPUFreq, it is
based on the work of Omri Itach .
Signed-off-by: Gregory CLEMENT
This commit makes sure the driver for the Armada 7K/8K CPU clock is
enabled.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/Kconfig.platforms | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 51bc479334a4..8a05870b1ba8 100644
Actually, the clocks exposed for the cluster are not the CPU clocks, but
the PLL clock used as entry clock for the CPU clocks. The CPU clock will
be managed by a driver submitting in the following patches.
Signed-off-by: Gregory CLEMENT
---
drivers/clk/mvebu/ap806-system-controller.c | 4
Add cpu clock node on AP
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 4
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 6 ++
2 files changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
b/arch
ead of it for cluster member of the ap_cpu_clk struct
- Use clk_hw instead of clk
- Use regmap_read_poll_timeout
- Use for_each_of_cpu_node
- Remove unnecessary WARN_ON()
- Remove headers from armada_ap_cp_helper.h
- Few other minor cleanup
Gregory CLEMENT (5):
clk: mvebu: add helper file
mmc-hs400-1_8v;
> + marvell,xenon-emmc;
> + marvell,xenon-tun-count = <9>;
> + marvell,pad-type = "fixed-1-8v";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc_pins>;
> status = "okay";
> };
>
> --
> 2.17.1
>
>
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
Hi,
On mar., juin 19 2018, Gregory CLEMENT wrote:
> Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz
> respectively) to L0 frequency (1.2 Ghz) requires a significant amount
> of time to let VDD stabilize to the appropriate voltage. This amount of
> time is large en
Hi Stephen,
On ven., juil. 06 2018, Stephen Boyd wrote:
> Quoting Gregory CLEMENT (2018-06-29 07:44:02)
>> Hi,
>>
>> On mar., juin 19 2018, Gregory CLEMENT wrote:
>>
>> > Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz
>>
};
> + helios_i2c1_pins: i2c1-pins {
> + marvell,pins = "mpp26", "mpp27";
> + marvell,function = "i2c1";
> + };
> + helios_sdhci_cd_pins: helios-sdhci-cd-pins {
> + marvell,pins = "mpp20";
> + marvell,function = "gpio";
> + };
> + helios_sdhci_pins: helios-sdhci-pins {
> + marvell,pins = "mpp21", "mpp28",
> +"mpp37", "mpp38",
> +"mpp39", "mpp40";
> + marvell,function = "sd0";
> + };
> + helios_led_pins: helios-led-pins {
> + marvell,pins = "mpp24", "mpp25",
> +"mpp49", "mpp50",
> +"mpp52", "mpp53",
> +"mpp54";
> + marvell,function = "gpio";
> + };
> + helios_fan_pins: helios-fan-pins {
> + marvell,pins = "mpp41", "mpp43",
> +"mpp48", "mpp55";
> + marvell,function = "gpio";
> + };
> + microsom_spi1_cs_pins: spi1-cs-pins {
> + marvell,pins = "mpp59";
> + marvell,function = "spi1";
> + };
> + };
> + };
> + };
> +};
> --
> 2.17.1
>
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
_start;
> + u32 code_len = mvebu_boot_wa_end - mvebu_boot_wa_start;
>
> mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
> mvebu_mbus_add_window_by_id(crypto_eng_target, crypto_eng_attribute,
> --
> 2.17.1
>
>
> _
Hi Ethan,
On mer., juin 27 2018, Ethan Tuttle wrote:
> Hi Gregory.
>
> On Tue, Jun 26, 2018 at 11:20 PM, Gregory CLEMENT
> wrote:
>> Hi Ethan,
>>
>> On mar., juin 19 2018, Ethan Tuttle wrote:
>>
>>> With CONFIG_FORTIFY_SOURCE, memcpy uses the d
the nand
> interface so use "nand" for the function name.
>
> Signed-off-by: Chris Packham
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/
;
> +
> + nand_rb: nand-rb {
> + marvell,pins = "mpp19";
> + marvell,function = "nand";
> + };
> +
> spi0_pins: spi0-pins {
> marvell,pins = "mpp0", "mpp1",
> "mpp2
,
this one is fine for 4.19*;
Thanks,
Gregory
Gregory CLEMENT (2):
clk: mvebu: armada-37xx-periph: Fix switching CPU rate from 300Mhz to
1.2GHz
clk: mvebu: armada-37xx-periph: switch to SPDX license identifier
drivers/clk/mvebu/armada-37xx-periph.c | 43 +++---
1 file
ned-off-by: Gregory CLEMENT
---
drivers/clk/mvebu/armada-37xx-periph.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c
b/drivers/clk/mvebu/armada-37xx-periph.c
index 6860bd5a37c5..44e4e27eddad 100644
--- a/drivers/clk/mvebu/a
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