I'll queue
>> it up for -rc1/2.
>
> OK, I'll prepare the patch. I thought that Gregory was going to create
> a patch for this.
If you want I still can take care of it.
>
> Br,
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded
From: Lior Amsalem
In order to be able to use more than 4GB address-cells and size-cells
have to be set to 2
Signed-off-by: Gregory CLEMENT
Signed-off-by: Lior Amsalem
---
arch/arm/boot/dts/skeleton64.dtsi | 13 +
1 file changed, 13 insertions(+)
create mode 100644 arch/arm
bad indentation.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-370-db.dts | 108 +-
arch/arm/boot/dts/armada-370-mirabox.dts | 78
arch/arm/boot/dts/armada-370-rd.dts |2 +
arch/arm/boot/dts/armada-370-xp.dtsi
device tree format,
armada-370 include the 32 bit skeleton and all the armada 370 based
dts can remain the same.
This was heavily based on the work of Lior Amsalem.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-370-xp.dtsi |4 ++--
arch/arm/boot/dts/armada-370.dtsi
: Gregory CLEMENT
---
arch/arm/mach-mvebu/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 440b13e..db1bbc8 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -13,6 +13,7 @@ config ARCH_MVEBU
From: Lior Amsalem
pj4b cpus are LPAE capable so enable them on LPAE compilations
Signed-off-by: Lior Amsalem
Tested-by: Franklin
Signed-off-by: Gregory CLEMENT
---
arch/arm/mm/proc-v7.S |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mm/proc-v7.S b/arch
This conversion will allow to keep 32 bits addresses for the internal
registers whereas the memory of the system will be 64 bits.
Later it will also ease the move of the mvebu-mbus driver to the
device tree support.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-370-db.dts
From: Thomas Petazzoni
reorganize the .dts and .dtsi files so that all devices are under the
soc { } node (currently some devices such as the interrupt controller,
the L2 cache and a few others are outside).
Signed-off-by: Thomas Petazzoni
---
arch/arm/boot/dts/armada-370-xp.dtsi | 26 ++
f code movement since it's indenting
by one more tab all the devices. So it was a good opportunity to fix
all the bad indentation.
* New patch from Thomas "fix cpus section indentation" to finalize the
fixing of the bad indentation
* For DMA transfer, DMA_ZONE was selected inste
From: Lior Amsalem
In order to be able to support the LPAE, the internal registers
virtual base must be aligned to 2MB. In LPAE section size is 2MB, in
earlyprintk we map the internal registers and it must be section
aligned.
Signed-off-by: Lior Amsalem
Signed-off-by: Gregory CLEMENT
From: Thomas Petazzoni
Align the cpu node indentation with the rest of the file
[gc]: added a commit description
Signed-off-by: Thomas Petazzoni
---
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 28
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 28
arch/arm/boot
+ of_fixed_factor_clkdiv_setup);
> +#endif
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 7f197d7..d4937cf 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -184,6 +184,7 @@ struct clk *clk_reg
The OpenBlocks A6 board has one software-controlled button on the
front side, labeled "INIT", so we add minimal support for this button
in the kernel.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 13 +
1 file changed, 13 insertion
On 05/02/2013 09:43 PM, Gregory CLEMENT wrote:
> The OpenBlocks A6 board has one software-controlled button on the
> front side, labeled "INIT", so we add minimal support for this button
> in the kernel.
>
Oh, I found that Thomas have already submitted the same patch but I
On 05/02/2013 10:02 PM, Andrew Lunn wrote:
> On Thu, May 02, 2013 at 09:48:50PM +0200, Sebastian Hesselbarth wrote:
>> On 05/02/2013 09:35 PM, Jason Gunthorpe wrote:
>>> I have kirkwood HW but I haven't had time to make newer kernels run on
>>> it, otherwise I'd test it too :(
>>
>> I also have kir
ter all, the
>> generic fixed rate clock also has a device tree binding and I'd guess
>> we're not the only ones statically deriving one clock from another in
>> our SOCs.
>>
>> Greetings,
>> Christian
>>
>> On Wed, Apr 10, 2013 at 05:56:2
Hi Jason,
On 04/11/2013 08:08 PM, Jason Cooper wrote:
> On Tue, Apr 09, 2013 at 12:52:12AM +0200, Gregory CLEMENT wrote:
>> From: Lior Amsalem
>>
>> pj4b cpus are LPAE capable so enable them on LPAE compilations
>>
>> Signed-off-by: Lior Amsalem
>> Tested-
Hi Jason,
On 04/11/2013 08:12 PM, Jason Cooper wrote:
> On Tue, Apr 09, 2013 at 12:52:13AM +0200, Gregory CLEMENT wrote:
>> From: Lior Amsalem
>>
>> In order to be able to use more than 4GB address-cells and size-cells
>> have to be set to 2
>>
>> Signed-of
On 04/12/2013 08:54 AM, Christian Ruppert wrote:
> On Thu, Apr 11, 2013 at 06:26:07PM +0200, Gregory CLEMENT wrote:
>> On 04/11/2013 11:19 AM, Christian Ruppert wrote:
>>> Hi Gregory,
>>>
>>> Since there doesn't seem to be anyone opposing this feature I jus
On 04/12/2013 08:54 AM, Christian Ruppert wrote:
> On Thu, Apr 11, 2013 at 06:26:07PM +0200, Gregory CLEMENT wrote:
>> On 04/11/2013 11:19 AM, Christian Ruppert wrote:
>>> Hi Gregory,
>>>
>>> Since there doesn't seem to be anyone opposing this feature I jus
On 04/12/2013 11:12 AM, Christian Ruppert wrote:
> On Fri, Apr 12, 2013 at 11:04:51AM +0200, Gregory CLEMENT wrote:
>> On 04/12/2013 08:54 AM, Christian Ruppert wrote:
>>> On Thu, Apr 11, 2013 at 06:26:07PM +0200, Gregory CLEMENT wrote:
>>>> On 04/11/2013 11:
Add support for DT "fixed-factor-clock" binding to the common fixed
factor clock support.
Signed-off-by: Gregory CLEMENT
---
.../bindings/clock/fixed-factor-clock.txt | 24 +
drivers/clk/clk-fixed-factor.c | 36
include
.
- Adding CLK_OF_DECLARE
- Using IS_ERR to test the clk value
Thanks,
Gregory CLEMENT (1):
clk: add device tree fixed-factor-clock binding support
.../bindings/clock/fixed-factor-clock.txt | 24 +
drivers/clk/clk-fixed-factor.c | 36
n I also add your tested-by flag?
Thanks,
>
> Greetings,
> Christian
>
> On Fri, Apr 12, 2013 at 11:58:28AM +0200, Gregory CLEMENT wrote:
>> Add support for DT "fixed-factor-clock" binding to the common fixed
>> factor clock support.
>>
>> S
Add support for DT "fixed-factor-clock" binding to the common fixed
factor clock support.
Signed-off-by: Gregory CLEMENT
Tested-by: Christian Ruppert
---
.../bindings/clock/fixed-factor-clock.txt | 24 +
drivers/clk/clk-fixed-factor.c
IS_ERR to test the clk value
Thanks,
Gregory CLEMENT (1):
clk: add device tree fixed-factor-clock binding support
.../bindings/clock/fixed-factor-clock.txt | 24 +
drivers/clk/clk-fixed-factor.c | 36
include/linux/clk-prov
From: Thomas Petazzoni
reorganize the .dts and .dtsi files so that all devices are under the
soc { } node (currently some devices such as the interrupt controller,
the L2 cache and a few others are outside).
Signed-off-by: Thomas Petazzoni
---
arch/arm/boot/dts/armada-370-xp.dtsi | 26 ++
Hi Jason,
I have just rebased the commits that you haven't applied yet. They are
rebased on mvebu/dt. I check that all the dtb can be built.
Thanks,
Gregory CLEMENT (3):
ARM: dts: mvebu: Convert all the mvebu files to use the range
property
ARM: dts: mvebu: introduce internal-regs
From: Thomas Petazzoni
Align the cpu node indentation with the rest of the file
[gc]: added a commit description
Signed-off-by: Thomas Petazzoni
---
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 32 +-
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 32 +-
arch/arm/
device tree format,
armada-370 include the 32 bit skeleton and all the armada 370 based
dts can remain the same.
This was heavily based on the work of Lior Amsalem.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-370-xp.dtsi |4 ++--
arch/arm/boot/dts/armada-370.dtsi
This conversion will allow to keep 32 bits addresses for the internal
registers whereas the memory of the system will be 64 bits.
Later it will also ease the move of the mvebu-mbus driver to the
device tree support.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-370-db.dts
On 04/15/2013 05:47 PM, Jason Cooper wrote:
> On Fri, Apr 12, 2013 at 04:29:05PM +0200, Gregory CLEMENT wrote:
>> Hi Jason,
>>
>> I have just rebased the commits that you haven't applied yet. They are
>> rebased on mvebu/dt. I check that all the dtb can be bu
give more details, but I believe we are also building
> daily linux-next and Linus master for the mvebu_defconfig.
Indeed every day we build linux-next for the mvebu_defconfig and for
multi_v7_defconfig (as mvebu is part of it). You can see the status here:
http://jenkins.free-electrons.com/j
ts all,
> or a selection of the supported Marvell EBU SoCs.
I agree with Thomas
>
> Thomas
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
--
To unsubscribe from this
The Armada 370 and Armada XP SoCs don't use the TWD timers, so don't
select it by default if CONFIG_LOCAL_TIMERS is selected
Signed-off-by: Gregory CLEMENT
---
arch/arm/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kco
Now that the time-armada-370-xp support local timers, updated the
device tree to take it into account.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-370-xp.dtsi |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi
b/arch
MPIC allows the use of private interrupt for each CPUs. The 28th first
interrupts are per-cpu. This patch adds support to use them.
Signed-off-by: Gregory CLEMENT
---
arch/arm/mach-mvebu/irq-armada-370-xp.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git
branch of Jason.
This patch set is based on 3.8-rc4 and is obviously 3.9 material. The
git branch called local_timer is available at:
https://github.com/MISL-EBU-System-SW/mainline-public.git.
Thanks,
Gregory CLEMENT (6):
arm: mvebu: Add support for local interrupt
clocksource: time-armada-37
On the SOCs Armada 370 and Armada XP, each CPU comes with two private
timers. This patch use the timer 0 of each CPU as local timer for the
clockevent if CONFIG_LOCAL_TIMER is selected. In the other case, use
only the private Timer 0 of CPU 0.
Signed-off-by: Gregory CLEMENT
---
drivers
On 01/08/2013 09:58 AM, Gregory CLEMENT wrote:
> On 01/08/2013 09:32 AM, Maxime Ripard wrote:
>> Hi Gregory,
>
> Hi Maxime,
>
> thanks for testing
>>
>> On 07/01/2013 23:51, Gregory CLEMENT wrote:
>>> -static int pca953x_write_reg(struct pca953x_chi
Thomas is currently in on vacations, so I apply this patch and the
first of the series, I built, compiled and tested it on an Aramda XP DB
board. Everything is OK for me.
So for sure you can have my
Tested-by: Gregory CLEMENT
and as the code looks good, so for what it's worth, you can
Now that pca953x driver can handle GPIO expanders with more than 32
bits this patch adds the support for the pca9505 which cam with 40
GPIOs.
Signed-off-by: Gregory CLEMENT
---
drivers/gpio/gpio-pca953x.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpio/gpio-pca953x.c b
The Globalscale Mirabox platform can be connected to the JTAG/GPIO box
through the Multi-IO port. The GPIO box use the NXP PCA9505 I/O port
expansion IC to provide 40-bit parallel input/output GPIOs. This patch
enable the use of this expander on the Mirabox.
Signed-off-by: Gregory CLEMENT
Acked
ue in the IRQ part which appeared once I have
enable CONFIG_GPIO_PCA953X_IRQ!
V2->V3:
- Rebased on v3.8-rc4
- Fix the interrupt handler and not try to call an handler if there is
no irq pending on a gpio bank
Gregory CLEMENT (3):
gpio: pca953x: make the register access by GPIO bank
gp
variables. This fits exactly the way the
registers are represented in the hardware.
It also adds helpers to access to a single register of a bank instead
of reading or writing all the banks for a given register.
Signed-off-by: Gregory CLEMENT
Tested-by: Maxime Ripard
---
drivers/gpio/gpio
the same way it
was used for the core clocks
Regards,
Gregory CLEMENT (3):
clk: mvebu: add armada-370-xp specific clocks
clk: armada-370-xp: add support for clock framework
clocksource: time-armada-370-xp converted to clk framework
.../devicetree/bindings/clock/mvebu-core-
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-370-db.dts |4
arch/arm/boot/dts/armada-370-xp.dtsi |1 +
drivers/clocksource/time-armada-370-xp.c | 11 ++-
3 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/armada-370
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-370.dtsi | 12 +
arch/arm/boot/dts/armada-xp.dtsi| 48 +++
arch/arm/mach-mvebu/Kconfig |5
arch/arm/mach-mvebu/armada-370-xp.c |8 +-
arch/arm/mach-mvebu
forward. For a new
SoC, only 3 binding have to be added:
- one to provide the tclk frequency
- one to provde the pclk frequency
- and one to provide the ratio between the pclk and the children
clocks
Signed-off-by: Gregory CLEMENT
---
.../devicetree/bindings/clock/mvebu-core-clock.txt | 40
Expose the DMA operations functions. Until now only the dma_ops
structs in a whole or some dma operation were exposed. This patch
exposes all the dma coherents operations. They can be reused when an
architecture or a driver need to create its own set of dma_operation.
Signed-off-by: Gregory
ency block, in other case transaction is driven
directly to DRAM.
Signed-off-by: Gregory CLEMENT
Reviewed-by: Yehuda Yitschak
Acked-by: Thomas Petazzoni
---
arch/arm/plat-orion/addr-map.c |4
arch/arm/plat-orion/include/plat/addr-map.h |1 +
2 files changed, 5 insertion
eneric name mvebu_hwcc
- removed the non SMP case during init
- spelling and wording issues
- updating the binding documentation for coherency fabric
Gregory CLEMENT (3):
arm: dma mapping: Export dma ops functions
arm: plat-orion: Add coherency attribute when setup mbus target
arm: mvebu: Add ha
p_cfg struct filled during the early initialization of
the platform.
Signed-off-by: Gregory CLEMENT
Reviewed-by: Yehuda Yitschak
---
.../devicetree/bindings/arm/coherency-fabric.txt |9 ++-
arch/arm/boot/dts/armada-370-xp.dtsi |3 +-
arch/arm/mach-mvebu/addr-
chitecture
- already exposed arm DMA related functions
- the arm_dma_set_mask which was not exposed yet.
Signed-off-by: Gregory CLEMENT
---
arch/arm/include/asm/dma-mapping.h |2 ++
arch/arm/mm/dma-mapping.c |4 +---
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git
p_cfg struct filled during the early initialization of
the platform.
Signed-off-by: Gregory CLEMENT
Reviewed-by: Yehuda Yitschak
---
.../devicetree/bindings/arm/coherency-fabric.txt |9 ++-
arch/arm/boot/dts/armada-370-xp.dtsi |3 +-
arch/arm/mach-mvebu/addr-
ency block, in other case transaction is driven
directly to DRAM.
Signed-off-by: Gregory CLEMENT
Reviewed-by: Yehuda Yitschak
Acked-by: Thomas Petazzoni
---
arch/arm/plat-orion/addr-map.c |4
arch/arm/plat-orion/include/plat/addr-map.h |1 +
2 files changed, 5 insertion
e dma ops functions
- Renamed the function for a more generic name mvebu_hwcc
- removed the non SMP case during init
- spelling and wording issues
- updating the binding documentation for coherency fabric
Gregory CLEMENT (3):
arm: dma mapping: Export a dma ops function arm_dma_set_mask
arm: plat-o
Dear Cong Ding,
On 01/14/2013 06:18 PM, Cong Ding wrote:
> the variable cpuclk and clk_name should be properly freed.
>
Thanks for reporting this memory leak and for your patch but I think
we could do even better, see below:
> Signed-off-by: Cong Ding
> ---
> drivers/clk/mvebu/clk-cpu.c |
}
>> clk_data.clk_num = MAX_CPU;
>> @@ -167,6 +171,7 @@ void __init of_cpu_clk_setup(struct device_node *node)
>> return;
>> bail_out:
>> kfree(clks);
>> +clks_out:
as cpuclk is allocated with all its member set to 0, and kfree(0) is a valid
call.
We can add
On 01/15/2013 07:26 PM, Cong Ding wrote:
> On Tue, Jan 15, 2013 at 05:33:57PM +0100, Gregory CLEMENT wrote:
>> On 01/15/2013 04:37 PM, Jason Cooper wrote:
>>> Mike,
>>>
>>> On Tue, Jan 15, 2013 at 03:23:08PM +, Cong Ding wrote:
>>>> From 75c730
On 01/15/2013 07:44 PM, Cong Ding wrote:
> the variable cpuclk and clk_name should be properly freed when error happens.
Dear Cong Ding,
Thanks for you efforts!
I am happy with this patch and I tested it on the Armada XP DB board, so
you can now add my:
Acked-by: Gregory CLEMENT
Mike,
co
have a conflict here. Currently my patch set is
based on v3.8-rc2, but I am willing to rebase onto gpio-for-next once
the GPIO block will be merged into it.
I also expected some tested-by as I was only able to test the pca9505
and I didn't test the IRQ part.
Thanks!
Gregory CLEMENT (3):
variables. This fits exactly the way the
registers are represented in the hardware.
It also adds helpers to access to a single register of a bank instead
of reading or writing all the banks for a given register.
Signed-off-by: Gregory CLEMENT
---
drivers/gpio/gpio-pca953x.c | 233
The Globalscale Mirabox platform can be connected to the JTAG/GPIO box
through the Multi-IO port. The GPIO box use the NXP PCA9505 I/O port
expansion IC to provide 40-bit parallel input/output GPIOs. This patch
enable the use of this expander on the Mirabox.
Signed-off-by: Gregory CLEMENT
Now that pca953x driver can handle GPIO expanders with more than 32
bits this patch adds the support for the pca9505 which cam with 40
GPIOs.
Signed-off-by: Gregory CLEMENT
---
drivers/gpio/gpio-pca953x.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpio/gpio-pca953x.c b
On 01/06/2013 06:34 PM, Gregory CLEMENT wrote:
> Hello,
>
> This patch set adds the support for the i2c gpio expander pca9505 used
> on the JTAG/GPIO box which can be connected to the Mirabox.
>
> To be able to use the pca9505 I had to do several changes in the
> driver.
variables. This fits exactly the way the
registers are represented in the hardware.
It also adds helpers to access to a single register of a bank instead
of reading or writing all the banks for a given register.
Signed-off-by: Gregory CLEMENT
---
drivers/gpio/gpio-pca953x.c | 281
The Globalscale Mirabox platform can be connected to the JTAG/GPIO box
through the Multi-IO port. The GPIO box use the NXP PCA9505 I/O port
expansion IC to provide 40-bit parallel input/output GPIOs. This patch
enable the use of this expander on the Mirabox.
Signed-off-by: Gregory CLEMENT
Now that pca953x driver can handle GPIO expanders with more than 32
bits this patch adds the support for the pca9505 which cam with 40
GPIOs.
Signed-off-by: Gregory CLEMENT
---
drivers/gpio/gpio-pca953x.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpio/gpio-pca953x.c b
e way to calculate the shift used to apply to register to
access a given bank.
- Fix all the pending issue in the IRQ part which appeared once I have
enable CONFIG_GPIO_PCA953X_IRQ!
Gregory CLEMENT (3):
gpio: pca953x: make the register access by GPIO bank
gpio: pca953x: add support for pca95
On 01/08/2013 09:32 AM, Maxime Ripard wrote:
> Hi Gregory,
Hi Maxime,
thanks for testing
>
> On 07/01/2013 23:51, Gregory CLEMENT wrote:
>> -static int pca953x_write_reg(struct pca953x_chip *chip, int reg, u32 val)
>> +static int pca953x_read_single(struct pca953x_chip *ch
On 01/10/2013 12:15 PM, Linus Walleij wrote:
> On Sun, Jan 6, 2013 at 6:34 PM, Gregory CLEMENT
> wrote:
>
>> Now that pca953x driver can handle GPIO expanders with more than 32
>> bits this patch adds the support for the pca9505 which cam with 40
>> GPIOs.
>>
clocks = <&cpm_syscon0 1 21>;
> status = "disabled";
> };
>
> --
> 1.8.3.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
>
> Fixes: c749b8d9de32 ("arm64: dts: marvell: add description for the ...")
> Signed-off-by: Marcin Wojtas
Acked-by: Gregory CLEMENT
Could you take this patch for 4.9? I didn't realized at first view it
was for 4.9, I though I could put it the PR for fixes for 4.8.
I can do a new P
From: Jamie Lentin
Referring to the u-boot sources for the Netgear WNR854T, add support
for the mv88f5181.
[gregory.clem...@free-electrons.com: fix commit title]
Signed-off-by: Jamie Lentin
Reviewed-by: Andrew Lunn
Acked-by: Rob Herring
Signed-off-by: Gregory CLEMENT
---
Hi Stephen and
Hi Stephen,
On mar., sept. 20 2016, Stephen Boyd wrote:
> On 09/20, Gregory CLEMENT wrote:
>> From: Jamie Lentin
>>
>> Referring to the u-boot sources for the Netgear WNR854T, add support
>> for the mv88f5181.
>>
>> [gregory.clem...@free-electrons.
Hi Grzegorz,
On jeu., juil. 21 2016, Grzegorz Jaszczyk wrote:
> Signed-off-by: Grzegorz Jaszczyk
As pointed by Andrew a commit log entry would be nice. Except this:
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> arch/arm/configs/mvebu_v7_defconfig | 1 +
> 1 fil
,6 +142,7 @@ CONFIG_UDF_FS=m
> CONFIG_MSDOS_FS=y
> CONFIG_VFAT_FS=y
> CONFIG_TMPFS=y
> +CONFIG_UBIFS_FS=y
> CONFIG_NFS_FS=y
> CONFIG_ROOT_NFS=y
> CONFIG_NLS_CODEPAGE_437=y
> --
> 1.8.3.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Hi Grzegorz,
On jeu., juil. 21 2016, Grzegorz Jaszczyk wrote:
> Signed-off-by: Grzegorz Jaszczyk
Here agina, as pointed by Andrew a commit log entry would be
nice. Except this:
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> arch/arm/boot/dts/armada-385-db-ap.dts | 4
Hi Grzegorz,
On jeu., juil. 21 2016, Grzegorz Jaszczyk wrote:
> Signed-off-by: Grzegorz Jaszczyk
It looks good:
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> arch/arm/boot/dts/armada-385-db-ap.dts | 26 +++---
> 1 file changed, 23 insertions(+),
Hi,
On mer., juil. 27 2016, Gregory CLEMENT
wrote:
> Hi Grzegorz,
>
> On jeu., juil. 21 2016, Grzegorz Jaszczyk wrote:
>
>> Signed-off-by: Grzegorz Jaszczyk
>
>
> Here agina, as pointed by Andrew a commit log entry would be
> nice. Except this:
>
>
Hi,
On mer., juil. 27 2016, Gregory CLEMENT
wrote:
> Hi Grzegorz,
>
> On jeu., juil. 21 2016, Grzegorz Jaszczyk wrote:
>
>> Signed-off-by: Grzegorz Jaszczyk
> It looks good:
>
> Acked-by: Gregory CLEMENT
And here again the title prefix should be change to:
&
d Device Tree files for Armada 39x SoC and
> board")
Change the title prefix to "ARM: dts: mvebu:". Alos usually we use
armada-390 instead of a390 to match the file name.
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> arch/arm/boot/dts/armada-390.dtsi | 3 +++
> 1 f
se the SDR50 and DDR50 modes.
>
> This commit updates the Device Tree description of the Armada
> 39x SDHCI controller in other to take advantage of this
> functionality.
>
> Signed-off-by: Grzegorz Jaszczyk
Change the prefix title to "ARM: dts: mvebu: armada-39x". With t
egorz Jaszczyk
> Reviewed-by: Lior Amsalem
Rename prefix to "ARM: dts: mvebu: armada-39x:" then
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> arch/arm/boot/dts/armada-39x.dtsi | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm/
+ };
> +
> pmsu@22000 {
> compatible = "marvell,armada-390-pmsu",
>"marvell,armada-380-pmsu";
> --
> 1.8.3.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Hi Grzegorz,
On jeu., juil. 21 2016, Grzegorz Jaszczyk wrote:
Add a commit log here and change the prefix to "ARM: dts: mvebu:
armada-39x:"
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> Signed-off-by: Grzegorz Jaszczyk
> ---
> arch/arm/boot/dts/armada-39x.dtsi |
Hi Grzegorz,
On jeu., juil. 21 2016, Grzegorz Jaszczyk wrote:
Add a commit log here and change the prefix to "ARM: dts: mvebu:
armada-39x:"
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> Signed-off-by: Grzegorz Jaszczyk
> Reviewed-by: Lior Amsalem
> ---
> ar
Hi Grzegorz,
On jeu., juil. 21 2016, Grzegorz Jaszczyk wrote:
> The whole Armada 39x SoC family of processors has GPIO's which all can be
> supported with existing driver.
>
Change the prefix to "ARM: dts: mvebu: armada-39x:"
Acked-by: Gregory CLEMENT
Thanks,
Hi Grzegorz,
On jeu., juil. 21 2016, Grzegorz Jaszczyk wrote:
> The whole Armada 39x SoC family of processors has one USB2.0 and one
> USB3.0 which all can be supported with existing drivers.
>
Change the prefix to "ARM: dts: mvebu: armada-39x:"
Acked-by: Gregory CLEMENT
Hi Grzegorz,
On jeu., juil. 21 2016, Grzegorz Jaszczyk wrote:
> Despite that FS states that rtc is present only in A395 and A398 and not in
> A390, the rtc is working with A390.
>
Change the prefix to "ARM: dts: mvebu: armada-39x:"
Acked-by: Gregory CLEMENT
Thanks,
Gr
amilies are actually the same die fused
> differently, or really different dies.
So do you want that we keep both "marvell,armada398" and
"marvell,armada395" or do you xant we use only "marvell,armada398" ?
Thanks,
Gregory
>
> Thomas
> --
> Thoma
to "ARM: dts: mvebu: armada-398:"
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> arch/arm/boot/dts/armada-398.dtsi | 10 +-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/armada-398.dtsi
> b/arch/arm/boot/dts/armada-
Hi Grzegorz,
On jeu., juil. 21 2016, Grzegorz Jaszczyk wrote:
Change the prefix to "ARM: dts: mvebu: armada-398-db:"
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> Signed-off-by: Grzegorz Jaszczyk
> ---
> arch/arm/boot/dts/armada-398-db.dts | 8
> 1 file
status = "okay";
> +
And the same for the following PCIe ports.
> + pcie@1,0 {
> + status = "okay";
> + };
> +
> + pcie@2,0 {
> + status = "okay";
> + };
> +
> + pcie@3,0 {
> + status = "okay";
> + };
> + };
> + };
> +};
Then you can add my
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> --
> 1.8.3.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
CIe units are accessible through
> + * mini PCIe slot on the board.
> + */
and here for each slot
> + pcie@2,0 {
> + /* Port 1, Lane 0 */
> + status = "okay";
> + };
> +
> + pcie@4,0 {
> + /* Port 3, Lane 0 */
> + status = "okay";
> + };
> + };
> + };
> +};
then you can add my:
Acked-by: Gregory CLEMENT
Thanks,
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
unsigned long irq);
>
> void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
> unsigned long mapbase,
> - unsigned long irq,
> - unsigned long irq_err);
> + unsigned long irq);
>
> void __init orion_ge00_switch_init(struct dsa_platform_data *d,
> int irq);
> --
> 2.9.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
unsigned long irq)
> {
> orion_sata.dev.platform_data = sata_data;
> - fill_resources(&orion_sata, orion_sata_resources,
> + fill_resources_irq(&orion_sata, orion_sata_resources,
> mapbase, 0x5000 - 1, irq);
>
> platform_device_register(&orion_sata);
> @@ -846,7 +852,7 @@ void __init orion_crypto_init(unsigned long mapbase,
> unsigned long sram_size,
> unsigned long irq)
> {
> - fill_resources(&orion_crypto, orion_crypto_resources,
> + fill_resources_irq(&orion_crypto, orion_crypto_resources,
> mapbase, 0x, irq);
> orion_crypto.num_resources = 3;
> orion_crypto_resources[2].start = srambase;
> --
> 2.9.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
= {
> {
> .modalias = "m25p80",
> .platform_data = &rd88f6183ap_ge_spi_slave_data,
> - .irq= NO_IRQ,
> .max_speed_hz = 2000,
> .bus_num= 0,
> .chip_sel
switch_resources[0].end = irq;
> - orion_switch_device.num_resources = 1;
> - }
> -
> d->netdev = &orion_ge00.dev;
> for (i = 0; i < d->nr_chips; i++)
> d->chip[i].host_dev = &orion_ge_mvmdio.dev;
> - orion_switch_device
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