[PATCH 0/8] AMD64 EDAC fixes for v5.2

2019-05-31 Thread Ghannam, Yazen
From: Yazen Ghannam Hi Boris, This set contains a few fixes for some changes merged in v5.2. There are also a couple of fixes for older issues. In addition, there are a couple of patches to add support for Asymmetric Dual-Rank DIMMs. Thanks, Yazen Yazen Ghannam (8): EDAC/amd64: Fix number of

[PATCH 1/8] EDAC/amd64: Fix number of DIMMs and Chip Select bases/masks on Family17h

2019-05-31 Thread Ghannam, Yazen
From: Yazen Ghannam ...because AMD Family 17h systems support 2 DIMMs, 4 CS bases, and 2 CS masks per channel. Fixes: 07ed82ef93d6 ("EDAC, amd64: Add Fam17h debug output") Signed-off-by: Yazen Ghannam --- drivers/edac/amd64_edac.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff

[PATCH 4/8] EDAC/amd64: Initialize DIMM info for systems with more than two channels

2019-05-31 Thread Ghannam, Yazen
From: Yazen Ghannam Currently, the DIMM info for AMD Family 17h systems is initialized in init_csrows(). This function is shared with legacy systems, and it has a limit of two channel support. This prevents initialization of the DIMM info for a number of ranks, so there will be missing ranks in

[PATCH 5/8] EDAC/amd64: Find Chip Select memory size using Address Mask

2019-05-31 Thread Ghannam, Yazen
From: Yazen Ghannam Chip Select memory size reporting on AMD Family 17h was recently fixed in order to account for interleaving. However, the current method is not robust. The Chip Select Address Mask can be used to find the memory size. There are a few cases. 1) For single-rank, use the addres

[PATCH 7/8] EDAC/amd64: Cache secondary Chip Select registers

2019-05-31 Thread Ghannam, Yazen
From: Yazen Ghannam AMD Family 17h systems have a set of secondary Chip Select Base Addresses and Address Masks. These do not represent unique Chip Selects, rather they are used in conjunction with the primary Chip Select registers in certain use cases. Cache these secondary Chip Select register

[PATCH 2/8] EDAC/amd64: Support more than two controllers for chip selects handling

2019-05-31 Thread Ghannam, Yazen
From: Yazen Ghannam The struct chip_select array that's used for saving chip select bases and masks is fixed at length of two. There should be one struct chip_select for each controller, so this array should be increased to support systems that may have more than two controllers. Increase the si

[PATCH 8/8] EDAC/amd64: Support Asymmetric Dual-Rank DIMMs

2019-05-31 Thread Ghannam, Yazen
From: Yazen Ghannam Future AMD systems will support "Asymmetric" Dual-Rank DIMMs. These are DIMMs were the ranks are of different sizes. The even rank will use the Primary Even Chip Select registers and the odd rank will use the Secondary Odd Chip Select registers. Recognize if a Secondary Odd

[PATCH 6/8] EDAC/amd64: Decode syndrome before translating address

2019-05-31 Thread Ghannam, Yazen
From: Yazen Ghannam AMD Family 17h systems currently require address translation in order to report the system address of a DRAM ECC error. This is currently done before decoding the syndrome information. The syndrome information does not depend on the address translation, so the proper EDAC csro

[PATCH 3/8] EDAC/amd64: Recognize DRAM device type with EDAC_CTL_CAP

2019-05-31 Thread Ghannam, Yazen
From: Yazen Ghannam AMD Family 17h systems support x4 and x16 DRAM devices. However, the device type is not checked when setting EDAC_CTL_CAP. Set the appropriate EDAC_CTL_CAP flag based on the device type. Fixes: 2d09d8f301f5 ("EDAC, amd64: Determine EDAC MC capabilities on Fam17h") Signed-off

[PATCH v2 4/6] x86/MCE: Make number of MCA banks per_cpu

2019-04-11 Thread Ghannam, Yazen
From: Yazen Ghannam The number of MCA banks is provided per logical CPU. Historically, this number has been the same across all CPUs, but this is not an architectural guarantee. Future AMD systems may have MCA bank counts that vary between logical CPUs in a system. This issue was partially addre

[PATCH v2 5/6] x86/MCE: Save MCA control bits that get set in hardware

2019-04-11 Thread Ghannam, Yazen
From: Yazen Ghannam The OS is expected to write all bits in MCA_CTL. However, only implemented bits get set in the hardware. Read back MCA_CTL so that the value in the hardware is saved and reported through sysfs. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20190408141205.

[PATCH v2 6/6] x86/MCE: Treat MCE bank as initialized if control bits set in hardware

2019-04-11 Thread Ghannam, Yazen
From: Yazen Ghannam The OS is expected to write all bits to MCA_CTL for each bank. However, some banks may be unused in which case the registers for such banks are Read-as-Zero/Writes-Ignored. Also, the OS may not write any control bits because of quirks, etc. A bank can be considered uninitiali

[PATCH v2 2/6] x86/MCE: Handle MCA controls in a per_cpu way

2019-04-11 Thread Ghannam, Yazen
From: Yazen Ghannam Current AMD systems have unique MCA banks per logical CPU even though the type of the banks may all align to the same bank number. Each CPU will have control of a set of MCA banks in the hardware and these are not shared with other CPUs. For example, bank 0 may be the Load-St

[PATCH v2 1/6] x86/MCE: Make struct mce_banks[] static

2019-04-11 Thread Ghannam, Yazen
From: Yazen Ghannam The struct mce_banks[] array is only used in mce/core.c so move the definition of struct mce_bank to mce/core.c and make the array static. Also, change the "init" field to bool type. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20190408141205.12376-2-yaz

[PATCH v2 3/6] x86/MCE/AMD: Don't cache block addresses on SMCA systems

2019-04-11 Thread Ghannam, Yazen
From: Yazen Ghannam On legacy systems, the addresses of the MCA_MISC* registers need to be recursively discovered based on a Block Pointer field in the registers. On Scalable MCA systems, the register space is fixed, and particular addresses can be derived by regular offsets for bank and registe

[PATCH v2 0/6] Handle MCA banks in a per_cpu way

2019-04-11 Thread Ghannam, Yazen
From: Yazen Ghannam The focus of this patchset is define and use the MCA bank structures and bank count per logical CPU. With the exception of patch 4, this set applies to systems in production today. Patch 1: Moves the declaration of struct mce_banks[] to the only file it's used. Patch 2: Spl

RE: [RFC PATCH] x86/mce: Check MCi_STATUS[MISCV] for usable addr on Intel only

2017-04-18 Thread Ghannam, Yazen
> -Original Message- > From: linux-edac-ow...@vger.kernel.org [mailto:linux-edac- > ow...@vger.kernel.org] On Behalf Of Borislav Petkov > Sent: Tuesday, April 18, 2017 2:39 PM > To: Ghannam, Yazen > Cc: Tony Luck ; linux-edac e...@vger.kernel.org>; lkml > Subj

RE: [PATCH v3 1/2] x86/mce/AMD: Redo logging of errors from APIC LVT interrupts

2017-04-26 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@alien8.de] > Sent: Wednesday, April 26, 2017 9:56 AM ... > > Oh well, here's an updated version with those suggestions incorporated. > > Also, I've carved out the common functionality into a _log_error_bank() which > is more compac

RE: [PATCH 1/2] x86/mce/AMD: Redo use of SMCA MCA_DE{STAT,ADDR} registers

2017-04-04 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@suse.de] > Sent: Monday, March 27, 2017 1:27 PM > To: Ghannam, Yazen ... > > static void > > -__log_error(unsigned int bank, bool deferred_err, bool threshold_err, > > u64 misc) > >

RE: [PATCH 2/2] x86/mce/AMD: Carve out SMCA bank configuration

2017-04-04 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@suse.de] > Sent: Tuesday, March 28, 2017 3:23 PM > To: Ghannam, Yazen > Cc: linux-e...@vger.kernel.org; Tony Luck ; > x...@kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH 2/2] x86/mce/AMD

RE: [PATCH 2/2] x86/mce/AMD: Carve out SMCA bank configuration

2017-04-04 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@alien8.de] > Sent: Tuesday, April 04, 2017 9:46 AM > To: Ghannam, Yazen > Cc: linux-e...@vger.kernel.org; Tony Luck ; > x...@kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH 2/2] x86/mce/AMD

RE: [PATCH 2/2] x86/mce/AMD: Carve out SMCA bank configuration

2017-04-04 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@alien8.de] > Sent: Tuesday, April 04, 2017 11:01 AM > To: Ghannam, Yazen > Cc: linux-e...@vger.kernel.org; Tony Luck ; > x...@kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH 2/2] x86/mce/AMD

RE: [PATCH v2 1/2] x86/mce/AMD: Redo use of SMCA MCA_DE{STAT,ADDR} registers

2017-04-05 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@alien8.de] > Sent: Wednesday, April 05, 2017 9:40 AM > To: Ghannam, Yazen > Cc: linux-e...@vger.kernel.org; Tony Luck ; > x...@kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v2 1/2] x86/mce/

RE: [PATCH v2 1/2] x86/mce/AMD: Redo use of SMCA MCA_DE{STAT,ADDR} registers

2017-04-05 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@alien8.de] > Sent: Wednesday, April 05, 2017 12:45 PM > To: Ghannam, Yazen > Cc: linux-e...@vger.kernel.org; Tony Luck ; > x...@kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v2 1/2] x86/mce/

RE: [PATCH v2 1/2] x86/mce/AMD: Redo use of SMCA MCA_DE{STAT,ADDR} registers

2017-04-05 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@alien8.de] > Sent: Wednesday, April 05, 2017 1:22 PM > To: Ghannam, Yazen > Cc: linux-e...@vger.kernel.org; Tony Luck ; > x...@kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v2 1/2] x86/mce/

RE: [PATCH v2 1/2] x86/mce/AMD: Redo use of SMCA MCA_DE{STAT,ADDR} registers

2017-04-05 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@alien8.de] > Sent: Wednesday, April 05, 2017 2:22 PM > To: Ghannam, Yazen > Cc: linux-e...@vger.kernel.org; Tony Luck ; > x...@kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v2 1/2] x86/mce/

RE: [PATCH v2 1/2] x86/mce/AMD: Redo use of SMCA MCA_DE{STAT,ADDR} registers

2017-04-07 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@alien8.de] > Sent: Wednesday, April 05, 2017 4:05 PM > To: Ghannam, Yazen > Cc: linux-e...@vger.kernel.org; Tony Luck ; > x...@kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v2 1/2] x86/mce/

RE: [PATCH v2 1/2] x86/mce/AMD: Redo use of SMCA MCA_DE{STAT,ADDR} registers

2017-04-11 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@alien8.de] > Sent: Friday, April 07, 2017 5:35 PM > To: Ghannam, Yazen > Cc: linux-e...@vger.kernel.org; Tony Luck ; > x...@kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v2 1/2] x86/mce/

RE: [PATCH v2 1/2] x86/mce/AMD: Redo use of SMCA MCA_DE{STAT,ADDR} registers

2017-04-11 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@alien8.de] > Sent: Tuesday, April 11, 2017 9:12 AM > To: Ghannam, Yazen > Cc: linux-e...@vger.kernel.org; Tony Luck ; > x...@kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v2 1/2] x86/mce/

RE: [PATCH v2 1/2] x86/mce/AMD: Redo use of SMCA MCA_DE{STAT,ADDR} registers

2017-04-11 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@alien8.de] > Sent: Tuesday, April 11, 2017 9:25 AM > To: Ghannam, Yazen > Cc: linux-e...@vger.kernel.org; Tony Luck ; > x...@kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v2 1/2] x86/mce/

RE: [PATCH v2 1/2] x86/mce/AMD: Redo use of SMCA MCA_DE{STAT,ADDR} registers

2017-04-11 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@alien8.de] > Sent: Tuesday, April 11, 2017 9:36 AM > To: Ghannam, Yazen > Cc: linux-e...@vger.kernel.org; Tony Luck ; > x...@kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v2 1/2] x86/mce/

RE: [PATCH 1/2] x86/CPU/AMD: Present package as die instead of socket

2017-06-27 Thread Ghannam, Yazen
> -Original Message- > From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel- > ow...@vger.kernel.org] On Behalf Of Borislav Petkov > Sent: Tuesday, June 27, 2017 1:44 PM > To: Suthikulpanit, Suravee > Cc: x...@kernel.org; linux-kernel@vger.kernel.org; Dura

RE: [PATCH] x86/mce/AMD: Fix partial SMCA bank init when CPU 0 != thread 0

2017-06-28 Thread Ghannam, Yazen
> -Original Message- > From: themo...@gmail.com [mailto:themo...@gmail.com] On Behalf Of > Jack Miller > Sent: Wednesday, June 28, 2017 1:44 PM > To: Borislav Petkov > Cc: Jack Miller ; linux-kernel@vger.kernel.org; > t...@linutronix.de; Ghannam, Yazen ; > x...@

RE: [PATCH] x86/mce/AMD: Fix partial SMCA bank init when CPU 0 != thread 0

2017-06-28 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@suse.de] > Sent: Wednesday, June 28, 2017 2:17 PM > To: Jack Miller ; Ghannam, Yazen > > Cc: linux-kernel@vger.kernel.org; t...@linutronix.de; x...@kernel.org > Subject: Re: [PATCH] x86/mce/AMD: Fix partial SM

RE: [PATCH] x86/ACPI/cstate: Allow ACPI C1 FFH MWAIT use on AMD systems

2017-05-24 Thread Ghannam, Yazen
> -Original Message- > From: Pavel Machek [mailto:pa...@ucw.cz] > Sent: Tuesday, May 23, 2017 8:25 AM > To: Ghannam, Yazen > Cc: linux...@vger.kernel.org; x...@kernel.org; linux- > ker...@vger.kernel.org; r...@rjwysocki.net; len.br...@intel.com > Subject: Re: [P

RE: [PATCH] x86/mce/AMD: Fix partial SMCA bank init when CPU 0 != thread 0

2017-06-28 Thread Ghannam, Yazen
> -Original Message- > From: themo...@gmail.com [mailto:themo...@gmail.com] On Behalf Of > Jack Miller > Sent: Wednesday, June 28, 2017 2:53 PM > To: Ghannam, Yazen > Cc: Jack Miller ; Borislav Petkov ; linux- > ker...@vger.kernel.org; t...@linutronix.de; x...@ker

RE: [PATCH] x86/mce/AMD: Fix partial SMCA bank init when CPU 0 != thread 0

2017-06-29 Thread Ghannam, Yazen
> -Original Message- > From: themo...@gmail.com [mailto:themo...@gmail.com] On Behalf Of > Jack Miller > Sent: Thursday, June 29, 2017 12:23 PM > To: Ghannam, Yazen > Cc: Jack Miller ; Borislav Petkov ; linux- > ker...@vger.kernel.org; t...@linutronix.de; x...@ker

RE: [PATCH 2/3] x86/MCE/AMD, EDAC/mce_amd: Enumerate Reserved SMCA bank type

2018-02-14 Thread Ghannam, Yazen
> -Original Message- > From: linux-edac-ow...@vger.kernel.org [mailto:linux-edac- > ow...@vger.kernel.org] On Behalf Of Borislav Petkov > Sent: Thursday, February 8, 2018 10:15 AM > To: Ghannam, Yazen > Cc: linux-e...@vger.kernel.org; linux-kernel@vger.kernel.org; b...

RE: [PATCH 1/3] x86/MCE/AMD: Redo function to get SMCA bank type

2018-02-14 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@alien8.de] > Sent: Thursday, February 8, 2018 10:05 AM > To: Ghannam, Yazen > Cc: linux-e...@vger.kernel.org; linux-kernel@vger.kernel.org; b...@suse.de; > tony.l...@intel.com; x...@kernel.org > Subject: Re: [P

RE: [PATCH 0/8] Decode IA32/X64 CPER

2018-02-26 Thread Ghannam, Yazen
> -Original Message- > From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org] > Sent: Saturday, February 24, 2018 11:47 AM > To: Ghannam, Yazen > Cc: linux-...@vger.kernel.org; Linux Kernel Mailing List ker...@vger.kernel.org>; Borislav Petkov ; the arch/x86 > maint

RE: [PATCH 2/8] efi: Decode IA32/X64 Processor Error Section

2018-02-26 Thread Ghannam, Yazen
> -Original Message- > From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel- > ow...@vger.kernel.org] On Behalf Of Ard Biesheuvel > Sent: Saturday, February 24, 2018 11:39 AM > To: Ghannam, Yazen > Cc: linux-...@vger.kernel.org; Linux Kernel Mailing List ker.

RE: [PATCH 3/8] efi: Decode IA32/X64 Processor Error Info Structure

2018-02-26 Thread Ghannam, Yazen
> -Original Message- > From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org] > Sent: Saturday, February 24, 2018 11:40 AM > To: Ghannam, Yazen > Cc: linux-...@vger.kernel.org; Linux Kernel Mailing List ker...@vger.kernel.org>; Borislav Petkov ; the arch/x86 > maint

RE: [PATCH 4/8] efi: Decode UEFI-defined IA32/X64 Error Structure GUIDs

2018-02-26 Thread Ghannam, Yazen
> -Original Message- > From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org] > Sent: Saturday, February 24, 2018 11:41 AM > To: Ghannam, Yazen > Cc: linux-...@vger.kernel.org; Linux Kernel Mailing List ker...@vger.kernel.org>; Borislav Petkov ; the arch/x86 > maint

RE: [PATCH 8/8] efi: Decode IA32/X64 Context Info structure

2018-02-26 Thread Ghannam, Yazen
> -Original Message- > From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org] > Sent: Saturday, February 24, 2018 11:46 AM > To: Ghannam, Yazen > Cc: linux-...@vger.kernel.org; Linux Kernel Mailing List ker...@vger.kernel.org>; Borislav Petkov ; the arch/x86 > maint

RE: [PATCH v2 1/8] efi: Fix IA32/X64 Processor Error Record definition

2018-02-27 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@suse.de] > Sent: Tuesday, February 27, 2018 5:47 AM > To: Ghannam, Yazen > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; > ard.biesheu...@linaro.org; x...@kernel.org > Subject: Re: [PATCH v2 1

RE: [PATCH v2 2/8] efi: Decode IA32/X64 Processor Error Section

2018-02-27 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@suse.de] > Sent: Tuesday, February 27, 2018 6:23 AM > To: Ghannam, Yazen > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; > ard.biesheu...@linaro.org; x...@kernel.org > Subject: Re: [PATCH v2 2/8]

RE: [PATCH v2 3/8] efi: Decode IA32/X64 Processor Error Info Structure

2018-02-27 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@suse.de] > Sent: Tuesday, February 27, 2018 9:26 AM > To: Ghannam, Yazen > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; > ard.biesheu...@linaro.org; x...@kernel.org > Subject: Re: [PATCH v2 3/8]

RE: [PATCH v2 4/8] efi: Decode UEFI-defined IA32/X64 Error Structure GUIDs

2018-02-27 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@suse.de] > Sent: Tuesday, February 27, 2018 9:30 AM > To: Ghannam, Yazen > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; > ard.biesheu...@linaro.org; x...@kernel.org > Subject: Re: [PATCH v2

RE: [PATCH v2 5/8] efi: Decode IA32/X64 Cache, TLB, and Bus Check structures

2018-02-27 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@suse.de] > Sent: Tuesday, February 27, 2018 10:04 AM > To: Ghannam, Yazen > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; > ard.biesheu...@linaro.org; x...@kernel.org > Subject: Re: [PATCH v2

RE: [PATCH v2 2/8] efi: Decode IA32/X64 Processor Error Section

2018-02-27 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@suse.de] > Sent: Tuesday, February 27, 2018 12:01 PM > To: Ghannam, Yazen > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; > ard.biesheu...@linaro.org; x...@kernel.org > Subject: Re: [PATCH v2

RE: [PATCH v2 3/8] efi: Decode IA32/X64 Processor Error Info Structure

2018-02-27 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@suse.de] > Sent: Tuesday, February 27, 2018 12:04 PM > To: Ghannam, Yazen > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; > ard.biesheu...@linaro.org; x...@kernel.org > Subject: Re: [PATCH v2

RE: [PATCH v2 2/8] efi: Decode IA32/X64 Processor Error Section

2018-02-27 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@suse.de] > Sent: Tuesday, February 27, 2018 12:45 PM > To: Ghannam, Yazen > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; > ard.biesheu...@linaro.org; x...@kernel.org > Subject: Re: [PATCH v2

RE: [PATCH v2 3/8] efi: Decode IA32/X64 Processor Error Info Structure

2018-02-27 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@suse.de] > Sent: Tuesday, February 27, 2018 1:03 PM > To: Ghannam, Yazen > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; > ard.biesheu...@linaro.org; x...@kernel.org > Subject: Re: [PATCH v2 3/8]

RE: [PATCH v2 3/8] efi: Decode IA32/X64 Processor Error Info Structure

2018-02-27 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@suse.de] > Sent: Tuesday, February 27, 2018 2:10 PM > To: Ghannam, Yazen > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; > ard.biesheu...@linaro.org; x...@kernel.org; Tony Luck > > Subject

RE: [PATCH 4.4 05/27] x86/efi: Build our own page table structures

2017-12-12 Thread Ghannam, Yazen
> -Original Message- > From: Greg Kroah-Hartman [mailto:gre...@linuxfoundation.org] > Sent: Sunday, December 10, 2017 4:27 PM > To: Ben Hutchings ; Ghannam, Yazen > > Cc: linux-kernel@vger.kernel.org; sta...@vger.kernel.org; Matt Fleming > ; Borislav Petkov ; A

RE: [PATCH] ACPI, APEI, EINJ: Subtract any matching Register Region from Trigger resources

2017-08-22 Thread Ghannam, Yazen
+EDAC, Boris and Tony for RAS comments. Any comments from ACPI folks? Thanks, Yazen > -Original Message- > From: Ghannam, Yazen > Sent: Thursday, August 10, 2017 1:58 PM > To: linux-a...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; r...@rjwysocki.net; l...@kernel

RE: [PATCH] ACPI, APEI, EINJ: Subtract any matching Register Region from Trigger resources

2017-08-23 Thread Ghannam, Yazen
> -Original Message- > From: Luck, Tony [mailto:tony.l...@intel.com] > Sent: Tuesday, August 22, 2017 12:03 PM > To: Ghannam, Yazen > Cc: linux-a...@vger.kernel.org; linux-kernel@vger.kernel.org; > r...@rjwysocki.net; l...@kernel.org; linux-e...@vger.kernel.org;

RE: [PATCH] x86/ACPI/cstate: Allow ACPI C1 FFH MWAIT use on AMD systems

2017-05-22 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@alien8.de] > Sent: Monday, May 22, 2017 12:22 PM > ... > What about x86_idle? > > That whole select_idle_routine() jumping through hoops. That's still doing > default_idle() on Zen, AFAICT. > > Or am I missing something? > > Be

RE: [PATCH] x86/ACPI/cstate: Allow ACPI C1 FFH MWAIT use on AMD systems

2017-05-23 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@alien8.de] > Sent: Tuesday, May 23, 2017 3:59 AM > To: Ghannam, Yazen > Cc: linux...@vger.kernel.org; x...@kernel.org; linux- > ker...@vger.kernel.org; r...@rjwysocki.net; len.br...@intel.com; > pa...@ucw.cz

RE: [PATCH 0/4] RAS: Merge mce_amd_inj into mce-inject

2017-06-06 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@alien8.de] > Sent: Tuesday, June 06, 2017 5:33 AM > To: Tony Luck ; Ghannam, Yazen > > Cc: linux-edac ; LKML ker...@vger.kernel.org> > Subject: [PATCH 0/4] RAS: Merge mce_amd_inj into mce-inject > >

RE: [PATCH] x86/mce: Always save severity in machine_check_poll

2017-06-12 Thread Ghannam, Yazen
> -Original Message- > From: linux-edac-ow...@vger.kernel.org [mailto:linux-edac- > ow...@vger.kernel.org] On Behalf Of Luck, Tony > Sent: Monday, June 12, 2017 2:08 PM > To: Ghannam, Yazen > Cc: linux-e...@vger.kernel.org; Borislav Petkov ; > x...@kernel.org; linux-k

RE: [PATCH] x86/MCE/AMD: Always give PANIC severity for UC errors in kernel context

2017-09-26 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@alien8.de] > Sent: Tuesday, September 26, 2017 8:01 AM > To: Ghannam, Yazen > Cc: linux-e...@vger.kernel.org; Tony Luck ; > x...@kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH] x86/MCE/A

RE: [PATCH] x86/MCE/AMD: Always give PANIC severity for UC errors in kernel context

2017-09-27 Thread Ghannam, Yazen
> -Original Message- > From: Borislav Petkov [mailto:b...@alien8.de] > Sent: Tuesday, September 26, 2017 6:21 PM > To: Ghannam, Yazen ... > > There are the stable branches on kernel.org and some distro kernels > > based on older kernel versions. > > > &g

RE: [PATCH] x86/mce: Always save severity in machine_check_poll

2017-06-16 Thread Ghannam, Yazen
> -Original Message- > From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel- > ow...@vger.kernel.org] On Behalf Of Borislav Petkov > Sent: Wednesday, June 14, 2017 10:21 AM > To: Ghannam, Yazen > Cc: linux-e...@vger.kernel.org; Tony Luck ; > x...@ker

RE: [PATCH 1/2] x86/mce/AMD: Define function to get SMCA bank type

2017-12-02 Thread Ghannam, Yazen
> -Original Message- > From: linux-edac-ow...@vger.kernel.org [mailto:linux-edac- > ow...@vger.kernel.org] On Behalf Of Borislav Petkov > Sent: Saturday, December 2, 2017 9:22 AM > To: Ghannam, Yazen > Cc: linux-e...@vger.kernel.org; Tony Luck ; > x...@ker

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