Hi Boris, hi Mark,
On 02.08.2018 15:09, Boris Brezillon wrote:
On Thu, 2 Aug 2018 14:53:52 +0200
Frieder Schrempf wrote:
We usually try to avoid empty commit message, even if this one is
pretty obvious, I'd suggest adding something here.
"
Fix a typo in the @drvpriv d
Hi Mark,
On 02.08.2018 12:17, Mark Brown wrote:
On Wed, Aug 01, 2018 at 09:57:33PM +0200, Boris Brezillon wrote:
Mark Brown wrote:
2/ Getting this patch [1] merged and implementing the ->get_name() hook
in this driver so that SPI NOR devs declared to the MTD layer keep
the same name
memory device in probe of m25p80
* Add Suggested-by tags
Changes in v2:
==
* Add a name field to struct spi_mem and fill it while probing
Frieder Schrempf (3):
spi: spi-mem: Fix a typo in the documentation of struct spi_mem
spi: spi-mem: Extend the SPI mem interface to set a custom
for the memory device.
Example for the FSL QSPI driver:
Name with the old driver: 21e.qspi,
or with multiple devices: 21e.qspi-0, 21e.qspi-1, ...
Name with the new driver without spi_mem_get_name: spi4.0
Suggested-by: Boris Brezillon
Signed-off-by: Frieder Schrempf
---
drivers
Signed-off-by: Frieder Schrempf
---
include/linux/spi/spi-mem.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index 4fa34a2..72cc9bc 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
By calling spi_mem_get_name(), the driver of the (Q)SPI controller can
set a custom name for the memory device if necessary.
This is useful to keep mtdparts compatible when controller drivers are
ported from the MTD to the SPI layer.
Suggested-by: Boris Brezillon
Signed-off-by: Frieder Schrempf
Hi Rob,
On 11.07.2018 17:54, Rob Herring wrote:
On Thu, Jul 05, 2018 at 01:15:00PM +0200, Frieder Schrempf wrote:
Move the documentation of the old SPI NOR driver to the place of the new
SPI memory interface based driver.
Signed-off-by: Frieder Schrempf
---
Changes in v2
Hi Rob,
On 11.07.2018 18:05, Rob Herring wrote:
On Thu, Jul 05, 2018 at 01:15:01PM +0200, Frieder Schrempf wrote:
Adjust the documentation of the new SPI memory interface based
driver to reflect the new drivers settings.
Bindings shouldn't change (other than new properties) due to d
Hi Rob,
On 12.07.2018 17:20, Rob Herring wrote:
On Thu, Jul 12, 2018 at 2:14 AM Frieder Schrempf
wrote:
Hi Rob,
On 11.07.2018 18:05, Rob Herring wrote:
On Thu, Jul 05, 2018 at 01:15:01PM +0200, Frieder Schrempf wrote:
Adjust the documentation of the new SPI memory interface based
driver
Hi,
On Fri, Feb 09, 2018 at 03:01:00PM +0100, Ulf Hansson wrote:
[...]
>> > I'd like to know if any progress has been made on that problem
(I may
>> > have missed patches).
>> > Had you had the time to look at the issue?
>>
>> I have looked at the issue, but not manage to cook some patches
Hi Boris, hi Yogesh,
first, thank you for testing and debugging the new driver.
On 19.06.2018 10:46, Boris Brezillon wrote:
On Tue, 19 Jun 2018 08:31:25 +
Yogesh Narayan Gaur wrote:
[...]
On Tue, 19 Jun 2018 07:10:37 +
Yogesh Narayan Gaur wrote:
Let us take below layout of me
dev_pm_ops?
This was taken from the original driver. I will add a struct dev_pm_ops
to hold fsl_qspi_suspend() and fsl_qspi_resume().
+};
+MODULE_AUTHOR("Freescale Semiconductor Inc."); MODULE_AUTHOR("Boris
+Brezillion "); MODULE_AUTHOR("Frieder
+Schrempf "); MODULE_LICENSE("GPL v2");
Wrong indentation.
What is wrong? Some newlines are missing here between the MODULE_
macros, but in my original patch it seems correct.
Thank you for your review,
Frieder
Move the documentation of the old SPI NOR driver to the place of the new
SPI memory interface based driver and adjust the content to reflect the
new drivers settings.
Signed-off-by: Frieder Schrempf
---
.../devicetree/bindings/mtd/fsl-quadspi.txt | 65 --
.../devicetree
ll be removed after the old driver was disabled to avoid
breaking ls1021a-moxa-uc-8410a.dts.
Signed-off-by: Frieder Schrempf
---
arch/arm/boot/dts/imx6sx-sdb-reva.dts | 8 ++--
arch/arm/boot/dts/imx6sx-sdb.dts| 8 ++--
arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | 2 ++
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 1
The new driver at spi/spi-fsl-qspi.c replaces the old SPI NOR driver
at mtd/fsl-quadspi.c. Switch to the new driver in the defconfigs.
Signed-off-by: Frieder Schrempf
---
arch/arm/configs/imx_v6_v7_defconfig | 2 +-
arch/arm/configs/multi_v7_defconfig | 2 +-
2 files changed, 2 insertions
There's a new driver using the SPI memory interface of the SPI framework
at spi/spi-fsl-qspi.c, which can be used together with m25p80.c to
replace the functionality of this SPI NOR driver.
Signed-off-by: Frieder Schrempf
---
drivers/mtd/spi-nor/Kconfig |9 -
drivers/mtd/sp
By calling spi_mem_get_name(), the driver of the (Q)SPI controller can
set a custom name for the memory device if necessary.
This is useful to keep mtdparts compatible when controller drivers are
ported from the MTD to the SPI layer.
Signed-off-by: Frieder Schrempf
---
drivers/mtd/devices
-by: Frieder Schrempf
---
drivers/spi/Kconfig| 11 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-fsl-qspi.c | 929
3 files changed, 941 insertions(+)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index e62ac32..6de0df5 100644
--- a
be removed.
The property 'fsl,qspi-has-second-chip' is not needed anymore
and will be removed after the old driver was disabled to avoid
breaking fsl-ls1046a-rdb.dts.
Signed-off-by: Frieder Schrempf
---
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 3 ++-
arch/arm64/boot/dt
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1
The driver was ported to the SPI framework so it can be used as
a generic SPI memory driver and not only for SPI NOR.
Reflect this transition in the MAINTAINERS file.
Signed-off-by: Frieder Schrempf
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
.
Example for the FSL QSPI driver:
Name with the old driver: 21e.qspi,
or with multiple devices: 21e.qspi-0, 21e.qspi-1, ...
Name with the new driver without spi_mem_get_name: spi4.0
Signed-off-by: Frieder Schrempf
---
drivers/spi/spi-mem.c | 25
Hi Boris,
On 30.05.2018 16:32, Boris Brezillon wrote:
Hi Frieder,
On Wed, 30 May 2018 15:14:30 +0200
Frieder Schrempf wrote:
When porting (Q)SPI controller drivers from the MTD layer to the SPI
layer, the naming scheme for the memory devices changes. To be able
to keep compatibility with
Hi Boris,
On 30.05.2018 16:58, Boris Brezillon wrote:
Hi Frieder,
On Wed, 30 May 2018 15:14:32 +0200
Frieder Schrempf wrote:
+
+static const char *fsl_qspi_get_name(struct spi_mem *mem)
+{
+ struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+ struct devic
Hi Boris,
On 30.05.2018 17:06, Boris Brezillon wrote:
On Wed, 30 May 2018 15:14:33 +0200
Frieder Schrempf wrote:
Move the documentation of the old SPI NOR driver to the place of the new
SPI memory interface based driver and adjust the content to reflect the
new drivers settings.
Maybe it&#
Hi Yogesh,
On 30.05.2018 16:24, Boris Brezillon wrote:
Hi Yogesh,
On Wed, 30 May 2018 13:50:51 +
Yogesh Narayan Gaur wrote:
Hi Frieder,
Thanks for migrating the fsl-quadspi.c driver on the new SPI
framework. This patch is using dynamic LUT approach to create the LUT
at run time instead
Hi Boris,
On 30.05.2018 17:10, Boris Brezillon wrote:
On Wed, 30 May 2018 15:14:34 +0200
Frieder Schrempf wrote:
The FSL QSPI driver was moved to the SPI framework and it now
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is use
.
Example for the FSL QSPI driver:
Name with the old driver: 21e.qspi,
or with multiple devices: 21e.qspi-0, 21e.qspi-1, ...
Name with the new driver without spi_mem_get_name: spi4.0
Signed-off-by: Frieder Schrempf
---
Changes in v2:
==
* Add a name field to struct
Move the documentation of the old SPI NOR driver to the place of the new
SPI memory interface based driver.
Signed-off-by: Frieder Schrempf
---
Changes in v2:
==
* Split the moving and editing of the dt-bindings in two patches
.../devicetree/bindings/mtd/fsl-quadspi.txt | 65
By calling spi_mem_get_name(), the driver of the (Q)SPI controller can
set a custom name for the memory device if necessary.
This is useful to keep mtdparts compatible when controller drivers are
ported from the MTD to the SPI layer.
Signed-off-by: Frieder Schrempf
---
drivers/mtd/devices
ll be removed after the old driver was disabled to avoid
breaking ls1021a-moxa-uc-8410a.dts.
Signed-off-by: Frieder Schrempf
---
arch/arm/boot/dts/imx6sx-sdb-reva.dts | 8 ++--
arch/arm/boot/dts/imx6sx-sdb.dts| 8 ++--
arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | 2 ++
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 1
There's a new driver using the SPI memory interface of the SPI framework
at spi/spi-fsl-qspi.c, which can be used together with m25p80.c to
replace the functionality of this SPI NOR driver.
Signed-off-by: Frieder Schrempf
---
drivers/mtd/spi-nor/Kconfig |9 -
drivers/mtd/sp
be removed.
The property 'fsl,qspi-has-second-chip' is not needed anymore
and will be removed after the old driver was disabled to avoid
breaking fsl-ls1046a-rdb.dts.
Signed-off-by: Frieder Schrempf
---
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 3 ++-
arch/arm64/boot/dt
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1
The driver was ported to the SPI framework so it can be used as
a generic SPI memory driver and not only for SPI NOR.
Reflect this transition in the MAINTAINERS file.
Signed-off-by: Frieder Schrempf
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
The new driver at spi/spi-fsl-qspi.c replaces the old SPI NOR driver
at mtd/fsl-quadspi.c. Switch to the new driver in the defconfigs.
Signed-off-by: Frieder Schrempf
---
arch/arm/configs/imx_v6_v7_defconfig | 2 +-
arch/arm/configs/multi_v7_defconfig | 2 +-
2 files changed, 2 insertions
Adjust the documentation of the new SPI memory interface based
driver to reflect the new drivers settings.
Signed-off-by: Frieder Schrempf
---
Changes in v2:
==
* Split the moving and editing of the dt-bindings in two patches
.../devicetree/bindings/spi/spi-fsl-qspi.txt| 22
-by: Frieder Schrempf
---
Changes in v2:
==
* Add Yogesh Gaur and Suresh Gupta as authors
* Use GENMASK() for generating bitmasks
* Use callback functions for read/write of registers
* Attach the seq variable to the selected CS
* Avoid using conditional in read/write loop
* Avoid infinite
Hi Boris,
On 05.07.2018 14:39, Boris Brezillon wrote:
Hi Frieder,
On Thu, 5 Jul 2018 13:14:57 +0200
Frieder Schrempf wrote:
When porting (Q)SPI controller drivers from the MTD layer to the SPI
layer, the naming scheme for the memory devices changes. To be able
to keep compatibility with
Hi Boris,
On 05.07.2018 14:56, Boris Brezillon wrote:
On Thu, 5 Jul 2018 13:14:58 +0200
Frieder Schrempf wrote:
By calling spi_mem_get_name(), the driver of the (Q)SPI controller can
set a custom name for the memory device if necessary.
This is useful to keep mtdparts compatible when
Hi Quentin,
On 09.10.2018 09:52, Quentin Schulz wrote:
Hi Frieder,
On Mon, Oct 08, 2018 at 11:53:21AM +0200, Frieder Schrempf wrote:
Hi,
On 27.09.2018 10:14, Maxime Ripard wrote:
On Wed, Sep 26, 2018 at 10:19:22PM +0200, Hans de Goede wrote:
On 26-09-18 16:44, Frieder Schrempf wrote:
Hi
From: Frieder Schrempf
This driver is derived from the SPI NOR driver at
mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface
of the SPI framework to issue flash memory operations to up to
four connected flash chips (2 buses with 2 CS each).
The controller does not support generic
From: Frieder Schrempf
Adjust the documentation of the new SPI memory interface based
driver to reflect the new drivers settings.
The "old" driver was using the "fsl,qspi-has-second-chip" property to
select one of two dual chip setups (two chips on one bus or two chips
on
From: Frieder Schrempf
The FSL QSPI driver was moved to the SPI framework and it now
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.
Also the properties 'num-cs' and 'bus-num' were never rea
From: Frieder Schrempf
The FSL QSPI driver was moved to the SPI framework and it now
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.
Also the properties 'bus-num', 'fsl,spi-num-chipselect
From: Frieder Schrempf
The new driver at spi/spi-fsl-qspi.c replaces the old SPI NOR driver
at mtd/fsl-quadspi.c. Switch to the new driver in the defconfigs.
Signed-off-by: Frieder Schrempf
---
arch/arm/configs/imx_v6_v7_defconfig | 2 +-
arch/arm/configs/multi_v7_defconfig | 2 +-
2 files
From: Frieder Schrempf
There's a new driver using the SPI memory interface of the SPI framework
at spi/spi-fsl-qspi.c, which can be used together with m25p80.c to
replace the functionality of this SPI NOR driver.
Signed-off-by: Frieder Schrempf
---
drivers/mtd/spi-nor/Kconfig |
From: Frieder Schrempf
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm/boot/dts/ls1021a-m
From: Frieder Schrempf
Move the documentation of the old SPI NOR driver to the place of the new
SPI memory interface based driver.
Signed-off-by: Frieder Schrempf
---
.../devicetree/bindings/mtd/fsl-quadspi.txt | 65
.../devicetree/bindings/spi/spi-fsl-qspi.txt
From: Frieder Schrempf
The driver was ported to the SPI framework so it can be used as
a generic SPI memory driver and not only for SPI NOR.
Reflect this transition in the MAINTAINERS file.
Signed-off-by: Frieder Schrempf
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
From: Frieder Schrempf
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm64/boot/dts/freesc
Hi,
On 27.09.2018 10:14, Maxime Ripard wrote:
On Wed, Sep 26, 2018 at 10:19:22PM +0200, Hans de Goede wrote:
On 26-09-18 16:44, Frieder Schrempf wrote:
Hi,
On Fri, Feb 09, 2018 at 03:01:00PM +0100, Ulf Hansson wrote:
[...]
I'd like to know if any progress has been made on that proble
Some SOCs in the i.MX6 family have a USB host controller that is
only capable of the HSIC interface and has no on-board PHY.
To be able to use these controllers, we need to add "usb-nop-xceiv"
dummy PHYs.
Signed-off-by: Frieder Schrempf
---
arch/arm/boot/dts/imx6qdl
Hi Boris, Yogesh,
On 17.09.2018 13:37, Boris Brezillon wrote:
Hi Yogesh,
On Mon, 17 Sep 2018 15:18:26 +0530
Yogesh Gaur wrote:
+
+ /*
+* R/W functions for big- or little-endian registers:
+* The FSPI controller's endianness is independent of
+* the CPU core's en
Hi Yogesh,
I have some remarks about your general approach that came to me when
looking at the FSPI driver with the things at the back of my mind, that
I've learned from working at the FSL QSPI driver.
On 17.09.2018 11:48, Yogesh Gaur wrote:
- Add a driver for NXP FlexSPI host controller
(0
Hi Marek, hi Boris,
On 09.07.2018 23:34, Boris Brezillon wrote:
+Fabio
Hi Yogesh,
On Wed, 13 Jun 2018 11:38:12 +0530
Yogesh Gaur wrote:
Some SPI controllers can't write nor->page_size bytes in a single
step because their TX FIFO is too small.
Allow nor->write() to return a size that is sma
nd I guess this deserves a "Fixes" and "Cc: stable" tag, so:
Fixes: c1c9d41319c3 ("dt-bindings: imx: Add pinctrl binding doc for imx8mm")
Cc: sta...@vger.kernel.org
Reviewed-by: Frieder Schrempf
---
arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h | 2 +-
1 file chan
Hi Abel,
On 17.11.20 15:48, Abel Vesa wrote:
On 20-11-11 17:13:25, Dong Aisheng wrote:
On Tue, Nov 3, 2020 at 7:22 PM Abel Vesa wrote:
...
+static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+ struct i
On 10.08.20 12:57, Robin Gong wrote:
On 2020/08/10 15:33 Frieder Schrempf wrote:
Hi Robin,
This patch seems to break UART DMA in case the ROM firmware is used. In that
case sdma->script_number is set to SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1, so
the ROM scripts at uart_2_mcu_addr
Hi Robin,
On 24.07.20 20:51, Robin Gong wrote:
For the compatibility of NXP internal legacy kernel before 4.19 which
is based on uart ram script and upstreaming kernel based on uart rom
script, add both uart ram/rom script in latest sdma firmware. By default
uart rom script used.
Besides, add tw
On 22.02.21 16:08, Schrempf Frieder wrote:
From: Frieder Schrempf
This fixes the return value of pca9450_i2c_probe() to use the correct
error code when getting the sd-vsel GPIO fails.
Signed-off-by: Frieder Schrempf
Sorry, I just noticed, that the PR for v5.12 was already sent, but I
On 30.11.20 12:44, Andy Shevchenko wrote:
On Mon, Nov 30, 2020 at 1:06 PM Schrempf Frieder
wrote:
From: Frieder Schrempf
There are other NXP NCI compatible NFC controllers such as the PN7150
that use an integrated firmware and therefore do not have a GPIO to
select firmware downloading mode
On 26.09.2018 06:53, Chen-Yu Tsai wrote:
The Pine64 Rock64 board comes with a GigaDevice GD25Q128CSIG
or GD25Q127CSIG chip, which is a 128 Mbit SPI NOR flash chip
that supports the JEDEC read-ID command.
This patch enables the SPI controller and adds a device node
for the flash chip using the ge
Hi Yogesh,
On 05.09.2018 12:07, Yogesh Narayan Gaur wrote:
Hi Boris,
-Original Message-
From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
Sent: Tuesday, September 4, 2018 8:29 PM
To: Yogesh Narayan Gaur
Cc: linux-...@lists.infradead.org; marek.va...@gmail.com; linux-
s...@vge
Hi Boris,
On 29.09.2018 17:40, Boris Brezillon wrote:
Hi Yogesh,
On Fri, 21 Sep 2018 15:51:59 +0530
Yogesh Gaur wrote:
+/* Registers used by the driver */
+#define FSPI_MCR0 0x00
+#define FSPI_MCR0_AHB_TIMEOUT_SHIFT24
+#define FSPI_MCR0_AHB_TIMEOUT_MASK (0xFF <<
.
Signed-off-by: Frieder Schrempf
---
Changes in v2:
- split into 3 separate patches
- make volume properties optional
.../devicetree/bindings/input/pwm-beeper.txt | 22 ++
1 file changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/input/pwm
This patch adds the devicetree bindings to set the volume levels
and the default volume level.
Signed-off-by: Frieder Schrempf
---
Changes in v3:
- none
drivers/input/misc/pwm-beeper.c | 49 ++---
1 file changed, 46 insertions(+), 3 deletions(-)
diff
This patch adds the documentation for the devicetree bindings to set
the volume levels.
Signed-off-by: Frieder Schrempf
---
Changes in v3:
- change description of volume-levels to be used for linear levels
.../devicetree/bindings/input/pwm-beeper.txt | 20
1 file
volume
levels (0 - mute, 4 - max. volume).
Signed-off-by: Frieder Schrempf
---
Changes in v3:
- update date
.../ABI/testing/sysfs-class-input-pwm-beeper | 17 ++
drivers/input/misc/pwm-beeper.c| 71 +-
2 files changed, 87 insertions(+), 1 deletion
adjustment is done by changing the duty cycle of
the pwm signal.
Changes in v3:
- update date
- change description of volume-levels to be used for linear levels
Frieder Schrempf (3):
input: pwm-beeper: add feature to set volume via sysfs
input: pwm-beeper: add documentation for volume devicetree
Hi Dmitry,
On 19.01.2017 22:29, Dmitry Torokhov wrote:
Hi Frieder,
On Thu, Jan 19, 2017 at 04:24:08PM +0100, Frieder Schrempf wrote:
Make the driver accept switching volume levels via sysfs.
This can be helpful if the beep/bell sound intensity needs
to be adapted to the environment of the
On 19.01.2017 22:30, Dmitry Torokhov wrote:
On Thu, Jan 19, 2017 at 04:24:10PM +0100, Frieder Schrempf wrote:
This patch adds the devicetree bindings to set the volume levels
and the default volume level.
Signed-off-by: Frieder Schrempf
---
Changes in v3:
- none
drivers/input/misc/pwm
generic device properties instead of dt properties
Frieder Schrempf (3):
input: pwm-beeper: add feature to set volume via sysfs
input: pwm-beeper: add documentation for volume devicetree bindings
input: pwm-beeper: add devicetree bindings to set volume levels
Documentation/ABI/testing/sysfs
volume
levels (0 - mute, 4 - max. volume).
Signed-off-by: Frieder Schrempf
---
Changes in v4:
- move sysfs attributes from class/input to devices/pwm-beeper
- rename max_volume_level to max_volume
- move array allocation to probe function
- rename attribute structs
- remove needless code
This patch adds the documentation for the devicetree bindings to set
the volume levels.
Signed-off-by: Frieder Schrempf
Acked-by: Rob Herring
---
Changes in v4:
- none
.../devicetree/bindings/input/pwm-beeper.txt | 20
1 file changed, 20 insertions(+)
diff --git
This patch adds the devicetree bindings to set the volume levels
and the default volume level.
Signed-off-by: Frieder Schrempf
---
Changes in v4:
- use generic device properties instead of dt properties
drivers/input/misc/pwm-beeper.c | 63 -
1 file
Hello David,
On 20.01.2017 20:11, David Lechner wrote:
On 01/19/2017 03:37 PM, Dmitry Torokhov wrote:
On Thu, Jan 19, 2017 at 04:24:07PM +0100, Frieder Schrempf wrote:
Make the driver accept switching volume levels via sysfs.
This can be helpful if the beep/bell sound intensity needs
to be
adjustment is done by changing the duty cycle of
the pwm signal.
Changes in v5:
- fix renaming of max_volume_level to max_volume
- remove needless variable declaration
Frieder Schrempf (3):
input: pwm-beeper: add feature to set volume via sysfs
input: pwm-beeper: add documentation for volume
volume
levels (0 - mute, 4 - max. volume).
Signed-off-by: Frieder Schrempf
---
Changes in v5:
- none
Documentation/ABI/testing/sysfs-devices-pwm-beeper | 17 +
drivers/input/misc/pwm-beeper.c| 84 +-
2 files changed, 100 insertions(+), 1 deletion
This patch adds the documentation for the devicetree bindings to set
the volume levels.
Signed-off-by: Frieder Schrempf
Acked-by: Rob Herring
---
Changes in v5:
- none
.../devicetree/bindings/input/pwm-beeper.txt | 20
1 file changed, 20 insertions(+)
diff --git
This patch adds the devicetree bindings to set the volume levels
and the default volume level.
Signed-off-by: Frieder Schrempf
---
Changes in v5:
- fix renaming of max_volume_level to max_volume
- remove needless variable declaration
drivers/input/misc/pwm-beeper.c | 60
On 16.02.2017 22:44, David Lechner wrote:
On 02/16/2017 03:15 PM, Frieder Schrempf wrote:
Hello David,
On 20.01.2017 20:11, David Lechner wrote:
On 01/19/2017 03:37 PM, Dmitry Torokhov wrote:
On Thu, Jan 19, 2017 at 04:24:07PM +0100, Frieder Schrempf wrote:
Make the driver accept switching
On 02.07.20 16:25, Mark Brown wrote:
On Thu, Jul 02, 2020 at 04:18:46PM +0200, Schrempf Frieder wrote:
From: Frieder Schrempf
Allow external SPI ports on Kontron boards to use the spidev driver.
I'd have expected this to require loading a DT overlay for whatever's
attached?
My
Hi Geert,
On 02.07.20 16:57, Geert Uytterhoeven wrote:
Hi Frieder,
On Thu, Jul 2, 2020 at 4:46 PM Frieder Schrempf
wrote:
On 02.07.20 16:25, Mark Brown wrote:
On Thu, Jul 02, 2020 at 04:18:46PM +0200, Schrempf Frieder wrote:
From: Frieder Schrempf
Allow external SPI ports on Kontron
On 02.07.20 17:07, Mark Brown wrote:
On Thu, Jul 02, 2020 at 04:46:09PM +0200, Frieder Schrempf wrote:
My intention is to use the spidev driver in the default board DT for an
interface that is routed to an extension connector and has no dedicated
slave device attached onboard. So users can
On 02.07.20 18:24, Frieder Schrempf wrote:
On 02.07.20 17:07, Mark Brown wrote:
On Thu, Jul 02, 2020 at 04:46:09PM +0200, Frieder Schrempf wrote:
My intention is to use the spidev driver in the default board DT for an
interface that is routed to an extension connector and has no dedicated
On 13.07.20 17:11, Mark Brown wrote:
On Mon, Jul 13, 2020 at 03:19:52PM +0200, Frieder Schrempf wrote:
I would have expected that there is some kind of existing userspace API to
load an overlay manually, but it seems like there isn't!?
So what's the reasoning behind this? How c
On 01.10.20 14:34, Schrempf Frieder wrote:
From: Frieder Schrempf
In order to use ultra high speed modes (UHS) on the SD card slot, we
add matching pinctrls and fix the voltage switching for LDO5 of the
PMIC, by providing the SD_VSEL pin as GPIO to the PMIC driver.
Signed-off-by: Frieder
On 01.10.20 14:53, Mark Brown wrote:
On Thu, Oct 01, 2020 at 02:34:31PM +0200, Schrempf Frieder wrote:
+ pca9450->sd_vsel_gpio = gpiod_get_optional(pca9450->dev, "sd-vsel",
GPIOD_OUT_HIGH);
We need a patch adding this to the binding document too.
Right, totally forgot about that.
On 01.10.20 14:34, Schrempf Frieder wrote:
From: Frieder Schrempf
In order to use ultra high speed modes (UHS) on the SD card slot, we
add matching pinctrls and fix the voltage switching for LDO5 of the
PMIC, by providing the SD_VSEL pin as GPIO to the PMIC driver.
Signed-off-by: Frieder
On 01.10.20 14:59, Krzysztof Kozlowski wrote:
On Thu, Oct 01, 2020 at 02:06:59PM +0200, Schrempf Frieder wrote:
From: Frieder Schrempf
Add entries for the SoMs and boards based on i.MX8MM from Kontron
Electronics GmbH.
Signed-off-by: Frieder Schrempf
Reviewed-by: Rob Herring
---
Changes
On 01.10.20 14:57, Krzysztof Kozlowski wrote:
On Thu, Oct 01, 2020 at 02:06:58PM +0200, Schrempf Frieder wrote:
From: Frieder Schrempf
Kontron Electronics GmbH offers small and powerful SoMs based on the
i.MX8M Mini SoC including PMIC, LPDDR4-RAM, eMMC and SPI NOR.
The matching baseboards
On 01.10.20 15:30, Frieder Schrempf wrote:
On 01.10.20 14:57, Krzysztof Kozlowski wrote:
On Thu, Oct 01, 2020 at 02:06:58PM +0200, Schrempf Frieder wrote:
From: Frieder Schrempf
Kontron Electronics GmbH offers small and powerful SoMs based on the
i.MX8M Mini SoC including PMIC, LPDDR4-RAM
On 17.08.20 10:51, Shawn Guo wrote:
On Thu, Jul 16, 2020 at 06:11:58PM +0200, Schrempf Frieder wrote:
From: Frieder Schrempf
Kontron Electronics GmbH offers small and powerful SoMs based on the
i.MX8M Mini SoC including PMIC, LPDDR4-RAM, eMMC and SPI NOR.
The matching baseboards have the
y by its name. I probably should have
tested this more properly.
Reviewed-by: Frieder Schrempf
---
v1 -> v2:
* Simplify commit message and error (Krzysztof).
* Pick up Krzysztof's tag.
arch/arm64/boot/dts/freescale/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
unction parameter or member '0'
not described in 'SPINAND_OP_VARIANTS'
Cc: Miquel Raynal
Cc: Richard Weinberger
Cc: Vignesh Raghavendra
Cc: Yoshio Furuyama
Cc: Frieder Schrempf
Cc: linux-...@lists.infradead.org
Signed-off-by: Lee Jones
Reviewed-by: Frieder Schrempf
On 14.07.20 21:29, Mark Brown wrote:
On Tue, Jul 14, 2020 at 10:54:15AM +0200, Frieder Schrempf wrote:
It would still be quite nice to benefit from the flexibility of DT overlays
not only for the SPI use case. But before I come up with any custom
solution, for now I will rather have the device
On 15.07.20 13:36, Mark Brown wrote:
On Wed, Jul 15, 2020 at 09:26:29AM +0200, Frieder Schrempf wrote:
On 14.07.20 21:29, Mark Brown wrote:
On Tue, Jul 14, 2020 at 10:54:15AM +0200, Frieder Schrempf wrote:
patch in our own tree, or if a node with a custom compatible string like for
example
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