Hello,
On Mon, 21 Dec 2020 at 12:02, Lee Jones wrote:
>
> On Sun, 20 Dec 2020, Dmitry Baryshkov wrote:
>
> > Qualcomm QCA639x is a family of WiFi + Bluetooth SoCs, with BT part
> > being controlled through the UART and WiFi being present on PCIe
> > bus. Both blocks
Qualcomm QCA639x is a family of WiFi + Bluetooth chips, with BT part
being controlled through the UART and WiFi being present on PCIe
bus. Both blocks share common power sources wich should be turned on
before either of devices can be probed. Declare common 'qca639x' driver
providing a power domain
Qualcomm QCA6390/1 is a family of WiFi + Bluetooth SoCs, with BT part
being controlled through the UART and WiFi being present on PCIe bus.
Both blocks share common power sources. Add binding to describe power
sequencing required to power up this device.
Signed-off-by: Dmitry Baryshkov
Qualcomm QCA639x is a family of WiFi + Bluetooth SoCs, with BT part
being controlled through the UART and WiFi being present on PCIe
bus. Both blocks share common power sources. Add device driver handling
power sequencing of QCA6390/1.
Signed-off-by: Dmitry Baryshkov
---
drivers/misc/Kconfig
Hi Rob,
On Thu, 14 Jan 2021 at 17:33, Rob Herring wrote:
>
> On Sat, Jan 2, 2021 at 9:41 PM Dmitry Baryshkov
> wrote:
> >
> > Hello,
> >
> > On Fri, 1 Jan 2021 at 01:50, Rob Herring wrote:
> > >
> > > On Sun, Dec 20, 2020 at 07:58:42PM +0300,
According to the datasheet pm8009's HFS515 regulators have 16mV
resolution rather than declared 1.6 mV. Correct the resolution.
Signed-off-by: Dmitry Baryshkov
Fixes: 06369bcc15a1 ("regulator: qcom-rpmh: Add support for SM8150")
---
drivers/regulator/qcom-rpmh-regulator.c | 2 +-
PM8009 has special revision (P=1), which is to be used for sm8250
platform. The major difference is the S2 regulator which supplies 0.95 V
instead of 2.848V. Declare regulators data to be used for this chip
revision. The datasheet calls the chip just pm8009-1, so use the same
name.
Fix pm8009 compatibility string to reference pm8009 revision specific to
sm8250 platform. Also add S2 regulator to be used for qca639x.
Signed-off-by: Dmitry Baryshkov
Fixes: b1d2674e6121 ("arm64: dts: qcom: Add basic devicetree support for
QRB5165 RB5")
---
arch/arm64/boot/dts/qc
: Dmitry Baryshkov
Fixes: 06369bcc15a1 ("regulator: qcom-rpmh: Add support for SM8150")
---
drivers/regulator/qcom-rpmh-regulator.c | 26 +
1 file changed, 26 insertions(+)
diff --git a/drivers/regulator/qcom-rpmh-regulator.c
b/drivers/regulator/qcom-rpmh-regulat
PMIC pm8009 has special revision (P=1) made for sm8250 platform. The
major difference is the S2 regulator which supplies 0.95 V instead of
2.848V. Add special compatibility string for this chip revision.
The datasheet calls the chip just pm8009-1, so use the same name.
Signed-off-by: Dmitry
)
Dmitry Baryshkov (6):
dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SM8250
phy: qcom-qmp: move DP functions to callbacks
phy: qcom-qmp: rename common registers
phy: qcom-qmp: add support for sm8250-usb3-dp
Add compatible for SM8250 in QMP USB3 DP PHY bindings.
Signed-off-by: Dmitry Baryshkov
---
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 -
Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 2 ++
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a
A plenty of DP PHY registers are common between V3 and V4. To simplify
V4 code, rename all common registers.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 50 ++---
drivers/phy/qualcomm/phy-qcom-qmp.h | 37 ++---
2 files
In preparation to adding support for V4 DP PHY move DP functions to
callbacks at struct qmp_phy_cfg.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 438 +++-
1 file changed, 231 insertions(+), 207 deletions(-)
diff --git a/drivers/phy/qualcomm
Add support for QMP V4 Combo USB3+DP PHY (for SM8250 platform).
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 388 ++--
drivers/phy/qualcomm/phy-qcom-qmp.h | 40 ++-
2 files changed, 406 insertions(+), 22 deletions(-)
diff --git a/drivers
USB1 QMP PHY is not just a USB3 PHY, but USB3+DP PHY. Change device tree
nodes accordingly.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
Plug dp_phy-provided clocks to display clock controller.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index
On 15/02/2021 19:27, Jonathan Marek wrote:
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jonathan Marek
Other that few comments bellow:
Reviewed-by: Dmitry
Hello,
On 10/02/2021 03:52, Jordan Crouse wrote:
Most a6xx targets have security issues that were fixed with new versions
of the microcode(s). Make sure that we are booting with a safe version of
the microcode for the target and print a message and error if not.
v2: Add more informative error m
f5df13 ("dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy
information")
Cc: Stephen Boyd
Cc: Sandeep Maheswaram
Signed-off-by: Dmitry Baryshkov
Acked-by: Rob Herring
Reviewed-by: Stephen Boyd
Reviewed-by: Bjorn Andersson
---
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
f5df13 ("dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy
information")
Cc: Stephen Boyd
Cc: Sandeep Maheswaram
Signed-off-by: Dmitry Baryshkov
Acked-by: Rob Herring
Reviewed-by: Stephen Boyd
Reviewed-by: Bjorn Andersson
---
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
Changes since v5:
- Rebase on top of phy-next
- Rework 'move DP functions to callbacks' patch to leave most of the
code in place, using function prototypes.
Changes since v4:
- Fix typo in the qcom,sc7180-qmp-usb3-phy name in the first patch
Changes since v3:
- Move qcom,sc7180-qmp-usb3-ph
Add compatible for SM8250 in QMP USB3 DP PHY bindings.
Signed-off-by: Dmitry Baryshkov
Acked-by: Rob Herring
Reviewed-by: Bjorn Andersson
---
Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings
Plug dp_phy-provided clocks to display clock controller.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Bjorn Andersson
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts
Add support for QMP V4 Combo USB3+DP PHY (for SM8250 platform).
Signed-off-by: Dmitry Baryshkov
Acked-by: Bjorn Andersson
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 394 ++--
drivers/phy/qualcomm/phy-qcom-qmp.h | 40 ++-
2 files changed, 412 insertions(+), 22 deletions
USB1 QMP PHY is not just a USB3 PHY, but USB3+DP PHY. Change device tree
nodes accordingly.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Bjorn Andersson
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch
A plenty of DP PHY registers are common between V3 and V4. To simplify
V4 code, rename all common registers.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 50 ++---
drivers/phy/qualcomm/phy-qcom-qmp.h | 37 ++---
2 files
In preparation to adding support for V4 DP PHY move DP functions to
callbacks at struct qmp_phy_cfg.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 73 -
1 file changed, 51 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/qualcomm
On 31/03/2021 14:27, Kalyan Thota wrote:
WARN_ON was introduced by the below commit to catch runtime resumes
that are getting triggered before icc path was set.
"drm/msm/disp/dpu1: icc path needs to be set before dpu runtime resume"
For the targets where the bw scaling is not enabled, this WARN
On Mon, 15 Mar 2021 at 20:39, Douglas Anderson wrote:
>
> As per Dmitry Baryshkov [1]:
> a) The 2nd "reg" should be 0x3c because "Offset 0x38 is
>USB3_DP_COM_REVISION_ID3 (not used by the current driver though)."
> b) The 3rd "reg" "is
en-Cohen
> Cc: Mark Brown
> Cc: Cheng-Yi Chiang
> Cc: Benson Leung
> Cc: Zhang Rui
> Cc: Daniel Lezcano
> Cc: Greg Kroah-Hartman
> Cc: Stefan Wahren
> Cc: Masahiro Yamada
> Cc: Odelu Kukatla
> Cc: Alex Elder
> Cc: Suman Anna
> Cc: Kuninori Mori
Bjorn Andersson
> Cc: Zhang Rui
> Cc: Daniel Lezcano
> Cc: Linus Walleij
> Cc: Kevin Tsai
> Cc: Dmitry Baryshkov
> Cc: Sebastian Reichel
> Cc: Mark Brown
> Cc: linux-...@vger.kernel.org
> Cc: linux-in...@vger.kernel.org
> Cc: linux...@vger.kernel.org
> Sig
On Fri, 26 Mar 2021 at 04:20, Rob Herring wrote:
>
> On Thu, Mar 18, 2021 at 10:59:25PM +0300, Dmitry Baryshkov wrote:
> > Add compatible for SM8250 in QMP USB3 DP PHY bindings.
> >
> > Signed-off-by: Dmitry Baryshkov
> > ---
> > Documentation/devic
Changes since v3:
- Move qcom,sc7180-qmp-usb3-phy and qcom,sdm845-qmp-usb3-phy from
qcom,qmp-usb3-dp.yaml to qcom,qmp-phy.yaml
- Do not touch qcom,sm8250-qmp-usb3-phy compatible
Changes since v2:
- Drop unused qmp_v4_usb3_rx_tbl
Changes since v1:
- Provide dt bindings
- Split register ren
A plenty of DP PHY registers are common between V3 and V4. To simplify
V4 code, rename all common registers.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 50 ++---
drivers/phy/qualcomm/phy-qcom-qmp.h | 37 ++---
2 files
f5df13 ("dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy
information")
Cc: Stephen Boyd
Cc: Sandeep Maheswaram
Signed-off-by: Dmitry Baryshkov
---
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++
Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 2 --
Plug dp_phy-provided clocks to display clock controller.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index
USB1 QMP PHY is not just a USB3 PHY, but USB3+DP PHY. Change device tree
nodes accordingly.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
Add compatible for SM8250 in QMP USB3 DP PHY bindings.
Signed-off-by: Dmitry Baryshkov
---
Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
b/Documentation
Add support for QMP V4 Combo USB3+DP PHY (for SM8250 platform).
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 388 ++--
drivers/phy/qualcomm/phy-qcom-qmp.h | 40 ++-
2 files changed, 406 insertions(+), 22 deletions(-)
diff --git a/drivers
In preparation to adding support for V4 DP PHY move DP functions to
callbacks at struct qmp_phy_cfg.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 438 +++-
1 file changed, 231 insertions(+), 207 deletions(-)
diff --git a/drivers/phy/qualcomm
)
Dmitry Baryshkov (7):
dt-bindings: phy: qcom,qmp-usb3-dp-phy: move usb3 compatibles back to
qcom,qmp-phy.yaml
dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SM8250
phy: qcom-qmp: move DP functions to callbacks
phy: qcom-qmp: rename
Add compatible for SM8250 in QMP USB3 DP PHY bindings.
Signed-off-by: Dmitry Baryshkov
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
f5df13 ("dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy
information")
Cc: Stephen Boyd
Cc: Sandeep Maheswaram
Signed-off-by: Dmitry Baryshkov
Acked-by: Rob Herring
Reviewed-by: Stephen Boyd
---
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++
Documentation/devicet
A plenty of DP PHY registers are common between V3 and V4. To simplify
V4 code, rename all common registers.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 50 ++---
drivers/phy/qualcomm/phy-qcom-qmp.h | 37 ++---
2 files
In preparation to adding support for V4 DP PHY move DP functions to
callbacks at struct qmp_phy_cfg.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 438 +++-
1 file changed, 231 insertions(+), 207 deletions(-)
diff --git a/drivers/phy/qualcomm
USB1 QMP PHY is not just a USB3 PHY, but USB3+DP PHY. Change device tree
nodes accordingly.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
Add support for QMP V4 Combo USB3+DP PHY (for SM8250 platform).
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 388 ++--
drivers/phy/qualcomm/phy-qcom-qmp.h | 40 ++-
2 files changed, 406 insertions(+), 22 deletions(-)
diff --git a/drivers
Plug dp_phy-provided clocks to display clock controller.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index
On 01/04/2021 01:47, Rob Clark wrote:
On Wed, Mar 31, 2021 at 9:03 AM Dmitry Baryshkov
wrote:
On 31/03/2021 14:27, Kalyan Thota wrote:
WARN_ON was introduced by the below commit to catch runtime resumes
that are getting triggered before icc path was set.
"drm/msm/disp/dpu1: icc path
On Thu, 1 Apr 2021 at 16:19, wrote:
>
> On 2021-04-01 07:37, Dmitry Baryshkov wrote:
> > On 01/04/2021 01:47, Rob Clark wrote:
> >> On Wed, Mar 31, 2021 at 9:03 AM Dmitry Baryshkov
> >> wrote:
> >>>
> >>> On 31/03/2021 14:27, Kalyan Thota wr
On Thu, 1 Apr 2021 at 23:09, Rob Clark wrote:
>
> On Mon, Feb 22, 2021 at 8:06 AM Rob Clark wrote:
> >
> > On Mon, Feb 22, 2021 at 7:45 AM Akhil P Oommen
> > wrote:
> > >
> > > On 2/19/2021 9:30 PM, Rob Clark wrote:
> > > > On Fri, Feb 19, 2021 at 2:44 AM Akhil P Oommen
> > > > wrote:
> > > >
Add compatible for SM8250 in QMP USB3 DP PHY bindings.
Signed-off-by: Dmitry Baryshkov
---
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 -
Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 2 ++
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a
In preparation to adding support for V4 DP PHY move DP functions to
callbacks at struct qmp_phy_cfg.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 438 +++-
1 file changed, 231 insertions(+), 207 deletions(-)
diff --git a/drivers/phy/qualcomm
A plenty of DP PHY registers are common between V3 and V4. To simplify
V4 code, rename all common registers.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 50 ++---
drivers/phy/qualcomm/phy-qcom-qmp.h | 37 ++---
2 files
)
Dmitry Baryshkov (6):
dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SM8250
phy: qcom-qmp: move DP functions to callbacks
phy: qcom-qmp: rename common registers
phy: qcom-qmp: add support for sm8250-usb3-dp phy
arm64: dts: qcom: sm8250: switch usb1 qmp
Plug dp_phy-provided clocks to display clock controller.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index
Add support for QMP V4 Combo USB3+DP PHY (for SM8250 platform).
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 400 ++--
drivers/phy/qualcomm/phy-qcom-qmp.h | 40 ++-
2 files changed, 418 insertions(+), 22 deletions(-)
diff --git a/drivers
USB1 QMP PHY is not just a USB3 PHY, but USB3+DP PHY. Change device tree
nodes accordingly.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
happens.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index e6bab9960cea..9aa7793cd7c0 100644
--- a/arch/arm64/boot/dts/qcom
Qualcomm QCA639x is a family of WiFi + Bluetooth chips, with BT part
being controlled through the UART and WiFi being present on PCIe
bus. Both blocks share common power sources wich should be turned on
before either of devices can be probed. Declare common 'qca639x' driver
providing a power domain
From: Manivannan Sadhasivam
Add Bluetooth support on RB5 using the onboard QCA6391 WLAN+BT chipset.
Signed-off-by: Manivannan Sadhasivam
[DB: added qca639x power domain]
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 97
1 file changed
Qualcomm QCA639x is a family of WiFi + Bluetooth SoCs, with BT part
being controlled through the UART and WiFi being present on PCIe
bus. Both blocks share common power sources. So add mfd device driver
handling power sequencing of QCA6390/1.
Signed-off-by: Dmitry Baryshkov
---
drivers/mfd
Qualcomm QCA639x is a family of WiFi + Bluetooth SoCs, with BT part
being controlled through the UART and WiFi being present on PCIe bus.
Both blocks share common power sources. Add binding to describe power
sequencing required to power up this device.
Signed-off-by: Dmitry Baryshkov
-by: Dmitry Baryshkov
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 125 +
arch/arm64/boot/dts/qcom/sm8250.dtsi | 327 +++
2 files changed, 452 insertions(+)
--
With best wishes
Dmitry
On Sat, 13 Feb 2021 at 11:25, Greg Kroah-Hartman
wrote:
>
> On Fri, Feb 12, 2021 at 10:26:58PM +0300, Dmitry Baryshkov wrote:
> > Verify that user applications are not using the kernel RPC message
> > handle to restrict them from directly attaching to guest OS on the
> > r
On Mon, 1 Mar 2021 at 18:48, Greg Kroah-Hartman
wrote:
>
> On Mon, Mar 01, 2021 at 06:34:10PM +0300, Dmitry Baryshkov wrote:
> > On Sat, 13 Feb 2021 at 11:25, Greg Kroah-Hartman
> > wrote:
> > >
> > > On Fri, Feb 12, 2021 at 10:26:58PM +0300, Dmitry Barys
On Wed, 6 Jan 2021 at 03:09, Bjorn Andersson wrote:
>
> The PM8150 comes with everything the RTC needs, so let's just leave it
> enabled instead of having to explicitly enable it for all boards.
> In effect this patch enables the RTC on the SM8150 MTP and the SM8250
> HD
Looks good to me.
Reviewed-by: Dmitry Baryshkov
On Fri, 12 Mar 2021 at 08:28, Vinod Koul wrote:
>
> This adds the SPMI nodes for SM8350 followed by PMIC base file containing
> the GPIO nodes for these pmics (pmic compatibles have been picked by LinusW)
>
> SM8350-MTP includes
On Thu, 11 Mar 2021 at 03:10, Bjorn Andersson
wrote:
>
> On Tue 16 Feb 15:14 CST 2021, Dmitry Baryshkov wrote:
>
> > Except for the compatible value changes:
> >
> > Reviewed-by: Dmitry Baryshkov
> >
> > May I suggest to split the compatibility name chang
On 26/02/2021 01:12, Douglas Anderson wrote:
From: Stephen Boyd
Drop the old node and add the new one in its place.
Cc: Stephen Boyd
Cc: Jeykumar Sankaran
Cc: Chandan Uddaraju
Cc: Vara Reddy
Cc: Tanmay Shah
Cc: Rob Clark
Signed-off-by: Stephen Boyd
[dianders: Adjusted due to DP not itse
d-off-by: Dan Carpenter
Acked-by: Dmitry Baryshkov
--
With best wishes
Dmitry
Hello,
On Mon, 1 Mar 2021 at 13:37, wrote:
>
> On 2021-02-26 15:57, Dmitry Baryshkov wrote:
> > On Fri, 26 Feb 2021 at 09:59, wrote:
> >>
> >> Hi,
> >>
> >> On 2021-02-25 16:39, Dmitry Baryshkov wrote:
> >> > On 24/02/2021 11:33, satya
Hello,
On Fri, 1 Jan 2021 at 01:50, Rob Herring wrote:
>
> On Sun, Dec 20, 2020 at 07:58:42PM +0300, Dmitry Baryshkov wrote:
> > Qualcomm QCA639x is a family of WiFi + Bluetooth SoCs, with BT part
> > being controlled through the UART and WiFi being present on PCIe bus.
>
On 27/11/2020 20:30, Manivannan Sadhasivam wrote:
Add support for onboard MCP2518FD SPI CAN transceiver attached to SPI0
of RB5.
Signed-off-by: Manivannan Sadhasivam
Tested-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 17 +
1 file changed, 17
On 26/05/2020 06:22, Jonathan Marek wrote:
This brings up basic video mode functionality for SM8150 DPU. Command mode
and dual mixer/intf configurations are not working, future patches will
address this. Scaler functionality and multiple planes is also untested.
Signed-off-by: Jonathan Marek
--
On 30/06/2020 00:17, Jonathan Marek wrote:
This series adds the missing clock drivers and dts nodes to enable
the GPU on both SM8150 and SM8250.
Note an extra patch [1] is still required for GPU to work on SM8250.
Changes in V2:
* Added "clk: qcom: gcc: fix sm8150 GPU and NPU clocks" to fix the
On 03/07/2020 18:08, Jonathan Marek wrote:
On 7/3/20 11:03 AM, Dmitry Baryshkov wrote:
On 30/06/2020 00:17, Jonathan Marek wrote:
This series adds the missing clock drivers and dts nodes to enable
the GPU on both SM8150 and SM8250.
Note an extra patch [1] is still required for GPU to work on
On 03/07/2020 18:14, Dmitry Baryshkov wrote:
On 03/07/2020 18:08, Jonathan Marek wrote:
On 7/3/20 11:03 AM, Dmitry Baryshkov wrote:
On 30/06/2020 00:17, Jonathan Marek wrote:
This series adds the missing clock drivers and dts nodes to enable
the GPU on both SM8150 and SM8250.
Note an extra
On 24/05/2020 05:14, Jonathan Marek wrote:
The primary USB PHY on sm8250 sets some values differently for the second
lane. This makes it possible to represent that.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On 24/05/2020 05:14, Jonathan Marek wrote:
Add both the DP and UNI PHY for primary/secondary usb controllers.
The tables are very similar to sm8150 (serdes_tbl is identical), but there
are some differences.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov
--
With best wishes
On 24/05/2020 05:14, Jonathan Marek wrote:
Add support for the USB3 PHY used by the secondary usb controller on sm8150
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov
--
With best wishes
Dmitry
hes fix I2C DMA issues on SM8250 we were observing
Tested-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On 08/06/2020 23:43, Jonathan Marek wrote:
The driver may be used without slimbus, so don't depend on slimbus.
Signed-off-by: Jonathan Marek
---
drivers/soundwire/Kconfig | 1 -
drivers/soundwire/qcom.c | 5 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/soundw
On 02/09/2020 04:01, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2020-09-01 06:36:34)
With these functions I'm struggling between introducing
PHY_TYPE_DP_V3/V4 and introducing callbacks into qmp_phy_cfg. What would
you prefer?
What about the following struct?
struct qmp_phy_dp
On 03/09/2020 15:41, Jonathan Marek wrote:
On 9/3/20 8:37 AM, Dmitry Baryshkov wrote:
On 02/09/2020 04:01, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2020-09-01 06:36:34)
With these functions I'm struggling between introducing
PHY_TYPE_DP_V3/V4 and introducing callbacks into qmp_ph
c: Douglas Anderson
Cc: Sean Paul
Cc: Stephen Boyd
Cc: Jonathan Marek
Cc: Dmitry Baryshkov
Cc: Rob Clark
Link: https://lore.kernel.org/r/20200609034623.10844-1-tan...@codeaurora.org
Signed-off-by: Stephen Boyd
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 935 +---
drivers/ph
On 03/09/2020 23:43, Jonathan Marek wrote:
On 9/2/20 7:02 PM, Stephen Boyd wrote:
Add support for the USB3 + DisplayPort (DP) "combo" phy to the qmp phy
driver. We already have support for the USB3 part of the combo phy, so
most additions are for the DP phy.
Split up the qcom_qmp_phy{enable,dis
On 04/09/2020 15:44, Jonathan Marek wrote:
On 9/4/20 8:29 AM, Dmitry Baryshkov wrote:
On 03/09/2020 23:43, Jonathan Marek wrote:
On 9/2/20 7:02 PM, Stephen Boyd wrote:
Add support for the USB3 + DisplayPort (DP) "combo" phy to the qmp phy
driver. We already have support for the US
values for dp_link clk is in Hz and not kHz
On SM8250:
Tested-by: Dmitry Baryshkov
v2:
- updated dts example to reflect the change (first patch)
- updated config_ctl_hi1_val in sm8250 dispcc to latest downstream
Jonathan Marek (7):
dt-bindings: clock: sdm845-dispcc: same name for
On 04/09/2020 20:28, Jonathan Marek wrote:
Add support for SM8150 and SM8250 DSI.
Note I haven't tested SM8150 recently, but DSI is almost identical to SM8250.
On SM8250:
Tested-by: Dmitry Baryshkov
Jonathan Marek (3):
drm/msm/dsi: remove unused clk_pre/clk_post in msm_dsi_dphy_t
On 16/08/2020 01:45, Rob Clark wrote:
On Sat, Aug 15, 2020 at 2:21 PM Jonathan Marek wrote:
On 8/15/20 4:20 PM, Rob Clark wrote:
On Fri, Aug 14, 2020 at 10:05 AM Dmitry Baryshkov
wrote:
On 12/08/2020 07:42, Tanmay Shah wrote:
> From: Chandan Uddaraju
>
> Add the need
On 12/08/2020 07:42, Tanmay Shah wrote:
> From: Chandan Uddaraju
>
> Add the needed DP PLL specific files to support
> display port interface on msm targets.
[skipped]
> diff --git a/drivers/gpu/drm/msm/dp/dp_pll_private.h
b/drivers/gpu/drm/msm/dp/dp_pll_private.h
> new file mode 100644
> i
Hello,
On 12/08/2020 07:42, Tanmay Shah wrote:
From: Chandan Uddaraju
[skipped]
+ } else if ((dp_parser_check_prefix("ctrl", clk_name) ||
+ dp_parser_check_prefix("stream", clk_name)) &&
+ ctrl_clk_index < ctrl_clk_count) {
+
On 15/08/2020 02:22, Tanmay Shah wrote:
On 2020-08-14 10:05, Dmitry Baryshkov wrote:
On 12/08/2020 07:42, Tanmay Shah wrote:
From: Chandan Uddaraju
Add the needed DP PLL specific files to support
display port interface on msm targets.
[skipped]
diff --git a/drivers/gpu/drm/msm/dp
Hello,
On 04/08/2020 18:40, Rob Clark wrote:
On Thu, Jul 16, 2020 at 4:36 AM Kalyan Thota wrote:
This change adds support to scale src clk and bandwidth as
per composition requirements.
Interconnect registration for bw has been moved to mdp
device node from mdss to facilitate the scaling.
C
On SM8250 MDSS_GDSC (and the rest of display clock controller) is
supplied power by MMCX power domain. Handle this link in GDSC code by
binding the power domain in dts file.
This patchset depends on [1]
Changes since v1:
- Define fixed-regulator-domain regulator using power domain
performance
Define bindings for fixed regulator using power domain performance state
to enable/disable corresponding regulator.
Signed-off-by: Dmitry Baryshkov
---
.../bindings/regulator/fixed-regulator.yaml | 47 +++
1 file changed, 47 insertions(+)
diff --git a/Documentation/devicetree
On SM8250 MMCX power domain is required to access MMDS_GDSC registers.
This power domain is expressed as mmcx-supply regulator property. Use
this regulator as MDSS_GDSC supply.
Signed-off-by: Dmitry Baryshkov
---
drivers/clk/qcom/dispcc-sm8250.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Adds possibility to choose the compatible "fixed-regulator-domain" for
regulators which use power domain for enabling/disabling corresponding
regulator.
Signed-off-by: Dmitry Baryshkov
---
drivers/regulator/fixed.c | 63 +++
1 file changed, 57
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