From: David Daney
SRIOV BARs can be specified via EA entries. Extend the EA parser to
extract the SRIOV BAR resources, and modify sriov_init() to use
resources previously obtained via EA.
Acked-by: Sean O. Stalley
Signed-off-by: David Daney
---
drivers/pci/iov.c | 11 +--
drivers
m.com: Add more support/checking for Entry Properties,
allow EA behind bridges, rewrite some error messages.]
Signed-off-by: David Daney
---
drivers/pci/pci.c | 177
drivers/pci/pci.h | 1 +
drivers/pci/probe.c | 3 +
3 files changed, 181
From: "Sean O. Stalley"
Add registers defined in PCI-SIG's Enhanced allocation ECN.
Signed-off-by: Sean O. Stalley
[david.da...@cavium.com: Added more definitions for PCI_EA_BEI_*]
Signed-off-by: Signed-off-by: David Daney
---
include/uapi/linux/
From: David Daney
The new Enhanced Allocation (EA) capability support (patches to
follow) creates resources with the IORESOURCE_PCI_FIXED set. During
resource assignment in pci_bus_assign_resources(),
IORESOURCE_PCI_FIXED resources are not given a parent. This, in turn,
causes
From: David Daney
The new Enhanced Allocation (EA) capability support (patches to
follow) creates resources with the IORESOURCE_PCI_FIXED set. Since
these resources cannot be relocated or resized, their alignment is not
really defined, and it is therefore not specified. This causes a
problem in
this.
Your additional changes look to be correct to me, I will give them a
test within the next few days.
David Daney
Bjorn
commit 6457d085fade7d96a3aa6c5dca848fd82b4a4fa4
Author: Bjorn Helgaas
Date: Wed Oct 21 09:34:15 2015 -0500
PCI: Make Enhanced Allocation bitmasks more obvious
aarch32_el0 = false;
}
How many times in the lifetime of the kernel are these functions called?
If it is just done at startup, then there is no "steady state"
performance impact, and the burden of complicating the code may not be
worthwhile.
David Daney
static void up
From: David Daney
It is perfectly legitimate for a PCI device to have an
PCI_INTERRUPT_PIN value of zero. This happens if the device doesn't
use interrupts, or on PCIe devices, where only MSI/MSI-X are
supported.
Silence the annoying "of_irq_parse_pci() failed with rc=-19" er
ut my patches for your consideration.
Thanks,
David Daney
On 07/27/2015 01:16 AM, Marc Zyngier wrote:
On 23/07/15 17:52, Mark Rutland wrote:
Currently msi-parent is used by a few bindings to describe the
relationship between a PCI root complex and a single MSI controller, but
this property doe
On 09/04/2015 06:14 PM, Frank Rowand wrote:
On 9/4/2015 12:12 PM, David Daney wrote:
From: David Daney
It is perfectly legitimate for a PCI device to have an
PCI_INTERRUPT_PIN value of zero. This happens if the device doesn't
use interrupts, or on PCIe devices, where only MSI/MSI-
From: Thanneeru Srinivasulu
Add support for ThunderX pass2 CPI and MPI configuration changes.
MPI_ALG is not enabled i.e MCAM parsing is disabled.
Signed-off-by: Thanneeru Srinivasulu
Signed-off-by: Sunil Goutham
Signed-off-by: David Daney
---
drivers/net/ethernet/cavium/thunder/nic_main.c
From: Sunil Goutham
Signed-off-by: Sunil Goutham
Signed-off-by: David Daney
---
drivers/net/ethernet/cavium/thunder/nicvf_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_main.c
b/drivers/net/ethernet/cavium/thunder
From: Sunil Goutham
In some silicon revisions, the soft reset clobbers PCI config space,
so quit doing the reset.
Signed-off-by: Sunil Goutham
Signed-off-by: David Daney
---
drivers/net/ethernet/cavium/thunder/nic_main.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/net
From: David Daney
The test for pass-1 silicon was incorrect, it should be for all
revisions less than 8. Also the revision is already present in the
pci_dev, so there is no need to read and keep a private copy.
Remove rev_id and code to read it from struct nicpf. Create new
static inline
From: David Daney
With the availability of a new revision of the ThunderX NIC hardware a
few changes to the driver are required. With these, the driver works
on all currently available hardware revisions.
David Daney (1):
net: thunderx: Rewrite silicon revision tests.
Sunil Goutham (2
On 10/01/2015 02:24 AM, Marc Zyngier wrote:
Hi David,
On 30/09/15 23:47, David Daney wrote:
From: David Daney
Add pci_msi_domain_get_msi_rid() to return the MSI requester id (RID).
Initially needed by gic-v3 based systems. It will be used by follow on
patch to drivers/irqchip/irq-gic-v3-its
From: David Daney
The first patch from Mark Rutland adds the OF device tree binding
description, which explains what we are attempting to do here. For
MSI messages on GICv3 systems there is some side-band data that
accompanies the message, this data is specified in the OF device tree
"ms
covers msi-parent, and a new msi-map property
(specific to PCI*) which may be used to map devices (identified by their
Requester ID) to sideband data for each MSI controller that they may
target.
Acked-by: Marc Zyngier
Signed-off-by: Mark Rutland
Signed-off-by: David Daney
---
Documentation
From: David Daney
Add pci_msi_domain_get_msi_rid() to return the MSI requester id (RID).
Initially needed by gic-v3 based systems. It will be used by follow on
patch to drivers/irqchip/irq-gic-v3-its-pci-msi.c
Initially supports mapping the RID via OF device tree. In the future,
this could be
From: David Daney
The device tree property "msi-map" specifies how to create the PCI
requester id used in some MSI controllers. Add a new function
of_msi_map_rid() that finds the msi-map property and applies its
translation to a given requester id.
Reviewed-by: Marc Zyngier
Ack
From: David Daney
Replace open coded generation PCI/MSI requester id with call to the
new function pci_msi_domain_get_msi_rid() which applies the "msi-map"
to the id value.
Signed-off-by: David Daney
---
drivers/irqchip/irq-gic-v3-its-pci-msi.c | 4 +---
1 file changed, 1 inser
From: David Daney
If the bus is being configured with a bus-range that does not start at
zero, pass that starting bus number to pci_scan_root_bus(). Passing
the incorrect value of zero causes attempted config accesses outside
of the supported range, which cascades to an OOPs spew and eventual
From: David Daney
While using the pci-host-generic driver to add PCI support for the
Cavium ThunderX processors, several bugs were discovered. This patch
set fixes the bugs, a follow-on set will add the ThunderX support.
Changes from v3:
- Drop "PCI: generic: Claim device resourc
From: David Daney
If we create multiple buses with pci-host-generic, or there are buses
created by other drivers, we don't want to call pci_fixup_irqs() which
operates on all devices, not just the devices on the bus being added.
The consequence is that either the fixups are done more than
From: David Daney
pci_bus_fixup_irqs() works like pci_fixup_irqs(), except it only does
the fixups for devices on the specified bus.
Follow-on patch will use the new function.
Signed-off-by: David Daney
---
No change from v2.
drivers/pci/setup-irq.c | 30
From: David Daney
There are two problems with the bus_max calculation:
1) The u8 data type can overflow for large config space windows.
2) The calculation is incorrect for a bus range that doesn't start at
zero.
Since the configuration space is relative to bus zero, make bus_max
ju
From: David Daney
The pci-host-generic driver keeps a global struct pci_ops which it
then patches with the .map_bus method appropriate for the bus device.
A problem arises when the driver is used for two different types of
bus devices, the .map_bus method for the last device probed clobbers
the
From: David Daney
The original patches are from Sean O. Stalley. I made a few tweaks,
but feel that it is substancially Sean's work, so I am keeping the
patch set version numbering scheme going.
Tested on Cavium ThunderX system with 4 Root Complexes containing 50
devices/bridges provis
From: David Daney
PCI bridges may have their properties be specified via EA entries.
Extend the EA parser to extract the bridge resources, and modify
pci_read_bridge_{io,mmio,mmio_pref}() to use resources previously
obtained via EA.
Save the offset to the EA capability in struct pci_dev, and
m.com: Add more support/checking for Entry Properties,
allow EA behind bridges, rewrite some error messages.]
Signed-off-by: David Daney
---
drivers/pci/pci.c | 184
drivers/pci/pci.h | 1 +
drivers/pci/probe.c | 3 +
3 files changed, 188
From: David Daney
The new Enhanced Allocation (EA) capability support creates resources
with the IORESOURCE_PCI_FIXED set. This creates a couple of problems:
1) Since these resources cannot be relocated or resized, their
alignment is not really defined, and it is therefore not specified
From: "Sean O. Stalley"
Add registers defined in PCI-SIG's Enhanced allocation ECN.
Signed-off-by: Sean O. Stalley
[david.da...@cavium.com: Added more definitions for PCI_EA_BEI_*]
Signed-off-by: Signed-off-by: David Daney
---
include/uapi/linux/
From: David Daney
SRIOV BARs can be specified via EA entries. Extend the EA parser to
extract the SRIOV BAR resources, and modify sriov_init() to use
resources previously obtained via EA.
Signed-off-by: David Daney
---
drivers/pci/iov.c | 11 +--
drivers/pci/pci.c | 5 +
2 files
On 10/02/2015 04:14 PM, Yinghai Lu wrote:
On Fri, Oct 2, 2015 at 3:37 PM, David Daney wrote:
From: David Daney
The new Enhanced Allocation (EA) capability support creates resources
with the IORESOURCE_PCI_FIXED set. This creates a couple of problems:
1) Since these resources cannot be
good cleanup/simplification...
Acked-by: David Daney
---
arch/mips/kernel/watch.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/arch/mips/kernel/watch.c b/arch/mips/kernel/watch.c
index 19fcab7348b1..329d2209521d 100644
--- a/arch/mips/kernel/watch.c
On 01/02/2018 03:31 AM, Matt Redfearn wrote:
Currently the bits to be masked when watchhi is read is defined inline
for each register. To avoid this, define the bits once and mask each
register with that value.
Signed-off-by: Matt Redfearn
Acked-by: David Daney
---
arch/mips/kernel
On 12/04/2014 03:49 AM, Maciej W. Rozycki wrote:
On Wed, 3 Dec 2014, David Daney wrote:
but it doesn't support customized instructions,
GCC will never put these in the delay slot of a FPU branch, so it is not
needed.
multiple ASEs,
Same as above. But any instructions that are d
!
Some programs require an executable stack, this patch will break them.
You can only select a non-executable stack in response to PT_GNU_STACK
program headers in the ELF file of the executable program.
David Daney
---
arch/mips/include/asm/page.h |2 +-
1 file changed, 1 insertion(+), 1
On 12/05/2014 10:51 AM, Kees Cook wrote:
On Fri, Dec 5, 2014 at 9:28 AM, David Daney wrote:
On 12/02/2014 05:58 PM, Leonid Yegoshin wrote:
This is a last step of 3 patches which shift FPU emulation out of
stack into protected area. So, it disables a default executable stack.
Additionally
On 12/05/2014 11:44 AM, Christoph Lameter wrote:
On Fri, 5 Dec 2014, David Daney wrote:
The problem is not with "modern" executables that are properly annotated with
PT_GNU_STACK.
My objection is to the intentional breaking of old executables that have no
PT_GNU_STACK annotation, b
add an Acked-by me if you do that.
David Daney.
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On 01/15/2015 11:53 AM, Aaro Koskinen wrote:
Hi,
On Thu, Jan 15, 2015 at 11:36:12AM -0800, David Daney wrote:
On 01/15/2015 10:49 AM, Aaro Koskinen wrote:
octeon_cpu_disable() will unconditionally enable interrupts when called
with interrupts disabled. Fix that.
interrupts are always
On 01/19/2015 06:28 AM, Mark Rutland wrote:
Hi,
On Mon, Jan 19, 2015 at 01:46:36PM +, Aleksey Makarov wrote:
The OCTEON MMC controller is currently found on cn61XX and cnf71XX
devices. Device parameters are configured from device tree data.
Currenly supported are eMMC, MMC and SD devices.
On 01/19/2015 07:43 AM, Mark Rutland wrote:
On Mon, Jan 19, 2015 at 03:23:58PM +, Aleksey Makarov wrote:
The OCTEON SATA controller is currently found on cn71XX devices.
Signed-off-by: David Daney
Signed-off-by: Vinita Gupta
[aleksey.maka...@auriga.com: preparing for submission,
conflict
On 03/19/2015 03:35 PM, Kamal Mostafa wrote:
3.13.11-ckt17 -stable review patch. If anyone has any objections, please let
me know.
Read the patch commentary. It should only be applied to 3.17 and later.
So: NACK.
--
From: David Daney
commit
Signed-off-by: Chandrakala Chavva
Signed-off-by: David Daney
Signed-off-by: Aleksey Makarov
Signed-off-by: Leonid Rosenboim
Signed-off-by: Peter Swain
Signed-off-by: Aaron Williams
---
.../devicetree/bindings/mmc/octeon-mmc.txt | 69 +
drivers/mmc/host/Kconfig
From: David Daney
The dma_alloc_coherent() function returns a virtual address which can
be used for coherent access to the underlying memory. On some
architectures, like arm64, undefined behavior results if this memory is
also accessed via virtual mappings that are not coherent. Because of
From: David Daney
Hack up the Makefile and add support code for mips unwinding
and dwarf-regs.
Signed-off-by: David Daney
Cc: linux-m...@linux-mips.org
Cc: Jiri Olsa
Cc: linux-kernel@vger.kernel.org
Cc: Peter Zijlstra
Cc: Paul Mackerras
Cc: Ingo Molnar
Cc: Arnaldo Carvalho de Melo
From: David Daney
Define a new symbol (ARCH_SUPPORTS_LIBUNWIND) in config/Makefile.
Use this from x86 and MIPS to gate testing of libunwind.
Signed-off-by: David Daney
Cc: linux-m...@linux-mips.org
Cc: Jiri Olsa
Cc: linux-kernel@vger.kernel.org
Cc: Peter Zijlstra
Cc: Paul Mackerras
Cc: Ingo
12
either. So if it is for r6, why not require modern tools, and put
something user readable in here?
David Daney
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From: David Daney
When we have a GPIO pin connected to an open-drain network, we want a
standard way of specifying this in the device tree. So we choose bit
1 of the flag field to indicate open drain.
A typical use case would be something like:
enum of_gpio_flags f
From: David Daney
Add two new flags for open-drain and open-source GPIOs and the
corresponding handling in gpiod_get() to automatically set the
corresponding flags in the GPIO system.
Changes from v1 (suggested by Alexandre Courbot):
o Add OF_GPIO_OPEN_SOURCE
o Add automatic propagation of
From: David Daney
Just as gpiod_get() automatically interprets the OF_GPIO_ACTIVE_LOW
flag from the device tree, add handling for OF_GPIO_OPEN_DRAIN and
OF_GPIO_OPEN_SOURCE.
This keeps the details of handling open-drain GPIOs in the core GPIO
code, and out of the individual drivers.
Signed-off
From: David Daney
When we have a GPIO pin connected to an open-drain network, we want a
standard way of specifying this in the device tree. So we choose bit
1 of the flag field to indicate open drain.
A typical use case would be something like:
enum of_gpio_flags f
On 02/10/2014 08:31 PM, Alexandre Courbot wrote:
On Tue, Feb 11, 2014 at 7:05 AM, David Daney wrote:
From: David Daney
When we have a GPIO pin connected to an open-drain network, we want a
standard way of specifying this in the device tree. So we choose bit
1 of the flag field to indicate
bar=x ...
Then it wouldn't get confused by arguments that weren't directly
targeted at it.
There is precedence for this form, as it is what we already use for
built-in modules. As a bonus, we would be ready for when systemd is
integrated into the kernel as a module itself.
Thanks
On 10/16/2013 04:27 PM, Michael Bohan wrote:
Ever since the following commit, libfdt has been available for
usage in the kernel:
commit ab25383983fb8d7786696f5371e75e79c3e9a405
Author: David Daney
Date: Thu Jul 5 18:12:38 2012 +0200
of/lib: Allow scripts/dtc/libfdt
done.
It may be that the overhead of unflattening the tree and then freeing
it, is much greater than just extracting a few things from the FDT.
That said, I don't really have a preference for what is done. My
original questions were targeted at understanding this particular use case.
D
On 11/14/2013 10:45 PM, Vineet Gupta wrote:
Avoids wasting cycles at boot specially on slower simulators
Signed-off-by: Vineet Gupta
Cc: David Daney
Cc: Michal Marek
Cc: Francois Bedard
Cc: linux-kernel@vger.kernel.org
I haven't tested it, but this looks sane.
Acked-by: David Dane
iable 'usp'
[-Werror=unused-variable]
cc1: all warnings being treated as errors
Fixes: c0ff3c53d4f9 ('MIPS: Enable HAVE_ARCH_TRACEHOOK')
Signed-off-by: Guenter Roeck
Acked-by: David Daney
---
arch/mips/include/asm/syscall.h |2 +-
1 file changed, 1 insertion(+), 1 delet
xplicitly tests VM_EXEC and !VM_READ that
works.
Do you have more information about the failure, I can look at it in the
simulator and see where it goes wrong.
Thanks,
David Daney
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On 10/29/2013 02:27 PM, Laurent Navet wrote:
Mac address validity is already checked in of_get_mac_address().
No need to do it twice.
Signed-off-by: Laurent Navet
Luka already sent this exact patch, and I acked his.
No need to do it twice.
David Daney
---
drivers/net/ethernet/octeon
From: David Daney
Tested against both EdgeRouter LITE (no bootloader supplied device
tree), and ebb5610 (device tree supplied by bootloader).
The patch set is spread across both the MIPS and staging trees, so it
would be great if Ralf could merge at least the MIPS parts, if not
both parts
From: David Daney
This will be needed by the next patch to use said nodes for probing
via the device tree.
Signed-off-by: David Daney
---
.../cavium-octeon/executive/cvmx-helper-board.c| 27 ++
arch/mips/cavium-octeon/octeon-platform.c | 32
From: David Daney
Extract clocking parameters from the device tree, and remove now dead
code and types.
Signed-off-by: David Daney
---
drivers/staging/octeon-usb/octeon-hcd.c | 273 ++--
1 file changed, 116 insertions(+), 157 deletions(-)
diff --git a/drivers
/crosstool/files/bin/x86_64/4.9.0/x86_64-gcc-4.9.0-nolibc_mips64-linux.tar.xz
Could you try to at least see if it compiles?
David Daney
drivers/net/ethernet/octeon/octeon_mgmt.c | 64 +++
1 file changed, 13 insertions(+), 51 deletions(-)
diff --git a/drivers/net
instruction.
So I think shouldn't be changing this stuff unless there is a real bug
we are fixing.
In conclusion: NAK unless the patch fixes a bug, in which case the
change log *must* state what the bug is, and how the patch addresses the
problem.
David Daney
Cc: Steven Rostedt
Cc:
Shedding, I will send a patch that
clears the warning with a fewer number of changed lines, that follows
the suggestion.
David Daney
/* Read the timestamp */
- u64 ns = cvmx_read_csr(CVMX_MIXX_TSTAMP(p->port));
+ ns = c
From: David Daney
We were getting:
drivers/net/ethernet/octeon/octeon_mgmt.c:295:4: warning: ISO C90 forbids
mixed declarations and code [-Wdeclaration-after-statement]
The idea of the fix from Joe Perches.
Signed-off-by: David Daney
Cc: Heinrich Schuchardt
Cc: Joe Perches
---
This
On 09/15/2014 09:23 AM, David Daney wrote:
From: David Daney
We were getting:
drivers/net/ethernet/octeon/octeon_mgmt.c:295:4: warning: ISO C90 forbids
mixed declarations and code [-Wdeclaration-after-statement]
The idea of the fix from Joe Perches.
Signed-off-by: David Daney
Cc
wish, you can add Acked-by: me.
But I am not the maintainer of the file, so you will have to get someone
else to merge it.
David Daney
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 1ccaf91..381370d 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -14,6 +14,7
On 04/25/2014 07:21 AM, Greg KH wrote:
On Fri, Apr 25, 2014 at 10:48:22AM -0300, Nicolas Del Piano wrote:
Fixed a coding style error, macros with complex values should be enclosed in
parentheses.
Signed-off-by: Nicolas Del Piano
---
drivers/staging/octeon-usb/octeon-hcd.c |2 +-
1 file
+ linux-m...@linux-mips.org, as that is the main MIPS patch reviewing list.
On 06/20/2014 12:31 PM, Christoph Lameter wrote:
From: David Daney
The use of __this_cpu_inc() requires a fundamental integer type, so
change the type of all the counters to unsigned long, which is the
same width they
ed-by: David Daney
---
arch/mips/cavium-octeon/oct_ilm.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/mips/cavium-octeon/oct_ilm.c
b/arch/mips/cavium-octeon/oct_ilm.c
index 71b213d..2d68a39 100644
--- a/arch/mips/cavium-octeon/oct_ilm.c
+++ b/arch/mips/cavium-o
On 06/28/2014 01:34 PM, Aaro Koskinen wrote:
Hi,
The following patches add minimal support for D-Link DSR-1000N router.
Which OCTEON chip does this device contain?
Also what is the bootloader version on the board?
David Daney
USB and ethernet ports should now work with these patches.
(I
On 06/30/2014 12:17 PM, Aaro Koskinen wrote:
Hi,
On Mon, Jun 30, 2014 at 10:14:54AM -0700, David Daney wrote:
On 06/28/2014 01:34 PM, Aaro Koskinen wrote:
The following patches add minimal support for D-Link DSR-1000N router.
Which OCTEON chip does this device contain?
[0.00] CPU0
test the patch on real hardware? If so, you can add:
Acked-By: David Daney
Otherwise, somebody will have to go and test it.
Thanks,
David Daney
---
drivers/ata/pata_octeon_cf.c |9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
Index: b/drivers/ata/pata_octeon_cf.c
On 05/29/2014 02:54 PM, abdoulaye berthe wrote:
Did you forget a changelog explaining why this is either needed, or even
a good idea? I joined the conversation late and don't know why you are
doing this.
Thanks,
David Daney
Signed-off-by: abdoulaye berthe
---
arch/arm/common/sc
("gpio: removing gpiochip with gpios still
requested\n");
panic?
NACK to the patch for this reason. The strongest thing you should do
here is WARN.
That said, I am not sure why we need this whole patch set in the first
place.
David Daney
Is this likely to happen?
Gr{o
cro-architecture. I have not done any exhaustive testing Transitivity
principle with respect to SYNCW/LL/SC as described above.
David Daney
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ctl_table
security:keys: Convert use of typedef ctl_table to struct ctl_table
After all this work, why not go ahead and remove the typedef? That way
people won't add more users of this abomination.
David Daney
arch/arm/kernel/isa.c | 6 ++---
arch/ia64/kernel/cr
On 12/19/2013 07:50 AM, Christoph Lameter wrote:
[Patch depends on another patch in this series that introduces raw_cpu_ops]
We define a check function in order to avoid trouble with the
include files. Then the higher level __this_cpu macros are
modified to invoke the preemption check.
Acked-by
On 12/19/2013 07:50 AM, Christoph Lameter wrote:
[...]
Cc: Ralf Baechle
Signed-off-by: Christoph Lameter
Index: linux/arch/mips/include/asm/fpu_emulator.h
===
--- linux.orig/arch/mips/include/asm/fpu_emulator.h 2013-12-02
16:
On 12/19/2013 01:10 PM, Christoph Lameter wrote:
On Thu, 19 Dec 2013, David Daney wrote:
16:07:58.244398747 -0600
@@ -43,7 +43,7 @@ DECLARE_PER_CPU(struct mips_fpu_emulator
#define MIPS_FPU_EMU_INC_STATS(M)\
do {
\
preempt_disable
ed by AARCH64 commit:
"arm64: extable: sort the exception table at build time"
(sha1: adace89562c7a9645b8dc84f6e1ac7ba8756094e)
Signed-off-by: Michal Simek
This seems plausible, I didn't test it, but this is how it is supposed
to work, so...
Acked-by: David Daney
---
arc
On 08/22/2014 01:42 PM, Florian Fainelli wrote:
On Aug 21, 2014 3:05 PM, "Andrew Bresticker" mailto:abres...@chromium.org>> wrote:
>
> To be consistent with other architectures and to avoid unnecessary
> makefile duplication, move all MIPS device-trees to arch/mips/boot/dts
> and build them w
runs just fine with a
larger page size.
David Daney
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On 08/25/2014 07:41 PM, Joshua Kinard wrote:
On 08/25/2014 20:36, David Daney wrote:
On 08/25/2014 04:55 PM, Joshua Kinard wrote:
On 08/25/2014 13:16, Ralf Baechle wrote:
On Sat, Aug 02, 2014 at 05:11:37AM +0400, Max Filippov wrote:
this series adds mapping color control to the generic kmap
C vendor. That would result in
the following structure (I think):
Octeon -> cavium/
To match the state of the art naming we have in other MIPS related
directories, it should probably be "cavium-octeon/" (See
arch/mips/cavium-octeon, and arch/mips/include/asm/mach-cavium-octeon)
David
On 09/03/2014 04:53 PM, Andrew Bresticker wrote:
On Tue, Sep 2, 2014 at 5:50 PM, David Daney wrote:
[...]
Your comments don't really make sense to me in the context of my knowledge
of the GIC.
Of course all the CP0 timer and performance counter interrupts are per-CPU
and routed direct
On 08/29/2014 03:14 PM, Andrew Bresticker wrote:
The Global Interrupt Controller (GIC) present on certain MIPS systems
can be used to route external interrupts to individual VPEs and CPU
interrupt vectors. It also supports a timer and software-generated
interrupts.
Signed-off-by: Andrew Brestic
On 09/02/2014 12:36 PM, Andrew Bresticker wrote:
On Tue, Sep 2, 2014 at 10:27 AM, David Daney wrote:
On 08/29/2014 03:14 PM, Andrew Bresticker wrote:
The Global Interrupt Controller (GIC) present on certain MIPS systems
can be used to route external interrupts to individual VPEs and CPU
On 08/07/2014 04:48 AM, Ralf Baechle wrote:
On Tue, Aug 05, 2014 at 01:37:47PM +0800, wei.y...@windriver.com wrote:
From: Yang Wei
In RT kernel, I ran into the following calltrace, so PMU interrupts cannot
be threaded
in_atomic(): 1, irqs_disabled(): 1, pid: 0, name: swapper/0
INFO: lockdep
o prepare for smoothing set_cpu_[active|online]() mess up
Signed-off-by: Yong Zhang
Cc: Sergei Shtylyov
Cc: David Daney
Acked-by: David Daney
Patchwork: https://patchwork.linux-mips.org/patch/3845/
Signed-off-by: Ralf Baechle
Why are you sending it again?
David Daney
On 08/11/2014 03:33 PM, Sadasivan Shaiju wrote:
Hi David,
Sorry , I didn't check that . I am late in submitting it .
OK. Next time try to apply your patch and test it before submitting.
David Daney
Regards,
Shaiju.
-Original Message-
From: David Daney [mailt
e.
Isn't this a program that would run on the target, not the build host?
David Daney
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Ple
lb_mm(), and
invalidates the TLBs on all CPUs. How does the TLB entry for the
special mapping survive this?
David Daney
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From: David Daney
In order for MIPS to be able to support a non-executable stack, we
need to supply a method to specify a userspace area that can be used
for executing emulated branch delay slot instructions.
We add a new system call, sys_set_fpuemul_xol_area so that userspace
threads that are
From: David Daney
In order for MIPS to be able to support a non-executable stack, we
need to supply a method to specify a userspace area that can be used
for executing emulated branch delay slot instructions.
We add a new system call, sys_set_fpuemul_xol_area so that userspace
threads that are
On 10/06/2014 01:54 PM, Rich Felker wrote:
On Mon, Oct 06, 2014 at 01:23:30PM -0700, David Daney wrote:
From: David Daney
In order for MIPS to be able to support a non-executable stack, we
need to supply a method to specify a userspace area that can be used
for executing emulated branch delay
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