Hi!
On Tue, Mar 12, 2019 at 4:59 PM Neil Armstrong wrote:
> [...]
> BTW, do you know if it's possible to have a sample of the Phicomm N1
> in order to be added in kernelci ?
It's easy to purchase one in China and second-handed ones are dirt
cheap, but I don't think it's available worldwide.
I'm no
Hi!
On Wed, Mar 13, 2019 at 8:28 PM Matthias Brugger wrote:
>
>
>
> On 13/03/2019 13:24, Armando Miraglia wrote:
> [...]
> Apart from fixing styling issues it would be usefull to see if we can add
> support for mt7621 to drivers/spi/spi-mt65xx.c
It's impossible. They are completely different IPs.
n fixed by my two "drop broken spi modes" patches.
>
> John: do you have any more details of the problem other than what is in
> the commit message?
>
> Thanks,
> NeilBrown
Regards,
Chuanhong Guo
belong to this switch at all and I think this
approach should not be followed further by future code.
The usage of mac5 should be explicitly defined as a dt property
under mt753x node.
--
Regards,
Chuanhong Guo
k design of mt7621 doesn't seem
to be part of ralink legacy stuff, and ralink is already
acquired by mediatek anyway.
I think it should be put in drivers/clk/mediatek instead.
--
Regards,
Chuanhong Guo
er you are working on.
[0]:
https://github.com/hackpascal/lede-rtl8196c/blob/realtek/target/linux/realtek/files/drivers/spi/spi-realtek.c
--
Regards,
Chuanhong Guo
d 500MHz clock or a clock created by the memory controller.
sysctl contains a bootstrap register to determine crystal clock, a
clock mux for choosing between the 3 sources for CPU clock, and
a clock gate register for various peripherals. The ralink,memctl
phandle here is to read the cpu clock frequency from the memory
controller.
The original implementation hides this hardware detail to avoid
splitting the driver into three just for the CPU clock.
Is this approach okay and we can put it under sysctl node,
or this driver needs to be further splitted?
--
Regards,
Chuanhong Guo
R
If that's true, this is a generic half-duplex spi controller, and the driver
should register a spi_controller with set_cs and transfer_one
implemented.
--
Regards,
Chuanhong Guo
an't determine corresponding clock frequencies for every
peripherals, thus unable to write a working clock driver.
>
> > +
> > + #clock-cells = <1>;
> > + clock-output-names = "cpu", "bus";
> > + };
> > --
> > 2.21.0
> >
Regards,
Chuanhong Guo
[0]
https://elixir.bootlin.com/linux/latest/source/arch/mips/ralink/mt7621.c#L156
ks are there since this piece
of info is missing in datasheet.
>
> IMO - this information is enough to create full blown
> drivers/clk/mediatek/clk-mt7621.c
And this information isn't enough because the assumption above is incorrect :P
Regards,
Chuanhong Guo
hardcoded clocks. With this driver will work part of power
> management and nice devicetree without fixed clocks.
Regards,
Chuanhong Guo
Clock gate is an unrelated part and there is no information to
properly implement it unless MTK decided to release a clock plan
somehow.
> This code is currently on prototyping phase
Code for clock calculation is done, not "prototyping".
> It means, we cannot expect that this driver will be fixed any time soon.
I think clock gating is a separated feature instead of a broken part
that has to be fixed.
Regards,
Chuanhong Guo
Hi!
On Sun, Aug 18, 2019 at 3:59 PM Oleksij Rempel wrote:
>
> Am 18.08.19 um 09:19 schrieb Chuanhong Guo:
> > Hi!
> >
> > On Sun, Aug 18, 2019 at 2:10 PM Oleksij Rempel
> > wrote:
> >>
> >>>> We have at least 2 know registers:
> >&g
On Sun, Aug 18, 2019 at 4:26 PM Chuanhong Guo wrote:
>
> Hi!
>
> On Sun, Aug 18, 2019 at 3:59 PM Oleksij Rempel wrote:
> >
> > Am 18.08.19 um 09:19 schrieb Chuanhong Guo:
> > > Hi!
> > >
> > > On Sun, Aug 18, 2019 at 2:10 PM Oleksij Rempel
&
ade my
> > point. Of course I can't read through the ancient and heavily hacked
> > vendor kernel to figure out a clock plan myself.
>
> Ok, I provided you some productive technical hints how it should be
> done. I don't think mt7620 has better documentation then mt7621 and even
> in this case it was possible to make more or less good driver.
It does. A clock plan for mt7620 is available in MT7620 Programming
Guide, Page 14.
Regards,
Chuanhong Guo
to better explain what's happening.
Fixes: cfd93d7c908e ("mtd: spinand: Add support for GigaDevice GD5F1GQ4UFxxG")
Signed-off-by: Chuanhong Guo
CC: Jeff Kletsky
---
RFC:
I doubt whether this patch is a proper fix for the underlying problem:
The actual problem is that we have two
pidev_to_mt7621_spi(spi);
>
> if ((spi->max_speed_hz == 0) ||
> - (spi->max_speed_hz > (rs->sys_freq / 2)))
> + (spi->max_speed_hz > (rs->sys_freq / 2)))
> spi->max_speed_hz = (rs->sys_freq / 2);
>
> if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
> --
> 2.20.1
>
Regards,
Chuanhong Guo
This function isn't called anywhere. just drop it.
Signed-off-by: Chuanhong Guo
---
Change since v1:
New patch. Split from:
"MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices"
arch/mips/ralink/mt7621.c | 43 ---
1 file change
This patch adds dt binding header for mediatek,mt7621-pll
Signed-off-by: Weijie Gao
Signed-off-by: Chuanhong Guo
Reviewed-by: Rob Herring
---
Change since v1:
Change commit title prefix.
include/dt-bindings/clock/mt7621-clk.h | 14 ++
1 file changed, 14 insertions(+)
create mode
This commit adds device-tree node for mt7621-pll and use its clocks
accordingly.
Signed-off-by: Chuanhong Guo
---
Changes since v1:
1. drop cpuclock node in gbpc1.dts
2. drop syscon in mt7621-pll node
drivers/staging/mt7621-dts/gbpc1.dts | 5 -
drivers/staging/mt7621-dts/mt7621.dtsi
: Weijie Gao
Signed-off-by: Chuanhong Guo
---
Changes since v1:
1. split patch.
2. calculate clocks using the function called by CLK_OF_DECLARE
drop direct function call in timer-gic.c of ralink_clk_init
3. drop assignment of mips-hpt-frequency
arch/mips/include/asm/mach-ralink/mt7621.h | 20
l and used it in mt7621-dts at
drivers/staging.
Changes since v1:
1. changed commit title prefix for dt include
2. split the patch adding clock node (details in that patch body)
3. drop useless syscon in dt documentation
4. drop cpuclock node for gbpc1
Chuanhong Guo (6):
dt-bindings: clock: a
The memc node from mt7621.dtsi has incorrect register resource.
Fix it according to the programming guide.
Signed-off-by: Weijie Gao
Signed-off-by: Chuanhong Guo
---
Change since v1: None.
drivers/staging/mt7621-dts/mt7621.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
This commit adds device tree binding documentation for MT7621
PLL controller.
Signed-off-by: Chuanhong Guo
---
Change since v1:
drop useless syscon in compatible string
.../bindings/clock/mediatek,mt7621-pll.txt | 18 ++
1 file changed, 18 insertions(+)
create mode 100644
l and used it in mt7621-dts at
drivers/staging.
BTW: What should I do with such a patchset that touches multiple
parts in kernel?
Is it correct to send the entire patchset to lists of all involved
subsystems?
Chuanhong Guo (5):
MIPS: ralink: add dt binding header for mt7621-pll
MIPS: ralink: fi
This patch adds dt binding header for mediatek,mt7621-pll
Signed-off-by: Weijie Gao
Signed-off-by: Chuanhong Guo
Reviewed-by: Rob Herring
---
include/dt-bindings/clock/mt7621-clk.h | 14 ++
1 file changed, 14 insertions(+)
create mode 100644 include/dt-bindings/clock/mt7621-clk.h
This commit adds device-tree node for mt7621-pll and use its clock
accordingly.
Signed-off-by: Chuanhong Guo
---
drivers/staging/mt7621-dts/mt7621.dtsi | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi
b/drivers/staging
This commit adds device tree binding documentation for MT7621
PLL controller.
Signed-off-by: Chuanhong Guo
---
.../bindings/clock/mediatek,mt7621-pll.txt| 19 +++
1 file changed, 19 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/mediatek,mt7621
The memc node from mt7621.dtsi has incorrect register resource.
Fix it according to the programming guide.
Signed-off-by: Weijie Gao
Signed-off-by: Chuanhong Guo
---
drivers/staging/mt7621-dts/mt7621.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging
Signed-off-by: Weijie Gao
Signed-off-by: Chuanhong Guo
---
arch/mips/include/asm/mach-ralink/mt7621.h | 20
arch/mips/ralink/mt7621.c | 102 ++---
arch/mips/ralink/timer-gic.c | 4 +-
3 files changed, 93 insertions(+), 33 deletions(-)
diff
On Wed, Jul 10, 2019 at 2:22 AM Chuanhong Guo wrote:
>
> This commit adds device-tree node for mt7621-pll and use its clock
> accordingly.
>
> Signed-off-by: Chuanhong Guo
Oops. Please ignore this single patch for now. I forgot to drop
cpuclock node in drivers/staging/mt7621-dts
There is a white LED on the front panel behind the logo and the
manufacturer uses that LED to indicate network and USB drive status.
Signed-off-by: Chuanhong Guo
---
.../boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts| 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64
which will be used in dts.
Signed-off-by: Weijie Gao
Ported from OpenWrt:
c7ca224299 ramips: fix cpu clock of mt7621 and add dt clk devices
Signed-off-by: Chuanhong Guo
---
arch/mips/include/asm/mach-ralink/mt7621.h | 20
arch/mips/ralink/mt7621.c | 102
mt7621 and add dt clk devices
Signed-off-by: Chuanhong Guo
---
Resend due to incorrect patch subject.
arch/mips/include/asm/mach-ralink/mt7621.h | 20
arch/mips/ralink/mt7621.c | 102 ++---
arch/mips/ralink/timer-gic.c | 4 +-
3 files changed
mt7621 and add dt clk devices
Signed-off-by: Chuanhong Guo
---
Change since v1:
Correctly fix the following checkpatch.pl warning:
WARNING: Missing a blank line after declarations
#137: FILE: arch/mips/ralink/mt7621.c:146:
+ u32 xtal_clk, cpu_clk, bus_clk;
+ const static u32 prediv_tbl
Some of these ralink devices come with an ancient u-boot which can't
extract LZMA properly when image gets too big.
Enable zboot support to get a self-extracting kernel instead of relying
on broken u-boot support.
Signed-off-by: Chuanhong Guo
---
arch/mips/Kconfig | 1 +
1 file chang
uartlite0 at 0x1e000c00 is a 16550 compatible uart controller. It's
usually used for debug console and is already configured by u-boot.
Add ZBOOT_UART16550 and related definitions in uart-16550.c for zboot
debug output.
Signed-off-by: Chuanhong Guo
---
arch/mips/boot/compressed/uart-16550.
Signed-off-by: Chuanhong Guo
---
Note:
This should supersede this patch on linux-mips:
[2/2] mips: boot compressed: add support for vlinuz ELF DTB [0]
[0]
https://patchwork.kernel.org/project/linux-mips/patch/20201015201100.4130-2-...@johnthomson.fastmail.com.au/
arch/mips/boot/compressed
; - "pcie0": "ahb"
> - "pcie1": "ahb"
> - "pcie2": "ahb"
> - "crypto": "ahb"
> - "shxc": "ahb"
>
> There was a previous attempt of doing this here[0] but the author
> did not wanted to make assumptions of a clock plan for the platform.
I've already said in previous threads that clock assignment in
current linux kernel is not trustworthy.
I've got the clock plan for mt7621 now. (Can't share it, sorry.)
Most of your clock assumptions above are incorrect.
I've made a clock driver with gate support a few months ago.[0]
but I don't have much time to really finish it.
Maybe you could rework your clock gate driver based on it.
[0]
https://github.com/981213/linux/commit/2eca1f045e4c3db18c941135464c0d7422ad8133
--
Regards,
Chuanhong Guo
On Thu, Nov 12, 2020 at 9:26 AM Chuanhong Guo wrote:
>
> I've already said in previous threads that clock assignment in
> current linux kernel is not trustworthy.
> I've got the clock plan for mt7621 now. (Can't share it, sorry.)
> Most of your clock assumptions abov
ing auto
clock gating.
--
Regards,
Chuanhong Guo
roller can trigger longer data shifting with
shift bytes more than PRGDATA_MAX + SHREG_MAX. This patch is implemented
with that in mind and it checks against both SHREG_MAX and PRG_CNT_MAX
for future support of new controllers.
Signed-off-by: Chuanhong Guo
---
There are two calls of mtk_nor_spi_
upport standard spi properties")
which breaks supports_op logic. But it can't be separated as it depends
on patch 2/3. Fortuantely the broken commit isn't in stable yet.
Chuanhong Guo (3):
spi: spi-mtk-nor: make use of full capability of prg mode
spi: spi-mtk-nor: add helper f
ck the left ops against controller program mode.
Fixes: a59b2c7c56bf7 ("spi: spi-mtk-nor: support standard spi properties")
Signed-off-by: Chuanhong Guo
---
drivers/spi/spi-mtk-nor.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/spi/sp
cause supports_op is currently
broken. It'll be used in the next fix commit.
Signed-off-by: Chuanhong Guo
---
drivers/spi/spi-mtk-nor.c | 76 +++
1 file changed, 69 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-mtk-nor.c b/drivers/spi/spi-mtk-n
for (i = 0; i < t->len; i++, reg_offset--) {
> - reg = sp->base + MTK_NOR_REG_SHIFT(reg_offset);
> - if (rxbuf)
> + if (rx_len > 0) {
> + reg_offset = rx_len - 1;
> + list_for_each_entry(t, &m->transfers, transfer_list) {
> + u8 *rxbuf = t->rx_buf;
> +
> + if (!rxbuf)
> + continue;
> +
> + for (i = 0; i < t->len && reg_offset >= 0; i++,
> reg_offset--) {
> + reg = sp->base +
> MTK_NOR_REG_SHIFT(reg_offset);
> rxbuf[i] = readb(reg);
> + }
I think this is replacing original code with some equivalent ones, which
seems unnecessary.
> }
> }
>
--
Regards,
Chuanhong Guo
SPI_MEM_DATA_IN)
> + return ((len + op->data.nbytes) <= MTK_NOR_PRG_MAX_CYCLES);
You need to consider the existence of adjust_op_size in supports_op as well.
This mtk_nor_check_prg still rejects SFDP reading command from spi-nor
driver altogether.
--
Regards,
Chuanhong Guo
oned here.
>
> Signed-off-by: Ikjoon Jang
>
> ---
>
> (no changes since v1)
There have been a lot of changes since v2 :)
Reviewed-by: Chuanhong Guo
--
Regards,
Chuanhong Guo
writel(dma_addr >> 32, sp->base + MTK_NOR_REG_DMA_DADR_HB);
> + writel((dma_addr + length) >> 32, sp->base +
> MTK_NOR_REG_DMA_END_DADR_HB);
> + }
I remembered kbuild test robot reported a warning on this on 32-bit platforms
in your v1. [0]
I don't know what's the fix for this though :(
[0] https://marc.info/?l=linux-spi&m=159982425706940&w=2
--
Regards,
Chuanhong Guo
em *mem,
> default:
> break;
> }
> + } else {
> + u8 len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
> +
> + if (len > MTK_NOR_PRG_MAX_SIZE)
> + return false;
> + if (op->data.nbytes && !(MTK_NOR_PRG_MAX_SIZE - len))
> + return false;
> }
> - len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
> - if ((len > MTK_NOR_PRG_MAX_SIZE) ||
> - ((op->data.nbytes) && (len == MTK_NOR_PRG_MAX_SIZE)))
> - return false;
>
> return spi_mem_default_supports_op(mem, op);
> }
> --
> 2.28.0.681.g6f77f65b4e-goog
>
--
Regards,
Chuanhong Guo
tic int mtk_nor_probe(struct platform_device *pdev)
> ret = mtk_nor_init(sp);
> if (ret < 0) {
> kfree(ctlr);
> + dma_free_coherent(&pdev->dev, MTK_NOR_BOUNCE_BUF_SIZE,
> + sp->buffer, sp->buffer_dma);
> return ret;
> }
>
> @@ -692,6 +700,8 @@ static int mtk_nor_remove(struct platform_device *pdev)
>
> mtk_nor_disable_clk(sp);
>
> + dma_free_coherent(&pdev->dev, MTK_NOR_BOUNCE_BUF_SIZE,
> + sp->buffer, sp->buffer_dma);
> return 0;
> }
>
> --
> 2.28.0.681.g6f77f65b4e-goog
>
--
Regards,
Chuanhong Guo
Hi!
On Fri, Sep 18, 2020 at 9:09 PM Chuanhong Guo wrote:
> On Fri, Sep 18, 2020 at 4:34 PM Ikjoon Jang wrote:
> > [...]
> > + switch (op->data.dir) {
> > + case SPI_MEM_DATA_IN:
> > +
. add a 4M transfer size cap so that the final timeout in DMA reading
doesn't overflow
Fixes: 881d1ee9fe81f ("spi: add support for mediatek spi-nor controller")
Cc:
Signed-off-by: Chuanhong Guo
---
drivers/spi/spi-mtk-nor.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-
On Tue, Sep 22, 2020 at 7:43 PM Chuanhong Guo wrote:
>
> CLK_TO_US macro is used to calculate potential transfer time for various
> timeout handling. However it overflows on transfer bigger than 512 bytes
> because it first did (len * 8 * 100).
> This controller typically op
. add a 4M transfer size cap so that the final timeout in DMA reading
doesn't overflow
Fixes: 881d1ee9fe81f ("spi: add support for mediatek spi-nor controller")
Cc:
Signed-off-by: Chuanhong Guo
---
Change since v1: fix transfer size cap to 4M
drivers/spi/spi-mtk-nor.c | 6 +-
Hi!
On Tue, Sep 22, 2020 at 8:02 PM Mark Brown wrote:
>
> On Tue, Sep 22, 2020 at 07:49:02PM +0800, Chuanhong Guo wrote:
>
> > if ((op->data.dir == SPI_MEM_DATA_IN) &&
> > mtk_nor_match_read(op)) {
> > +
f no custom adjust_op_size hook is defined in the driver. If a custom
adjust_op_size is defined, the driver adjusts the transfer size for it's
exec_op hook. The size limit between exec_op and transfer_one_message
can be different. (this spi-mtk-nor is an example of that.)
--
Regards,
Chuanhong Guo
These pins are named ANTSEL[0~29] in datasheet and are used by wmac for
various functions.
Signed-off-by: Chuanhong Guo
---
drivers/pinctrl/mediatek/pinctrl-mt7622.c | 103 ++
1 file changed, 103 insertions(+)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
b
times before giving up.
Signed-off-by: Chuanhong Guo
---
On my mt7622 board mt7615_load_patch always fails the first time
and it then succeeded on the first retry added by this patch.
"10 times" is an arbitarily picked value and it'll still leave a
broken phy behind if all 10 retries
This patch adds dt binding header for mediatek,mt7621-pll which
was added in:
commit e6046b5e69a0 ("MIPS: ralink: fix cpu clock of mt7621 and add dt clk
devices")
Signed-off-by: Weijie Gao
Signed-off-by: Chuanhong Guo
---
checkpatch.pl shows a warning that the line referencing old
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