On Fri, 2020-11-20 at 19:17 +0800, Jisheng Zhang wrote:
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> We have removed the dw_pcie_ops always exists assumption i
On Tue, 2019-08-20 at 20:54 +0100, Andrew Murray wrote:
> On Tue, Aug 20, 2019 at 05:06:22PM +0000, Chocron, Jonathan wrote:
> > On Tue, 2019-08-20 at 16:25 +0100, Andrew Murray wrote:
> > > On Tue, Aug 20, 2019 at 02:52:30PM +, Chocron, Jonathan
> > > wrote:
>
On Thu, 2019-08-22 at 12:41 +0100, Andrew Murray wrote:
> On Wed, Aug 21, 2019 at 06:35:43PM +0300, Jonathan Chocron wrote:
> > The Amazon Annapurna Labs PCIe Root Port exposes the VPD
> > capability,
> > but there is no actual support for it.
> >
> > The reason for not using the already existing
On Thu, 2019-08-22 at 11:00 +0100, Andrew Murray wrote:
> On Wed, Aug 21, 2019 at 06:47:44PM +0300, Jonathan Chocron wrote:
> > This driver is DT based and utilizes the DesignWare APIs.
> >
> > It allows using a smaller ECAM range for a larger bus range -
> > usually an entire bus uses 1MB of addr
On Thu, 2019-08-22 at 12:13 +0100, Andrew Murray wrote:
> On Wed, Aug 21, 2019 at 06:47:45PM +0300, Jonathan Chocron wrote:
> > Some PCIe controllers can be set to either Host or EP according to
> > some
> > early boot FW. To make sure there is no discrepancy (e.g. FW
> > configured
> > the port to
On Thu, 2019-08-22 at 09:31 +0100, Andrew Murray wrote:
> On Wed, Aug 21, 2019 at 06:35:42PM +0300, Jonathan Chocron wrote:
> > From: Ali Saidi
> >
> > The Amazon's Annapurna Labs root ports don't advertise an ACS
> > capability, but they don't allow peer-to-peer transactions and do
> > validate
On Thu, 2019-08-22 at 16:07 +0100, Andrew Murray wrote:
> On Thu, Aug 22, 2019 at 02:36:24PM +0000, Chocron, Jonathan wrote:
> > On Thu, 2019-08-22 at 12:41 +0100, Andrew Murray wrote:
> > > On Wed, Aug 21, 2019 at 06:35:43PM +0300, Jonathan Chocron wrote:
> > > >
On Tue, 2019-08-27 at 10:48 +0100, Andrew Murray wrote:
> On Thu, Aug 22, 2019 at 04:30:09PM +0000, Chocron, Jonathan wrote:
> > On Thu, 2019-08-22 at 12:13 +0100, Andrew Murray wrote:
> > > On Wed, Aug 21, 2019 at 06:47:45PM +0300, Jonathan Chocron wrote:
> > > > So
On Mon, 2019-09-02 at 10:58 +0100, Lorenzo Pieralisi wrote:
> On Wed, Aug 21, 2019 at 06:35:40PM +0300, Jonathan Chocron wrote:
> > This series adds support for Amazon's Annapurna Labs DT-based PCIe
> > host
> > controller driver.
> > Additionally, it adds 3 quirks (ACS, VPD and MSI-X) and 2 generi
On Sat, 2019-09-07 at 11:54 -0500, Bjorn Helgaas wrote:
> On Thu, Sep 05, 2019 at 05:00:16PM +0300, Jonathan Chocron wrote:
> > From: Ali Saidi
> >
> > The Amazon's Annapurna Labs root ports don't advertise an ACS
> > capability, but they don't allow peer-to-peer transactions and do
> > validate
On Sat, 2019-09-07 at 11:55 -0500, Bjorn Helgaas wrote:
> On Thu, Sep 05, 2019 at 05:00:17PM +0300, Jonathan Chocron wrote:
> > The Amazon Annapurna Labs PCIe Root Port exposes the VPD
> > capability,
> > but there is no actual support for it.
>
> Oops. Another oops for the device ID reuse mentio
On Sat, 2019-09-07 at 11:55 -0500, Bjorn Helgaas wrote:
> s/Add quirk to disable/Disable/ in subject
>
> On Thu, Sep 05, 2019 at 05:00:18PM +0300, Jonathan Chocron wrote:
> > The Root Port (identified by [1c36:0031]) doesn't support MSI-X. On
> > some
> > platforms it is configured to not advertis
On Sat, 2019-09-07 at 11:55 -0500, Bjorn Helgaas wrote:
> s/Add support for DW based driver type/Add Amazon Annapurna Labs PCIe
> controller driver/
>
Ack.
> On Thu, Sep 05, 2019 at 05:01:43PM +0300, Jonathan Chocron wrote:
> > This driver is DT based and utilizes the DesignWare APIs.
> >
> > It
On Tue, 2019-08-13 at 14:46 -0600, Rob Herring wrote:
> On Tue, Aug 13, 2019 at 10:49 AM Chocron, Jonathan > wrote:
> >
> > On Tue, 2019-08-13 at 09:30 -0600, Rob Herring wrote:
> > > On Tue, Jul 23, 2019 at 12:27:08PM +0300, Jonathan Chocron wrote:
> > > >
On Mon, 2019-08-19 at 19:23 +0100, Andrew Murray wrote:
> On Tue, Jul 23, 2019 at 12:25:29PM +0300, Jonathan Chocron wrote:
> > The Root Port (identified by [1c36:0032]) doesn't support MSI-X. On
> > some
>
> Shouldn't this read [1c36:0031]?
>
Indeed. Thanks for catching this.
>
> > platforms i
On Tue, 2019-08-20 at 16:25 +0100, Andrew Murray wrote:
> On Tue, Aug 20, 2019 at 02:52:30PM +0000, Chocron, Jonathan wrote:
> > On Mon, 2019-08-19 at 19:23 +0100, Andrew Murray wrote:
> > > On Tue, Jul 23, 2019 at 12:25:29PM +0300, Jonathan Chocron wrote:
> > > >
On Fri, 2019-07-12 at 08:42 -0500, Bjorn Helgaas wrote:
> On Thu, Jul 11, 2019 at 05:57:05PM +0300, Jonathan Chocron wrote:
> > This driver is DT based and utilizes the DesignWare APIs.
> > It allows using a smaller ECAM range for a larger bus range -
> > usually an entire bus uses 1MB of address s
On Thu, 2019-07-11 at 10:32 +0100, Lorenzo Pieralisi wrote:
> On Thu, Jul 11, 2019 at 10:12:35AM +0300, Shenhar, Talel wrote:
> >
> > On 7/10/2019 7:45 PM, Jonathan Chocron wrote:
> > > Document Amazon's Annapurna Labs PCIe host bridge.
> >
> > That is the way! (best to keep same wordings (Amazon
On Fri, 2019-07-12 at 08:10 -0500, Bjorn Helgaas wrote:
> On Thu, Jul 11, 2019 at 05:55:56PM +0300, Jonathan Chocron wrote:
> > The Amazon Annapurna Labs pcie host bridge exposes the VPD
> > capability,
> > but there is no actual support for it.
>
> s/pcie/PCIe/
> s/host bridge/Root Port/
Ack.
>
On Fri, 2019-07-12 at 08:04 -0500, Bjorn Helgaas wrote:
> On Thu, Jul 11, 2019 at 05:56:25PM +0300, Jonathan Chocron wrote:
> > On some platforms, the host bridge exposes an MSI-X capability but
> > doesn't actually support it.
> > This causes a crash during initialization by the pcieport driver,
>
2019 at 09:30:05AM +, Chocron, Jonathan wrote:
> > On Wed, 2019-08-07 at 17:36 +0100, Lorenzo Pieralisi wrote:
> > > On Tue, Jul 23, 2019 at 12:27:11PM +0300, Jonathan Chocron wrote:
> > > > This basically aligns the usage of PCI_PROBE_ONLY and
> > > >
On Tue, 2019-08-13 at 09:30 -0600, Rob Herring wrote:
> On Tue, Jul 23, 2019 at 12:27:08PM +0300, Jonathan Chocron wrote:
> > Document Amazon's Annapurna Labs PCIe host bridge.
> >
> > Signed-off-by: Jonathan Chocron
> > ---
> > .../devicetree/bindings/pci/pcie-al.txt | 45
> >
On Mon, 2019-08-12 at 18:03 +0100, Lorenzo Pieralisi wrote:
> "PCI: dwc: al: Add support for DW based driver type"
>
> Make $SUBJECT compliant with other host controllers patches.
>
Will do.
BTW,I actually see that many of the other dwc controllers don't have
the 'dwc:' (and some are inconsisten
On Wed, 2019-08-07 at 17:36 +0100, Lorenzo Pieralisi wrote:
> On Tue, Jul 23, 2019 at 12:27:11PM +0300, Jonathan Chocron wrote:
> > This basically aligns the usage of PCI_PROBE_ONLY and
> > PCI_REASSIGN_ALL_BUS in dw_pcie_host_init() with the logic in
> > pci_host_common_probe().
> >
> > Now it wi
On Fri, 2019-07-19 at 08:55 +, Gustavo Pimentel wrote:
> On Thu, Jul 18, 2019 at 10:47:16, Jonathan Chocron >
> wrote:
>
> > This driver is DT based and utilizes the DesignWare APIs.
> > It allows using a smaller ECAM range for a larger bus range -
> > usually an entire bus uses 1MB of addre
On Mon, 2019-07-22 at 08:54 +, Gustavo Pimentel wrote:
>
> >
> > > > +static inline void al_pcie_target_bus_set(struct al_pcie
> > > > *pcie,
> > > > + u8 target_bus,
> > > > + u8 mask_target_bus)
> > > > +{
> > >
On Tue, 2020-05-26 at 23:09 +0800, Dejin Zheng wrote:
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> It will print an error message by itself when
> devm_pci_rem
On Wed, 2020-05-27 at 21:20 +0800, Dejin Zheng wrote:
> CAUTION: This email originated from outside of the organization. Do
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> On Tue, May 26, 2020 at 06:22:56PM +00
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