luetooth/hci_uart.h
index 17ba3b4..8c53b50 100644
--- a/drivers/bluetooth/hci_uart.h
+++ b/drivers/bluetooth/hci_uart.h
@@ -35,7 +35,7 @@
#define HCIUARTGETFLAGS _IOR('U', 204, int)
/* UART protocols */
-#define HCI_UART_MAX_PROTO 10
+#define HCI_UART_MAX_PROTO 11
#define HCI_UART_H4 0
#define HCI_UART_BCSP 1
@@ -47,6 +47,7 @@
#define HCI_UART_BCM 7
#define HCI_UART_QCA 8
#define HCI_UART_AG6XX9
+#define HCI_UART_MRVL 10
#define HCI_UART_RAW_DEVICE 0
#define HCI_UART_RESET_ON_INIT1
@@ -192,3 +193,8 @@ int qca_deinit(void);
int ag6xx_init(void);
int ag6xx_deinit(void);
#endif
+
+#ifdef CONFIG_BT_HCIUART_MRVL
+int mrvl_init(void);
+int mrvl_deinit(void);
+#endif
--
caesar wang | software engineer | w...@rock-chip.com
same value,
because normal temperature update speed is also our consern in IPA.
Signed-off-by: Rocky Hao
Signed-off-by: Caesar Wang
Cc: Zhang Rui
Cc: Eduardo Valentin
Cc: Heiko Stuebner
Cc: linux...@vger.kernel.org
---
drivers/thermal/rockchip_thermal.c | 4 ++--
1 file changed, 2 inser
Signed-off-by: Caesar Wang
Cc: Eduardo Valentin
Cc: Zhang Rui
Cc: Heiko Stuebner
Cc: linux...@vger.kernel.org
---
drivers/thermal/rockchip_thermal.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/thermal/rockchip_thermal.c
b/drivers/thermal
SARADC controller needs to be reset before programming it, otherwise
it will not function properly.
Signed-off-by: Caesar Wang
Cc: Jonathan Cameron
Cc: Heiko Stuebner
Cc: Rob Herring
Cc: linux-...@vger.kernel.org
Cc: linux-rockc...@lists.infradead.org
Tested-by: Guenter Roeck
---
Changes
SARADC controller needs to be reset before programming it, otherwise
it will not function properly.
Signed-off-by: Caesar Wang
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3066a.dtsi | 2 ++
arch/arm/boot/dts/rk3288.dtsi | 2 ++
arch/arm/boot/dts/rk3xxx.dtsi | 2 ++
3
SARADC controller needs to be reset before programming it, otherwise
it will not function properly.
Signed-off-by: Caesar Wang
---
Changes in v3:
- add Doug's reviewed tag.
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a
This patch adds saradc needed information on rk3399 SoCs.
Signed-off-by: Caesar Wang
Reviewed-by: Douglas Anderson
---
Changes in v3: None
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts
On 2016年07月30日 05:28, Rob Herring wrote:
On Wed, Jul 27, 2016 at 10:24:04PM +0800, Caesar Wang wrote:
SARADC controller needs to be reset before programming it, otherwise
it will not function properly.
Signed-off-by: Caesar Wang
Cc: Jonathan Cameron
Cc: Heiko Stuebner
Cc: Rob Herring
Cc
On 2016年07月30日 05:28, Rob Herring wrote:
On Wed, Jul 27, 2016 at 10:24:04PM +0800, Caesar Wang wrote:
SARADC controller needs to be reset before programming it, otherwise
it will not function properly.
Signed-off-by: Caesar Wang
Cc: Jonathan Cameron
Cc: Heiko Stuebner
Cc: Rob Herring
Cc
On 2016年07月27日 22:47, Peter Meerwald-Stadler wrote:
SARADC controller needs to be reset before programming it, otherwise
it will not function properly.
nitpicking on wording below
Signed-off-by: Caesar Wang
Cc: Jonathan Cameron
Cc: Heiko Stuebner
Cc: Rob Herring
Cc: linux
This patch add to handle the gmac pd issue, and support
the rk3399 gmac for devicetree.
Caesar Wang (2):
arm64: dts: rockchip: support gmac for rk3399
arm64: dts: rockchip: enable the gmac for rk3399 evb board
David Wu (1):
net: stmmac: dwmac-rk: add pd_gmac support for rk3399
Roger
From: David Wu
Add the gmac power domain support for rk3399, in order to save more
power consumption.
Signed-off-by: David Wu
Signed-off-by: Caesar Wang
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/net/ethernet
From: Roger Chen
GMAC Power Domain(PD) will be disabled during suspend.
That will causes GRF registers reset.
So corresponding GRF registers for GMAC must be setup again.
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 19
We add the required and optional properties for evb board.
See the [0] to get the detail information.
[0]:
Documentation/devicetree/bindings/net/rockchip-dwmac.txt
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
---
arch/arm64/boot/dts/rockchip/rk3399-evb.dts | 31
This patch adds needed gamc information for rk3399,
also support the gmac pd.
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 90
1 file changed, 90 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip
This patch supports the gmac pd to save power consumption.
Even though some boards not need Ethernet support, the driver
core can also take care of powering up the pd before probe.
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
---
Changes in v3:
- leave into two patches based on patchv2
://patchwork.kernel.org/patch/9306339/
- generate a patch from https://patchwork.kernel.org/patch/9306339/.
Changes in v2:
- rk_gmac_powerup instead of the rk_gmac_init.
- fixes the build error on next kernel.
- Fixes the order, ss Heiko commnets on
https://patchwork.kernel.org/patch/9305991/
Caesar
From: Roger Chen
GMAC Power Domain(PD) will be disabled during suspend.
That will causes GRF registers reset.
So corresponding GRF registers for GMAC must be setup again.
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
---
Changes in v3: None
Changes in v2:
- rk_gmac_powerup instead of
From: David Wu
Add the gmac power domain support for rk3399, in order to save more
power consumption.
Signed-off-by: David Wu
Signed-off-by: Caesar Wang
---
Changes in v3: None
Changes in v2:
- fixes the build error on next kernel.
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 9
We add the required and optional properties for evb board.
See the [0] to get the detail information.
[0]:
Documentation/devicetree/bindings/net/rockchip-dwmac.txt
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
---
Changes in v3: None
Changes in v2: None
arch/arm64/boot/dts/rockchip
, clocks, pinctrl and so on.
The full details are in [0].
[0]:
Documentation/devicetree/bindings/net/rockchip-dwmac.txt
Signed-off-by: Caesar Wang
---
Changes in v3:
- generate a patch from https://patchwork.kernel.org/patch/9306339/.
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3399.dtsi
.: interrupts, grf, clocks, pinctrl and so on.
The full details are in [0].
[0]:
Documentation/devicetree/bindings/net/rockchip-dwmac.txt
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
---
Changes in v4:
- The Roger had posted patch on https://patchwork.kernel.org/patch/9274561/.
- re
atch/9306339/.
Changes in v2:
- rk_gmac_powerup instead of the rk_gmac_init.
- fixes the build error on next kernel.
- Fixes the order, ss Heiko commnets on
https://patchwork.kernel.org/patch/9305991/
Caesar Wang (1):
arm64: dts: rockchip: add the gmac power domain on rk3399
David Wu (1):
From: Roger Chen
Add constants and callback functions for the dwmac on rk3228/rk3229 socs.
As can be seen, the base structure is the same, only registers and the
bits in them moved slightly.
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
Reviewed-by: Heiko Stuebner
---
Changes in v4
From: Roger Chen
GMAC Power Domain(PD) will be disabled during suspend.
That will causes GRF registers reset.
So corresponding GRF registers for GMAC must be setup again.
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
---
Changes in v4: None
Changes in v3: None
Changes in v2
From: Roger Chen
We add the required and optional properties for evb board.
See the [0] to get the detail information.
[0]:
Documentation/devicetree/bindings/net/rockchip-dwmac.txt
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
---
Changes in v4: None
Changes in v3: None
Changes in v2
From: David Wu
Add the gmac power domain support for rk3399, in order to save more
power consumption.
Signed-off-by: David Wu
Signed-off-by: Caesar Wang
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- fixes the build error on next kernel.
drivers/net/ethernet/stmicro/stmmac
This patch supports the gmac pd to save power consumption.
Even though some boards not need Ethernet support, the driver
core can also take care of powering up the pd before probe.
Signed-off-by: Caesar Wang
---
Changes in v4:
- remove the Roger signed-off for domain patch.
Changes in v3
Kevin,
Thanks for having a look into it.
在 2015年09月03日 02:28, Kevin Hilman 写道:
Caesar Wang writes:
This driver is found on RK3288 SoCs.
In order to meet high performance and low power requirements, a power
management unit is designed or saving power when RK3288 in low power
mode.
The
Kevin,
在 2015年09月03日 02:12, Kevin Hilman 写道:
Caesar Wang writes:
This add the necessary binding documentation for the power domains
found on Rockchip SoCs.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
---
Changes in v17:
- add the decription in detail for RK3288 SoCs.
Changes
According to a description from TRM, add all the power domains.
At the moment, we can support some domains on RK3288.
We can add more types on RK3288 in the future, that's need to do.
Signed-off-by: Caesar Wang
---
Changes in v18: None
Changes in v17:
- delete the ugly chart in the c
corresponding registers.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
---
Changes in v18:
- As Kevin suggestion, set pd->num_clks = 0 in
rockchip_pm_remove_one_domain() ans add the mutex for protect
- assign the order in rk3288_pm_domains[] in pm-domain driver.
Changes in v17:
- (re)defin
This add the necessary binding documentation for the power domains
found on Rockchip SoCs.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
---
Changes in v18:
- remove the notes of domains from dt-binding.
Changes in v17:
- add the decription in detail for RK3288 SoCs.
Changes in v16
f do that.
The clocks in the dts are needed to enable before you want to happy work.
At the moment, This patch is very good work for PM hardware.
Also, we can add these clocks in the future if we have some hidden clocks.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
Reviewed-by: Mi
esume() and pm_clk_suspend().
- Decomposition power-controller, changed to multiple controller
(gpu-power-controller, hevc-power-controller).
Changes in v2:
- move clocks to "optional".
- remove the "pd->pd.of_node = np".
- make pd_vio clocks all one entry per line and alph
Doug,
在 2015年10月20日 23:52, Doug Anderson 写道:
Caesar,
On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang wrote:
We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.
Says:
The TSHUT temperature is setting more than 80 degree
Doug,
在 2015年10月21日 10:14, Doug Anderson 写道:
Caesar,
On Tue, Oct 20, 2015 at 6:47 PM, Caesar Wang wrote:
Doug,
在 2015年10月21日 00:01, Doug Anderson 写道:
Caesar,
On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang wrote:
As the TRM says, the TSHUT default state is high active.
In general, the
ent.
- As the Doug comments, drop the thermal driver patchs since
we can with pinctrl changing to work.
- As the Doug's patch to add the 'init' property.
Caesar Wang (2):
dt-bindings: Sync the dts to this document
ARM: dts: rockchip: Add the OTP gpio pinctrl
Documenta
We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.
Signed-off-by: Caesar Wang
---
Changes in v1:
- As the Doug comments, drop the thermal driver patchs since
we can with pinctrl changing to work.
- As the Doug&#
Add the OTP gpio state, we need switch the pin to gpio state
before the TSADC controller is reset.
Signed-off-by: Caesar Wang
---
Changes in v1:
- As the Doug comments, add the 'init' property to sync document.
Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 5 +++
Hi Rob,
在 2015年10月21日 23:18, Rob Herring 写道:
On Tue, Oct 20, 2015 at 9:42 PM, Caesar Wang wrote:
Add the OTP gpio state, we need switch the pin to gpio state
before the TSADC controller is reset.
Signed-off-by: Caesar Wang
---
Changes in v1:
- As the Doug comments, add the '
re), the OTP output the
*low* Signal.
In some cases, the OTP pin is connected to the PMIC, maybe the
PMIC can accept the reset response time to avoid this issue.
In other words, the system will be always reboot if we make the
OTP pin is connected the others IC to control the power.
Signed-off-by: C
r patchs since
we can with pinctrl changing to work.
- As the Doug's patch to add the 'init' property.
Caesar Wang (2):
dt-bindings: Add the "init" pinctrl in this document
ARM: dts: rockchip: Add the OTP gpio pinctrl
Documentation/devicetree/bindings/thermal
h/7454311/
Signed-off-by: Caesar Wang
Reviewed-by: Douglas Anderson
---
Changes in v2:
- Add some commits for more obvious in PATCH[2/2]
Changes in v1:
- As the Doug comments, drop the thermal driver patchs since
we can with pinctrl changing to work.
- As the Doug's patch to a
在 2015年10月22日 09:18, Rob Herring 写道:
On Wed, Oct 21, 2015 at 11:48 AM, Rob Herring wrote:
On Wed, Oct 21, 2015 at 10:45 AM, Caesar Wang wrote:
Hi Rob,
在 2015年10月21日 23:18, Rob Herring 写道:
On Tue, Oct 20, 2015 at 9:42 PM, Caesar Wang wrote:
Add the OTP gpio state, we need switch the pin
在 2015年10月22日 09:34, Rob Herring 写道:
On Wed, Oct 21, 2015 at 8:25 PM, Caesar Wang wrote:
The "init" pinctrl is defined we'll set
pinctrl to this state before probe and then "default" after probe.
Add the "init" pinctrl as the OTP gpio state, since we need
I'm missing this patch for long time.
在 2015年10月06日 22:50, Rob Herring 写道:
On Mon, Sep 14, 2015 at 6:06 AM, Caesar Wang wrote:
This add the necessary binding documentation for mailbox
found on RK3368 SoC.
Signed-off-by: Caesar Wang
---
.../bindings/mailbox/rockchip-mailbo
Hello Jassi,
Sorry for delay reply.
在 2015年10月06日 18:34, Jassi Brar 写道:
On Mon, Sep 14, 2015 at 4:36 PM, Caesar Wang wrote:
This add the necessary binding documentation for mailbox
found on RK3368 SoC.
Signed-off-by: Caesar Wang
---
.../bindings/mailbox/rockchip-mailbox.txt | 33
re), the OTP output the
*low* Signal.
In some cases, the OTP pin is connected to the PMIC, maybe the
PMIC can accept the reset response time to avoid this issue.
In other words, the system will be always reboot if we make the
OTP pin is connected the others IC to control the power.
Signed-off-by: C
op the thermal driver patchs since
we can with pinctrl changing to work.
- As the Doug's patch to add the 'init' property.
Caesar Wang (2):
dt-bindings: rockchip-thermal: Add the "init" pinctrl in this document
ARM: dts: rockchip: Add the OTP gpio p
h/7454311/
Signed-off-by: Caesar Wang
Reviewed-by: Douglas Anderson
---
Changes in v2:
- Add some commits for more obvious in PATCH[2/2]
Changes in v1:
- As the Doug comments, drop the thermal driver patchs since
we can with pinctrl changing to work.
- As the Doug's patch to a
在 2015年10月22日 11:45, Doug Anderson 写道:
Caesar,
On Wed, Oct 21, 2015 at 7:30 PM, Caesar Wang wrote:
The "init" pinctrl is defined we'll set
pinctrl to this state before probe and then "default" after probe.
Add the "init" pinctrl as the OTP gpio state, s
According to a description from TRM, add all the power domains.
At the moment, we can support some domains on RK3288.
We can add more types on RK3288 in the future, that's need to do.
Signed-off-by: Caesar Wang
---
Changes in v17:
- delete the ugly chart in the commit.
Changes in v16:
This add the necessary binding documentation for the power domains
found on Rockchip SoCs.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
---
Changes in v17:
- add the decription in detail for RK3288 SoCs.
Changes in v16:
- remove the pmu node.
Changes in v15: None
Changes in v14
idle_request().
Changes in v4:
- use list storage dev.
Changes in v3:
- DT structure has changed.
- change use pm_clk_resume() and pm_clk_suspend().
- Decomposition power-controller, changed to multiple controller
(gpu-power-controller, hevc-power-controller).
Changes in v2:
- move clocks t
corresponding registers.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
---
Changes in v17:
- (re)defining config for ROCKCHIP.
Changes in v16:
- the driver type from tristate to bool.
- Letter misspelled.
- As Ulf suggestion, remove #include ,
use "%pC" as the formatting string for t
f do that.
The clocks in the dts are needed to enable before you want to happy work.
At the moment, This patch is very good work for PM hardware.
Also, we can add it in the future if we have some hidden clocks.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
Reviewed-by: Michael Turquette
Add the OTP gpio state, we need switch the pin to gpio state
before the TSADC controller is reset.
Signed-off-by: Caesar Wang
---
Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree
pt the reset response time to avoid this issue.
In other words, the system will be always reboot if we make the OTP pin
is connected the others IC to control the power.
Tested on box board.
Caesar Wang (4):
dt-bindings: Sync the dts to this document
thermal: rockchip: ensure the otp
We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.
Signed-off-by: Caesar Wang
---
arch/arm/boot/dts/rk3288.dtsi | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi
As the TRM says, the TSHUT default state is high active.
In general, the TSHUT state can get from the dts. Otherwise
it gets the state from this.
Signed-off-by: Caesar Wang
---
drivers/thermal/rockchip_thermal.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
pt the reset response time to avoid this issue.
In other words, the system will be always reboot if we make the OTP pin
is connected the others IC to control the power.
Signed-off-by: Caesar Wang
---
drivers/thermal/rockchip_thermal.c | 32
1 file changed, 3
The subject is deleted by my finger.
在 2015年10月20日 17:11, Caesar Wang 写道:
We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.
Says:
The TSHUT temperature is setting more than 80 degree, the default
tshut polarity is
n
accept the reset response time to avoid this issue.
In other words, the system will be always reboot if we
make the OTP pin is connected the others IC to control the power.
Signed-off-by: Caesar Wang
---
Changes in v3:
- Add the pinctrl state for in the suspend/resume.
Changes in v2: None
C
/patchwork.kernel.org/patch/7454311/
Signed-off-by: Caesar Wang
Reviewed-by: Douglas Anderson
---
Changes in v3:
- Add the "sleep" pinctrl as the gpio state in PATCH[3/3]
Changes in v2:
- Add some commits for more obvious in PATCH[2/2]
Changes in v1:
- As the Doug comments, drop th
tting temperature), the OTP output the
*low* Signal.
In some cases, the OTP pin is connected to the PMIC, maybe the
PMIC can accept the reset response time to avoid this issue.
In other words, the system will be always reboot if we make the
OTP pin is connected the others IC to control the power
the Doug comments, drop the thermal driver patchs since
we can with pinctrl changing to work.
- As the Doug's patch to add the 'init' property.
Caesar Wang (3):
dt-bindings: rockchip-thermal: Add the pinctrl states in this document
thermal: rockchip: ensure the otp sta
在 2015年10月23日 12:04, Doug Anderson 写道:
Caesar,
On Thu, Oct 22, 2015 at 9:54 PM, Caesar Wang wrote:
We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.
Says:
The TSHUT temperature is setting more than 80 degree, the
在 2015年10月23日 12:04, Doug Anderson 写道:
Caesar,
On Thu, Oct 22, 2015 at 9:54 PM, Caesar Wang wrote:
We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.
Says:
The TSHUT temperature is setting more than 80 degree, the
Doug comments, add the 'init' property to sync document.
- As the Doug comments, drop the thermal driver patchs since
we can with pinctrl changing to work.
- As the Doug's patch to add the 'init' property.
Caesar Wang (3):
dt-bindings: rockchip-thermal: Add the pinctr
tting temperature), the OTP output the
*low* Signal.
In some cases, the OTP pin is connected to the PMIC, maybe the
PMIC can accept the reset response time to avoid this issue.
In other words, the system will be always reboot if we make the
OTP pin is connected the others IC to control the power
/patchwork.kernel.org/patch/7454311/
Signed-off-by: Caesar Wang
Reviewed-by: Douglas Anderson
---
Changes in v4: None
Changes in v3:
- Add the "sleep" pinctrl as the gpio state in PATCH[3/3]
Changes in v2:
- Add some commits for more obvious in PATCH[2/2]
Changes in v1:
- As the
d avoid glitches when the system is resumed.
Signed-off-by: Caesar Wang
---
Changes in v4:
- take the Doug's commit as correct decription.
Changes in v3:
- Add the pinctrl state for in the suspend/resume.
Changes in v2: None
Changes in v1: None
drivers/thermal/rockchip_thermal.
This add the necessary binding documentation for mailbox
found on RK3368 SoC.
Signed-off-by: Caesar Wang
---
Changes in v1:
- PATCH[1/3] doc:
- As the Rob Herring comments, s/share/shared/ and specify the value of
#mbox-cells.
- Move the shared memory in mailbox, let's move the propert
and tx buf into the client drivers.
- PATCH[3/3] dts:
- fix "processormZ"--> "processor",the miss-fingerboard.
- Remove the shared memory in mailbox controller dtsi.
Caesar Wang (3):
dt-bindings: rockchip-mailbox: Add mailbox controller document on
Rockchip SoCs
mailbo
lock registers for software to use to indicate whether
mailbox is occupied.
Signed-off-by: Caesar Wang
---
Changes in v1:
- PATCH[2/3] driver:
- The commit: %s/@/(num order).
- Add the module authors to instead of the notes.
- Add the COMPILE_TEST to auto compile test in Kconfig.
- Let the
This adds mailbox device nodes in dts.
Mailbox is used by the Rockchip CPU cores to communicate
requests to MCU processor.
Signed-off-by: Caesar Wang
---
Changes in v1:
- PATCH[3/3] dts:
- fix "processormZ"--> "processor",the miss-fingerboard.
- Remove the shared memor
e the API instead of open-coding it, no functional change
intended.
Signed-off-by: Shawn Lin
Reviewed-by: Brian Norris
Tested-by: Caesar Wang
Tested-by: Ziyuan Xu
---
Changes in v2:
- propagate the error and print it
- avoid using busy wait
drivers/phy/rockchip/phy-rockchip-emmc.c
在 2018年01月11日 03:36, Doug Anderson 写道:
Hi,
On Wed, Jan 10, 2018 at 9:46 AM, Brian Norris wrote:
*/
- timeout = jiffies + msecs_to_jiffies(50);
- do {
- udelay(1);
-
- regmap_read(rk_phy->reg_base,
- rk_phy->reg_offset + GRF_EMMCPHY_ST
From: Shawn Lin
Just use the API instead of open-coding it, no functional change
intended.
Signed-off-by: Shawn Lin
Reviewed-by: Brian Norris
Signed-off-by: Caesar Wang
---
Changes in v3:
- As Doug commented on https://patchwork.kernel.org/patch/10154797,
Change "1, 50"
From: Shawn Lin
It turns out that 5us isn't enough for all cases, so let's
retry some more times to wait for caldone.
Signed-off-by: Shawn Lin
Tested-by: Ziyuan Xu
Signed-off-by: Caesar Wang
---
Changes in v3:
- As Doug commented on both upstream and gerrit.
Change "5, 50&q
Hi Kishon,
Since the Shawn isn't available, I take over this series patches for now.
As the original bug had tracked on https://issuetracker.google.com/71561742.
In some cases, the mmc phy power on failed during booting up.
The log as below:
...
[ 2.375333] rockchip_emmc_phy_power: caldone time
e.
Signed-off-by: Shawn Lin
Tested-by: Caesar Wang
I had tested on rk3399 chromebook, so feel free to add my tag.
-Caesar
---
drivers/phy/rockchip/phy-rockchip-emmc.c | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-
From: Shawn Lin
It turns out that 5us isn't enough for all cases, so let's
retry some more times to wait for caldone.
Signed-off-by: Shawn Lin
Tested-by: Ziyuan Xu
Signed-off-by: Caesar Wang
---
Changes in v2:
- print the return valut with regmap_read_poll_timeout failing.
d
Hi Kishon,
Since the Shawn isn't available, I take over this series patches for now.
As the original bug had tracked on https://issuetracker.google.com/71561742.
In some cases, the mmc phy power on failed during booting up.
The log as below:
...
[ 2.375333] rockchip_emmc_phy_power: caldone time
From: Shawn Lin
Just use the API instead of open-coding it, no functional change
intended.
Signed-off-by: Shawn Lin
Reviewed-by: Brian Norris
Signed-off-by: Caesar Wang
---
Changes in v2:
- As Brian commented on https://patchwork.kernel.org/patch/10139891/,
changed the note and added to
On 2018/12/17 下午11:02, Thierry Reding wrote:
From: Thierry Reding
Get rid of some boilerplate driver removal code by using the newly added
device-managed registration API.
Reviewed-by: Caesar Wang
Thanks,
Caesar
Cc: Caesar Wang
Signed-off-by: Thierry Reding
---
drivers/mailbox
/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39994
Signed-off-by: Caesar Wang
Reviewed-by: Dmitry Torokhov
---
Changes in v4:
&
doesn't reject "code == 0xfff"
Fixed in rk_tsadcv2_code_to_temp(u32 code)
Changes in v2:
Reviewed-by: Dmitry Torokhov
Caesar Wang (1):
thermal: rockchip: make temperature reporting much more accurate
drivers/thermal/rockchip_thermal.c | 32 ++--
1
sted-by Daniel Kurtz,
the check doesn't reject "code == 0xfff"
Fixed in rk_tsadcv2_code_to_temp(u32 code)
Changes in v2:
Reviewed-by: Dmitry Torokhov
Caesar Wang (1):
thermal: rockchip: make temperature reporting much more accurate
drivers/thermal/rockchip_thermal.c | 38 ++
/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39994
Signed-off-by: Caesar Wang
Reviewed-by: Dmitry Torokhov
---
Changes in v5:
Fi
/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39994
Signed-off-by: Caesar Wang
Reviewed-by: Dmitry Torokhov
Reviewed-by: Daniel Kurtz
rn -EAGAIN" instead of "return rk_tsadcv2_code_to_temp(code)"
Changes in v3:
Suggested-by Daniel Kurtz,
the check doesn't reject "code == 0xfff"
Fixed in rk_tsadcv2_code_to_temp(u32 code)
Changes in v2:
Reviewed-by: Dmitry Torokhov
Caesar Wang (1):
thermal: rockch
This patch is merged on chromiumos/third_party/kernel.
https://chromium-review.googlesource.com/#/c/239190/
Tested on veyron boards.
Caesar Wang (1):
thermal: rockchip: make temperature reporting much more accurate
drivers/thermal/rockchip_thermal.c | 26 +-
1 file
/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39994
Signed-off-by: Caesar Wang
---
drivers/thermal/rockchip_
/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39994
Signed-off-by: Caesar Wang
Reviewed-by: Dmitry Torokhov
---
Changes in v2:
Revie
This patch is merged on chromiumos/third_party/kernel.
https://chromium-review.googlesource.com/#/c/239190/
Tested on veyron boards.
Changes in v2:
Reviewed-by: Dmitry Torokhov
Caesar Wang (1):
thermal: rockchip: make temperature reporting much more accurate
drivers/thermal
for next kernel.
Caesar Wang (3):
dt-bindings: add document of Rockchip power domain
power-domain: rockchip: add power domain driver
ARM: dts: add RK3288 power-domain node
.../bindings/arm/rockchip/power_domain.txt | 48 ++
arch/arm/boot/dts/rk3288.dtsi | 59
In order to meet high performance and low power requirements, a power
management unit is designed or saving power when RK3288 in low power
mode.
The RK3288 PMU is dedicated for managing the power ot the whole chip.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
---
arch/arm/mach
syncchronous reset and
then sync revoked.so we need to enable clocks of all devices.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
---
Changes in v14:
- does not need to set an owner,remove the "THIS_MODULE".
Changes in v13:
- Remove essential clocks from rk3288 PD_
1 - 100 of 936 matches
Mail list logo
