On Thu, 25 May 2017 11:49:13 +1200
Chris Packham wrote:
> Use mtd_device_register() instead of mtd_device_parse_register() to
> eliminate two unused parameters.
>
> Signed-off-by: Chris Packham
> Reviewed-by: Andrew Lunn
> Tested-by: Andrew Lunn
Acked-by: Boris Brezillon
On Thu, 25 May 2017 11:49:12 +1200
Chris Packham wrote:
> This allows registering of this device via a Device Tree.
>
> Signed-off-by: Chris Packham
> Reviewed-by: Andrew Lunn
> Tested-by: Andrew Lunn
Acked-by: Boris Brezillon
> ---
> Changes in v2:
> - collect
re they fall on writesize boundaries.
>
> Helped-by: Boris Brezillon
> Signed-off-by: Chris Packham
Acked-by: Boris Brezillon
> ---
> Changes in v3:
> - new
> Changes in v4:
> - None
>
> drivers/mtd/mtdpart.c | 25 -
> 1 file change
eviewed-by: Andrew Lunn
> Tested-by: Andrew Lunn
Acked-by: Boris Brezillon
> ---
> Changes in v2
> - collect revew/test from Andrew
> Changes in v3:
> - remove setting of erasesize
> Changes in v4:
> - none
>
> drivers/mtd/devices/mchp23k256.c | 1 +
> 1 fil
t be told via a
> Device Tree or default to mchp23k256 when device tree is not used.
>
> Signed-off-by: Chris Packham
> Reviewed-by: Andrew Lunn
Acked-by: Boris Brezillon
> ---
> Changes in v2:
> - fix formatting in switch statement
> - add support for 24-bit addressing
On Thu, 25 May 2017 13:50:20 +0900
Masahiro Yamada wrote:
> Drivers are supposed to set correct ecc->{size,strength,bytes} before
> calling nand_scan_tail(), but it does not complain about ecc->total
> bigger than oobsize.
>
> In this case, chip->scan_bbt() crashes due to memory corruption, but
Hi Stephen,
On Tue, 30 May 2017 11:37:23 +1000
Stephen Rothwell wrote:
> Hi Boris,
>
> Today's linux-next merge of the nand tree got a conflict in:
>
> drivers/mtd/nand/nand_base.c
>
> between commit:
>
> b6f6c29454d2 ("mtd: adjust kernel-docs to avoid Sphinx/kerneldoc warnings")
>
> fr
Hi Christophe,
On Sun, 22 Oct 2017 10:28:31 +0200
Christophe JAILLET wrote:
> If 'chip->state == FL_SYNCING', we will 'goto retry' with the mutex
> '&shared->lock' already taken.
> In such a case, the 'mutex_lock' at line 927 can never succeed.
>
> In order to avoid a deadlock, move the 'mutex_
Hi Stephen,
On Wed, 1 Nov 2017 14:16:40 +1100
Stephen Rothwell wrote:
> Hi Dave,
>
> After merging the drm tree, today's linux-next build (x86_64 allmodconfig)
> produced these warnings:
>
> drivers/gpu/drm/vc4/vc4_bo.c: In function 'vc4_bo_stats_debugfs':
> drivers/gpu/drm/vc4/vc4_bo.c:91:17:
On Mon, 30 Oct 2017 22:32:45 -0500
moto...@gmail.com wrote:
> From: Brent Taylor
>
> When mtdoops calls mtd_panic_write, it eventually calls
> panic_nand_write in nand_base.c. In order to properly
> wait for the nand chip to be ready in panic_nand_wait,
> the chip must first be selected.
>
> W
Hi Arnd,
On Thu, 2 Nov 2017 12:20:43 +0100
Arnd Bergmann wrote:
> Printing a size_t variable needs to use the %z format string modifier
> rather than %l, otherwise we get this warning on 64-bit architectures:
>
> drivers/gpu/drm/vc4/vc4_bo.c: In function 'vc4_bo_stats_debugfs':
> drivers/gpu/d
On Wed, 1 Nov 2017 21:48:22 +0200
Baruch Siach wrote:
> Hi Marc,
>
> On Wed, Nov 01, 2017 at 08:03:20PM +0100, Marc Gonzalez wrote:
> > On 01/11/2017 18:53, Alan Cox wrote:
> > > For that matter given the bad blocks don't randomly change why not cache
> > > them ?
> >
> > That's a good que
On Thu, 19 Oct 2017 11:41:29 +0300
Roger Quadros wrote:
> Since v4.12, NAND subpage writes were causing a NULL pointer
> dereference on OMAP platforms (omap2-nand) using OMAP_ECC_BCH4_CODE_HW,
> OMAP_ECC_BCH8_CODE_HW and OMAP_ECC_BCH16_CODE_HW.
>
> This is because for those ECC modes, omap_calcu
On Thu, 19 Oct 2017 17:11:34 +0300
Roger Quadros wrote:
> On 19/10/17 16:51, Boris Brezillon wrote:
> > On Thu, 19 Oct 2017 11:41:29 +0300
> > Roger Quadros wrote:
> >
> >> Since v4.12, NAND subpage writes were causing a NULL pointer
> >> dereferen
On Thu, 19 Oct 2017 17:23:24 +0300
Roger Quadros wrote:
> On 19/10/17 17:20, Boris Brezillon wrote:
> > On Thu, 19 Oct 2017 17:11:34 +0300
> > Roger Quadros wrote:
> >
> >> On 19/10/17 16:51, Boris Brezillon wrote:
> >>> On Thu, 19 Oct 2017
On Fri, 20 Oct 2017 15:16:21 +0300
Roger Quadros wrote:
> Since v4.12, NAND subpage writes were causing a NULL pointer
> dereference on OMAP platforms (omap2-nand) using OMAP_ECC_BCH4_CODE_HW,
> OMAP_ECC_BCH8_CODE_HW and OMAP_ECC_BCH16_CODE_HW.
>
> This is because for those ECC modes, omap_calcu
Hi Brent,
Subject should be prefixed by "mtd: nand: ", so
"mtd: nand: Fix writing mtdoops to nand flash"
On Sun, 29 Oct 2017 23:23:43 -0500
moto...@gmail.com wrote:
> From: Brent Taylor
>
> When mtdoops calls mtd_panic_write, it eventually calls
> panic_nand_write in nand_base.c. In order to
On Sun, 29 Oct 2017 20:40:02 +0800
Pan Bian wrote:
> Memory allocated by kmem_cache_alloc() should not be deallocated with
> kfree(). Use kmem_cache_free() instead.
>
> Signed-off-by: Pan Bian
Reviewed-by: Boris Brezillon
Richard, maybe you can add:
Fixes: dbb7d2a88d2a ("
eans up
> clang warning:
>
> drivers/mtd/ubi/fastmap.c:217:19: warning: Value stored to 'p'
> during its initialization is never read
>
> Signed-off-by: Colin Ian King
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/ubi/fastmap.c | 3 +--
> 1 file chang
Hi PrasannaKumar,
On Sat, 28 Oct 2017 13:13:51 +0530
PrasannaKumar Muralidharan wrote:
> From: Lars-Peter Clausen
>
> Avoid sending unnecessary READ commands to the chip.
>
> Signed-off-by: Lars-Peter Clausen
> Signed-off-by: PrasannaKumar Muralidharan
> ---
> This patch is taken from git:/
Hi Chen,
On Thu, 14 Sep 2017 21:58:11 +0800
Chen Bin wrote:
> On UBIFS, Cypress S29GL01GT flash is failed to access occasionally
> , and throw below error information and call trace:
> MTD get_chip(): chip not ready after erase suspend
> UBI error: ubi_io_write: error -5 while writing 512 bytes
On Mon, 30 Oct 2017 18:17:50 +0530
PrasannaKumar Muralidharan wrote:
> Hi Boris,
>
> On 30 October 2017 at 14:04, Boris Brezillon
> wrote:
> > Hi PrasannaKumar,
> >
> > On Sat, 28 Oct 2017 13:13:51 +0530
> > PrasannaKumar Muralidharan wrote:
On Mon, 30 Oct 2017 07:46:18 -0500
Brent Taylor wrote:
> Hi Bors, thanks for your quick reply.
>
> On Mon, Oct 30, 2017 at 3:23 AM, Boris Brezillon
> wrote:
> > Hi Brent,
> >
> > Subject should be prefixed by "mtd: nand: ", so
> >
> > "
On Mon, 30 Oct 2017 22:32:45 -0500
moto...@gmail.com wrote:
> From: Brent Taylor
>
> When mtdoops calls mtd_panic_write, it eventually calls
> panic_nand_write in nand_base.c. In order to properly
> wait for the nand chip to be ready in panic_nand_wait,
> the chip must first be selected.
>
> W
just remove GENERIC_IO.
>
> Signed-off-by: Rob Herring
> Cc: Jeff Dike
> Cc: Richard Weinberger
> Cc: David Woodhouse
> Cc: Brian Norris
> Cc: Boris Brezillon
Acked-by: Boris Brezillon
> Cc: Marek Vasut
> Cc: Cyrille Pitchen
> Cc: user-mode-linux
error log.
>
> This is a little risky in my opinion. Not only does it print two error
> messages for non-legacy platforms (that would be another regression if
> you want to be nit-picking), but it is subtly buggy. If you have a
> system with multiple PWM providers, you could end up
On Mon, 5 Oct 2015 14:58:03 +0200
Thierry Reding wrote:
> On Mon, Oct 05, 2015 at 01:19:12PM +0200, Boris Brezillon wrote:
> > Hi Thierry,
> >
> > On Mon, 5 Oct 2015 11:35:43 +0200
> > Thierry Reding wrote:
> >
> > > On Thu, Oct 01, 2015 at 10:00:22AM
On Mon, 5 Oct 2015 16:07:41 +0200
Thierry Reding wrote:
> On Mon, Oct 05, 2015 at 03:30:24PM +0200, Boris Brezillon wrote:
> > On Mon, 5 Oct 2015 14:58:03 +0200
> > Thierry Reding wrote:
> >
> > > On Mon, Oct 05, 2015 at 01:19:12PM +0200, Boris Brezi
Hi Brian,
On Mon, 12 Oct 2015 16:35:37 -0700
Brian Norris wrote:
> On Fri, Oct 02, 2015 at 07:53:25AM +0200, Boris Brezillon wrote:
> > The ->read_xxx() methods are all passed the page number the NAND controller
> > is supposed to read, but ->write_xxx() do not
) methods add some
consistency to the current API.
Signed-off-by: Boris Brezillon
CC: Josh Wu
CC: Ezequiel Garcia
CC: Maxime Ripard
CC: Greg Kroah-Hartman
CC: Huang Shijie
CC: Stefan Agner
CC: de...@driverdev.osuosl.org
CC: linux-arm-ker...@lists.infradead.org
CC: linux-kernel@vger.k
il someone else comes with another scrambler
controller and we really see the need to factorize some code.
Best Regards,
Boris
[1]https://lkml.org/lkml/2014/4/30/721
Boris Brezillon (3):
mtd: nand: add NAND_NEED_SCRAMBLING option flag
mtd: nand: add NAND_NEED_SCRAMBLING flag to the H27UC
NAND
block.
Randomizing input data mitigate this problem by avoiding such repeated
patterns.
Signed-off-by: Boris Brezillon
---
drivers/mtd/nand/sunxi_nand.c | 274 ++
1 file changed, 250 insertions(+), 24 deletions(-)
diff --git a/drivers/mtd/nand/sunxi_nan
The H27UCG8T2ATR-BC requires an external data scrambler. Reflect this
constraint in the nand_flash_ids definition.
Signed-off-by: Boris Brezillon
---
drivers/mtd/nand/nand_ids.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd
Some MLC NANDs are sensible to repeated patterns and require data to be
scrambled in order to limit the number of bitflips.
Add a new flag to let the NAND controller know about this constraint.
Signed-off-by: Boris Brezillon
---
include/linux/mtd/nand.h | 6 ++
1 file changed, 6 insertions
Hi Julian,
On Fri, 16 Oct 2015 09:32:38 +1100
Julian Calaby wrote:
> Hi Boris,
>
> On Fri, Oct 16, 2015 at 4:17 AM, Boris Brezillon
> wrote:
> > Some MLC NANDs are sensible to repeated patterns and require data to be
>
> Do you mean "sensitive" instead of
On Fri, 16 Oct 2015 08:28:54 +0200
Boris Brezillon wrote:
> Hi Julian,
>
> On Fri, 16 Oct 2015 09:32:38 +1100
> Julian Calaby wrote:
>
> > Hi Boris,
> >
> > On Fri, Oct 16, 2015 at 4:17 AM, Boris Brezillon
> > wrote:
> > > Some MLC NANDs are s
On Thu, 15 Oct 2015 19:17:23 +0200
Boris Brezillon wrote:
> Add support for the randomizer engine available in Allwinner's NFC IP.
>
> Randomization is useful to support modern NAND chips which are sensible to
> repeated patterns. On such NANDs you might experience an unexpecte
On Tue, 20 Oct 2015 09:20:10 +0200
Richard Weinberger wrote:
> On Thu, Oct 15, 2015 at 7:17 PM, Boris Brezillon
> wrote:
> > The H27UCG8T2ATR-BC requires an external data scrambler. Reflect this
> > constraint in the nand_flash_ids definition.
> >
> >
patch 2 is given here as an example of how patch 1 simplifies
things, but won't apply cleanly on mtd-next (it's based on top of other
changes I haven't submitted yet).
Best Regards,
Boris
Boris Brezillon (2):
mtd: nand: automate NAND timings selection
mtd: nand: sunxi: switch
The NAND framework is now able to select the best NAND timings for us.
All we have to do is implement a ->setup_data_interface() function to
apply those timings and remove the timing selection code from the sunxi
driver.
Signed-off-by: Boris Brezillon
---
drivers/mtd/nand/sunxi_nand.c |
ult information.
NAND controller willing to support timings adjustment should just
implement the ->setup_data_interface() method.
Signed-off-by: Boris Brezillon
---
drivers/mtd/nand/nand_base.c | 189 ++-
include/linux/mtd/nand.h | 115 +++
6,9 @@ struct device_node;
> /**
> * struct mtd_part_parser_data - used to pass data to MTD partition parsers.
> * @origin: for RedBoot, start address of MTD device
> - * @of_node: for OF parsers, device node containing partitioning information
> + * @of_node: for OF parsers,
ne in duplicate for now on some drivers. I don't think this should
> break things. (Famous last words.)
>
> Signed-off-by: Brian Norris
For the sunxi_nand driver
Acked-by: Boris Brezillon
Thanks,
Boris
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
htt
don't think there are multiple gpios for r/b# function.
Because it's supposed to be a generic binding, and some NAND chips
embed several dies, thus exposing several CS and RB pins, hence the
rb-gpios name.
Also, as described here [1], the convention is to name your property
-gpios ev
ed the ->dev_ready() or ->waitfunc()
fields, and to choose how to implement it he may need to know
which kind of RB handler should be used (this is the case in the sunxi
driver, where the user can either use a GPIO or native R/B pin directly
connected to the controller).
All this makes m
_main_base base;
unsigned long frequency;
unsigned long accuracy;
};
Also, it would avoid any problem if someone decides to change the field
oder in one of those structures.
Best Regards,
Boris
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-
ver, this hook is not used by any mainline driver, and should not be
used by new drivers, because detecting the NAND chip is not something
controller specific.
Signed-off-by: Boris Brezillon
---
drivers/mtd/nand/nand_base.c | 5 +
include/linux/mtd/nand.h | 6 --
2 files changed
Hi Brian,
On Mon, 24 Aug 2015 19:10:19 +0200
Boris Brezillon wrote:
> The ->read_xxx() methods are all passed the page number the NAND controller
> is supposed to read, but ->write_xxx() do not have such a parameter.
>
> This is a problem if we want to properly implement
) methods add some
consistency to the current API.
Signed-off-by: Boris Brezillon
CC: Josh Wu
CC: Ezequiel Garcia
CC: Maxime Ripard
CC: Greg Kroah-Hartman
CC: Huang Shijie
CC: Bryan Wu
CC: Stefan Agner
CC: de...@driverdev.osuosl.org
CC: linux-arm-ker...@lists.infradead.org
CC: lin
On Thu, 1 Oct 2015 10:17:50 -0700
Brian Norris wrote:
> On Mon, Aug 24, 2015 at 07:10:19PM +0200, Boris Brezillon wrote:
> > The ->read_xxx() methods are all passed the page number the NAND controller
> > is supposed to read, but ->write_xxx() do not have such a paramete
) methods add some
consistency to the current API.
Signed-off-by: Boris Brezillon
CC: Josh Wu
CC: Ezequiel Garcia
CC: Maxime Ripard
CC: Greg Kroah-Hartman
CC: Huang Shijie
CC: Bryan Wu
CC: Stefan Agner
CC: de...@driverdev.osuosl.org
CC: linux-arm-ker...@lists.infradead.org
CC: lin
On Thu, 1 Oct 2015 20:04:17 +0200
Boris Brezillon wrote:
> The ->read_xxx() methods are all passed the page number the NAND controller
> is supposed to read, but ->write_xxx() do not have such a parameter.
>
> This is a problem if we want to properly implement data
> scr
) methods add some
consistency to the current API.
Signed-off-by: Boris Brezillon
CC: Josh Wu
CC: Ezequiel Garcia
CC: Maxime Ripard
CC: Greg Kroah-Hartman
CC: Huang Shijie
CC: Stefan Agner
CC: de...@driverdev.osuosl.org
CC: linux-arm-ker...@lists.infradead.org
CC: linux-kernel@vger.k
we can consistently make BBM checks look for 6 or 7
> "one" bits (rather than a full 8 bits, i.e. BBM == 0xff), then we can
> just unconditionally switch to RAW rather than PLACE_OOB. And we don't
> need a flag like this pach introduces.
I guess it all depends whether w
command only knows whether there was bitflips above the
> threshold and can not get accurate bitflips. For now, I set
> max_bitflips mtd->bitflip_threshold.
>
> Signed-off-by: KOBAYASHI Yoshitake
Reviewed-by: Boris Brezillon
> ---
> drivers
AYASHI Yoshitake
With the commit message adjusted as suggested above,
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/nand_toshiba.c | 53
> -
> 1 file changed, 52 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw
Hi Dan,
On Wed, 1 Aug 2018 15:05:51 +0300
Dan Carpenter wrote:
> On Wed, Aug 01, 2018 at 11:24:19AM +0800, Jheng-Jhong Wu wrote:
> > For NAND flash chips with more than 1Gbit (e.g. MT29F2G) more than 16 bits
> > are necessary to address the correct page. The driver sets the address for
> > more
On Mon, 6 Aug 2018 15:01:37 +0300
Dan Carpenter wrote:
> On Mon, Aug 06, 2018 at 01:46:48PM +0200, Boris Brezillon wrote:
> > Hi Dan,
> >
> > On Wed, 1 Aug 2018 15:05:51 +0300
> > Dan Carpenter wrote:
> >
> > > On Wed, Aug 01, 2018 at 11:24:19AM
On Tue, 7 Aug 2018 00:29:13 +0200
Janusz Krzysztofik wrote:
> In its current shape, the driver sets data port direction before each
> byte read/write operation, even during multi-byte transfers. Since
> performance of the driver is completely not acceptable on Amstrad Delta
> after it has been
Hi Piotr,
On Mon, 18 Jun 2018 18:21:24 +0200
Piotr Bugalski wrote:
> Documentation for DT-binding change.
>
> Suggested-by: Boris Brezillon
I'm pretty sure I didn't make a single suggestion about the DT
bindings you use here ;-).
> Signed-off-by: Piotr Bugalski
>
Hi Piotr,
On Mon, 18 Jun 2018 18:21:22 +0200
Piotr Bugalski wrote:
> Hello,
>
> Atmel SAMA5D2 is equipped with two QSPI interfaces. These interfaces can
> work as in SPI-compatible mode or use two / four lines to improve
> communication speed. At the moment there is QSPI driver strongly tied to
On Wed, 20 Jun 2018 21:12:02 +
Chris Packham wrote:
> On 20/06/18 19:54, Boris Brezillon wrote:
> > On Wed, 20 Jun 2018 17:05:43 +1200
> > Chris Packham wrote:
> >
> >> Some Micron NAND chips (MT29F1G08ABAFAWP-ITE:F) report 00 00 for the
> >> revi
On Thu, 21 Jun 2018 22:33:25 +1200
Chris Packham wrote:
> Add defines for the ONFI version bits and use them in
> nand_flash_detect_onfi().
>
> Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
> ---
> Changes in v4:
> - New
>
> drivers/mt
On Thu, 21 Jun 2018 22:33:27 +1200
Chris Packham wrote:
> Micron MT29F1G08ABAFAWP-ITE:F supports an on-die ECC with 8 bits
> per 512 bytes. Add support for this combination.
>
> Signed-off-by: Chris Packham
> ---
> Changes in v2:
> - New
> Changes in v3:
> - Handle reporting of corrected errors
On Thu, 21 Jun 2018 22:33:28 +1200
Chris Packham wrote:
> Some Micron NAND chips have on-die ECC forceably enabled. The detect
> these based on chip ID as there seems to be no other way of
> distinguishing these chips from those that have optional support for
> on-die ECC.
>
> When a chip with m
ler
> and is not related to MTD, however can work with NAND-flash or other
> peripherals using spi-mem interface.
Thanks for working on that.
>
> Suggested-by: Boris Brezillon
> Signed-off-by: Piotr Bugalski
>
> ---
> drivers/spi/Kconfig | 9 +
>
Hi Stefan,
On Thu, 21 Jun 2018 22:31:43 +0200
Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations using ->exec_op()
> use PIO mode for data transfers. Raw, ECC and
On Tue, 12 Jun 2018 11:15:00 +0800
Zhouyang Jia wrote:
> When ioremap_nocache fails, the lack of error-handling code may
> cause unexpected results.
>
> This patch adds error-handling code after calling ioremap_nocache.
>
> Signed-off-by: Zhouyang Jia
> ---
> drivers/mtd/maps/gpio-addr-flash.
Hi Piotr,
On Fri, 22 Jun 2018 07:57:10 +0200 (CEST)
Piotr Bugalski wrote:
> Hi Boris,
>
> I'm a bit allergic to personal preferences in coding style,
I'm just pointing things that are common kernel coding style practices.
You might not like coding style rules of a particular project, but when
On Fri, 22 Jun 2018 13:28:34 +1200
Chris Packham wrote:
> Micron MT29F1G08ABAFAWP-ITE:F supports an on-die ECC with 8 bits
> per 512 bytes. Add support for this combination.
>
> Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
> ---
>
> Notes:
> Ch
hips from those that have optional support for
> on-die ECC.
>
> When a chip with mandatory on-die ECC is detected change the current ECC
> mode to on-die.
That part is no longer true.
>
> Signed-off-by: Chris Packham
With the commit message fixed:
Reviewed-by: Boris B
Add a driver for Cadence I3C GPIO expander.
Signed-off-by: Boris Brezillon
---
Hi Linus,
I intentionally did not report your Acked-by because of the scract
buffer changes I added in this version (needed to follow the
"buffer should be DMA-able" rule)
Feel free to add it back if y
On Mon, 18 Jun 2018 15:57:57 +0200
Miquel Raynal wrote:
> Hi Boris,
>
> On Wed, 13 Jun 2018 14:32:36 +0530, Abhishek Sahu
> wrote:
>
> > Positive return value from read_oob() is making false BAD
> > blocks. For some of the NAND controllers, OOB bytes will be
> > protected with ECC and read_oob
On Fri, 22 Jun 2018 09:04:25 +0200
Geert Uytterhoeven wrote:
> With gcc 4.1.2 when compiling for 32-bit:
>
> drivers/mtd/devices/mtd_dataflash.c:736: warning: integer constant is too
> large for ‘long’ type
> drivers/mtd/devices/mtd_dataflash.c:737: warning: integer constant is too
> l
Hi Masahiro,
On Tue, 19 Jun 2018 13:28:11 +0200
Boris Brezillon wrote:
> Hi Masahiro,
>
> On Fri, 15 Jun 2018 10:18:50 +0900
> Masahiro Yamada wrote:
>
> > According to the Denali User's Guide, this IP needs three clocks:
> >
> > - clk: contro
for existing DT of UniPhier, and also
> fixes the issue of SOCFPGA because both platforms use 200 MHz for the
> bus interface clock.
>
> Fixes: 1bb88666775e ("mtd: nand: denali: handle timing parameters by
> setup_data_interface()")
> Cc: linux-stable #4.14+
> Reporte
e clock for the backward
> compatibility, but the DT binding should represent the real hardware,
> and future platforms must follow this.
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Boris Brezillon
> ---
>
> Changes in v4:
> - split into a separate patch
>
>
ct denali_dt {
> struct denali_nand_info denali;
> - struct clk *clk;
> + struct clk *clk;/* core clock */
> + struct clk *clk_x; /* bus interface clock */
> + struct clk *clk_ecc;/* ECC circuit clock */
Probably better to use a ke
On Wed, 13 Jun 2018 23:23:33 +0200
Richard Weinberger wrote:
> With version 2 of fastmap, flags are supported.
> We fall back to scanning mode if unsupported flags are found.
>
> Signed-off-by: Richard Weinberger
> ---
> drivers/mtd/ubi/fastmap.c | 24
> drivers/mtd/
On Wed, 13 Jun 2018 23:23:34 +0200
Richard Weinberger wrote:
> This flag indicates that the fastmap was preseeded, which means
> it was created offline by a tool such as ubinize which cannot know
> the whole MTD state such as real size and bad blocks.
> As consequence UBI has to take special care
mber if used PEBs for
> the calculation.
> Therefore the found fastmap might be smaller than the kernel expects.
>
> Signed-off-by: Richard Weinberger
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/ubi/fastmap.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
On Wed, 13 Jun 2018 23:23:40 +0200
Richard Weinberger wrote:
> This WARN_ON() was used while development of fastmap, now
> it can be a regular ubi_err().
>
> Signed-off-by: Richard Weinberger
> ---
> drivers/mtd/ubi/fastmap.c | 14 --
> 1 file changed, 8 insertions(+), 6 deletions(
On Wed, 13 Jun 2018 23:23:41 +0200
Richard Weinberger wrote:
> Using this parameter one can force UBI do to a full scan
> instead of using a fastmap.
>
> Signed-off-by: Richard Weinberger
> ---
> drivers/mtd/ubi/attach.c | 13 +
> drivers/mtd/ubi/build.c | 5 -
> 2 files chan
On Wed, 13 Jun 2018 23:23:42 +0200
Richard Weinberger wrote:
> This allows userspace, ubiattach, to force a full scan.
>
> Signed-off-by: Richard Weinberger
> ---
> include/uapi/mtd/ubi-user.h | 14 +-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/include/uapi
Hi Yixun,
On Wed, 13 Jun 2018 16:13:13 +
Yixun Lan wrote:
> From: Liang Yang
>
> Add Amlogic NAND controller dt-bindings for Meson SoC,
> Current this driver support GXBB/GXL/AXG platform.
>
> Signed-off-by: Liang Yang
> Signed-off-by: Yixun Lan
> ---
> .../bindings/mtd/amlogic,meson-n
Hi Yixun,
On Wed, 13 Jun 2018 16:13:14 +
Yixun Lan wrote:
> From: Liang Yang
>
> Add initial support for the Amlogic NAND flash controller which found
> in the Meson-GXBB/GXL/AXG SoCs.
>
> Singed-off-by: Liang Yang
> Signed-off-by: Yixun Lan
> ---
> drivers/mtd/nand/raw/Kconfig
ase() being used here. As I said in my review of
v6, it's not safe. Please use mtd_device_unregister() + nand_cleanup()
instead, and check the return code of mtd_device_unregister().
With this addressed
Reviewed-by: Boris Brezillon
> +
> + clk_disable_unprepare(ctrl->clk);
> +
> + return 0;
> +}
> +
Hi Tudor,
Just one minor comment, I'll let Marek review the patch in more details.
On Fri, 8 Jun 2018 16:48:18 +0300
Tudor Ambarus wrote:
> /*
> * Erase an address range on the nor chip. The address range may extend
> * one or more erase sectors. Return an error is there is a problem era
On Wed, 20 Jun 2018 11:16:11 -0700
Kees Cook wrote:
> On Wed, Jun 20, 2018 at 12:38 AM, Boris Brezillon
> wrote:
> > Hi Kees,
> >
> > On Tue, 19 Jun 2018 16:48:17 -0700
> > Kees Cook wrote:
> >
> >> On Fri, Jun 1, 2018 at 4:09 AM, Ivan Djelic
&g
Hi Naga,
Subject prefix should be "dt-bindings: memory: " not "Devicetree: ".
On Thu, 21 Jun 2018 12:12:28 +0530
Naga Sureshkumar Relli wrote:
> Add pl353 static memory controller devicetree binding information.
>
> Signed-off-by: Naga Sureshkumar Relli
> ---
> Changes in v10:
> - Corrected
On Thu, 21 Jun 2018 12:12:30 +0530
Naga Sureshkumar Relli wrote:
> Added notes about the controller and driver.
>
> Signed-off-by: Naga Sureshkumar Relli
> ---
> Changes in v10:
> - None
> Changes in v9:
> - Addressed the comments given by Miquel and Randy
> Changes in v8
> - None
> Changes
On Mon, 25 Jun 2018 08:56:41 +
Naga Sureshkumar Relli wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Monday, June 25, 2018 2:24 AM
> > To: Naga Sureshkumar Relli
> > Cc:
On Mon, 25 Jun 2018 09:50:18 -0500
Dinh Nguyen wrote:
> On 06/22/2018 10:58 AM, Richard Weinberger wrote:
> > Masahiro,
> >
> > Am Freitag, 22. Juni 2018, 16:37:21 CEST schrieb Masahiro Yamada:
> >> Hi Richard,
> >>
> >>
> >> 2018-06-19 21:07 GMT+09:00 Richard Weinberger :
> >>> The denali N
On Mon, 27 Aug 2018 16:01:41 +0900
Masahiro Yamada wrote:
> Commit 49aa76b16676 ("mtd: rawnand: do not execute nand_scan_ident()
> if maxchips is zero") gave a new meaning for calling nand_scan_ident()
> with maxchips=0.
>
> It is a special usage for some drivers such as docg4, but actually
> th
Hi Gustavo,
On Thu, 23 Aug 2018 20:09:38 -0500
"Gustavo A. R. Silva" wrote:
> One of the more common cases of allocation size calculations is finding
> the size of a structure that has a zero-sized array at the end, along
> with memory for some number of elements for that array. For example:
>
On Sat, 18 Aug 2018 17:14:23 +0800
Liu Xiang wrote:
> If the size of spi-nor flash is larger than 16MB, the read_opcode
> is set to SPINOR_OP_READ_1_1_4_4B, and fsl_qspi_get_seqid() will
> return -EINVAL when cmd is SPINOR_OP_READ_1_1_4_4B. This can
> cause read operation fail.
>
> Signed-off-by
> Fixes: f88fc122cc34 ("mtd: nand: Cleanup/rework the atmel_nand driver")
> Cc: stable # 4.11
> Cc: Nicolas Ferre
> Cc: Josh Wu
> Cc: Boris Brezillon
> Signed-off-by: Johan Hovold
Acked-by: Boris Brezillon
I'll let Miquel queue this patch to the nand/next b
On Mon, 27 Aug 2018 10:44:14 +0200
Johan Hovold wrote:
> On Mon, Aug 27, 2018 at 10:28:20AM +0200, Boris Brezillon wrote:
> > Hi Johan
> >
> > On Mon, 27 Aug 2018 10:21:49 +0200
> > Johan Hovold wrote:
> >
> > > Use the new of_get_compatible_child()
On Mon, 27 Aug 2018 23:02:29 +0800 (CST)
liuxiang wrote:
> Fixes:e46ecda764dc37f9fc6279d95ea2c007daef1a71("mtd: spi-nor: Add Freescale
> QuadSPI driver")
12 digits should be enough for the commit-id.
> Cc: sta...@vger.kernel.org
>
> Should I send a V2 patch that adds these above？
Yes please
On Thu, 23 Aug 2018 23:43:45 +0200
Geert Uytterhoeven wrote:
> If gcc (e.g. 4.1.2) decides not to inline init_mtd_structs() and
> read_id_reg(), this will cause section mismatches, and crashes:
>
> WARNING: drivers/mtd/nand/raw/docg4.o(.text+0xc10): Section mismatch in
> reference from the
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