Hi Ben,
Thanks for the detailed response!
On Fri, Oct 16, 2015 at 11:56:28AM -0500, Ben Shelton wrote:
> Hi Bjorn,
>
> > What problem does this patch solve, Ben? I assume you have devices
> > that do change TotalVFs when ARI is enabled, and you do want the new
> > value?
> >
> > Or is the prob
stride values, so there's no need to read the capability again in
sriov_enable().
Remove the PCI_SRIOV_VF_OFFSET and PCI_SRIOV_VF_STRIDE config reads from
sriov_enable() and use the cached values from the pci_sriov structure.
Signed-off-by: Bjorn Helgaas
---
drivers/pci/iov.c |
On Fri, Oct 02, 2015 at 11:25:05AM +0100, Phil Edworthy wrote:
> The R-Car PCIe host controller driver uses pci_common_init_dev(),
> which is ARM-specific and requires the ARM struct hw_pci. The part of
> pci_common_init_dev() that is needed is limited and can be done here
> without using hw_pci.
>
On Fri, Oct 02, 2015 at 11:25:03AM +0100, Phil Edworthy wrote:
> Fixes and changes to get PCIe working on ARM64 with mulitple instances.
>
> I've tested these on ARM (Koelsch board), and it works fine.
> I've also tested on ARM64 (Salvator-X board), but I currently have an issue
> with inbound PCI
On Thu, Oct 08, 2015 at 02:38:22PM -0700, Yinghai Lu wrote:
> We register regions for legacy and iommu and all have open code.
>
> Unify them to pci_register_region() and call it accordingly.
>
> Signed-off-by: Yinghai Lu
> ---
> arch/sparc/kernel/pci_common.c | 83
> +++---
On Tue, Oct 20, 2015 at 03:30:44PM -0700, Yinghai Lu wrote:
> On Tue, Oct 20, 2015 at 3:16 PM, Yinghai Lu wrote:
> > On Tue, Oct 20, 2015 at 2:57 PM, Bjorn Helgaas wrote:
> >> On Thu, Oct 08, 2015 at 02:38:22PM -0700, Yinghai Lu wrote:
> >>> We register regions for
s.
> - Add patch 5/5 to handle EA provisioned bridges.
>
> Changes from V4 (By David Daney):
> - Drop patch 5/5 to handle EA provisioned bridges.
> - Drop cases for bridge resources in 2/5.
> - Drop unnecessary fallback resource parent handling in 3/5
>
On Fri, Oct 09, 2015 at 12:23:34PM +0200, Joerg Roedel wrote:
> From: Joerg Roedel
>
> The pcibios-irq and MSI both use dev->irq to store the IRQ
> number. While the MSI code checks for that and frees the
> pcibios-irq before overwriting dev->irq, the
> pcibios_alloc_irq function does not.
>
> U
On Wed, Oct 21, 2015 at 11:16:53AM -0700, Yinghai Lu wrote:
> On Tue, Oct 20, 2015 at 7:35 PM, Bjorn Helgaas wrote:
> > On Tue, Oct 20, 2015 at 03:30:44PM -0700, Yinghai Lu wrote:
> > I doubt I would agree with a change like this, but maybe, if you can
> > explain what
Hi Guenter,
On Mon, Oct 12, 2015 at 12:10:13PM -0700, Guenter Roeck wrote:
> Some oddball devices may experience a PCIe link flap after power-on.
> This may result in the following sequence of events.
>
> fpc0 kernel: pciehp :02:08.0:pcie24: Card present on Slot(0)
> fpc0 kernel: pciehp :
On Mon, Oct 12, 2015 at 12:10:12PM -0700, Guenter Roeck wrote:
> Up to now, work items to be queued to be handled by pciehp_power_thread()
> are allocated using kmalloc() in three different locations. If not needed,
> kfree() is called to free the allocated data.
>
> Introduce a separate function
Hi Ley,
I'm ignoring this series for now because of the build errors reported by
the kbuild test robot.
Bjorn
On Wed, Oct 14, 2015 at 02:31:40PM +0800, Ley Foon Tan wrote:
> This is 2nd version of patch to add pci support for nios2 architecture.
> This patchset also update asm-generic/pci.h to i
On Thu, Oct 15, 2015 at 02:31:16PM -0500, Bjorn Helgaas wrote:
> On Thu, Oct 08, 2015 at 10:20:17AM -0500, Ben Shelton wrote:
> > For some SR-IOV devices, the number of available virtual functions increases
> > after enabling ARI. Currently, SRIOV_NUM_VF is read and saved off
On Thu, Oct 15, 2015 at 12:16:00PM -0500, Bjorn Helgaas wrote:
> Hi Ethan,
>
> On Wed, Sep 16, 2015 at 12:19:53PM +0900, Ethan Zhao wrote:
> > After commit 4449f079722c ("PCI: Calculate maximum number of buses
> > required for VFs"),the initial value of NumVFs re
Hi Zhou & Gabriele,
On Fri, Oct 16, 2015 at 06:23:36PM +0800, Zhou Wang wrote:
> From: gabriele paoloni
>
> Commit f4c55c5a3f7f ("PCI: designware: Program ATU with untranslated
> address") added the calculation of PCI BUS addresses in designware,
> storing them in new fields added in "struct pci
Hi Gabriele,
On Thu, Oct 22, 2015 at 07:21:41AM +, Gabriele Paoloni wrote:
> > -Original Message-
> > From: Bjorn Helgaas [mailto:helg...@kernel.org]
> > > #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
&g
Hi Zhou,
On Fri, Oct 16, 2015 at 06:23:38PM +0800, Zhou Wang wrote:
> This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
> function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci,
> move related operations to dw_pcie_host_init.
>
> This patch also try
Hi Zhou,
This looks pretty good to me; just a mask question and add a printk.
On Fri, Oct 16, 2015 at 06:23:39PM +0800, Zhou Wang wrote:
> This patch adds PCIe host support for HiSilicon SoC Hip05.
> ...
> +#define PCIE_SUBCTRL_SYS_STATE4_REG 0x6818
> +#define PCIE_LTSSM_LINK
On Fri, Oct 16, 2015 at 12:04:04PM -0700, Florian Fainelli wrote:
> The header of pcie-iproc.c contains an obvious typo on Broadcom
> Corporation, fix that.
>
> Signed-off-by: Florian Fainelli
Applied with Ray's ack to pci/host-iproc for v4.4, thanks, Florian!
> ---
> drivers/pci/host/pcie-ipr
On Fri, Oct 16, 2015 at 04:16:28PM -0500, Bjorn Helgaas wrote:
> Previously, we read PCI_SRIOV_VF_OFFSET and PCI_SRIOV_VF_STRIDE from the
> SR-IOV capability in pci_iov_set_numvfs() after changing PCI_SRIOV_NUM_VF,
> and we read them again in sriov_enable(). But sriov_init() alw
On Thu, Oct 22, 2015 at 05:27:27PM +0800, Ley Foon Tan wrote:
> Signed-off-by: Ley Foon Tan
> ---
> include/linux/pci_ids.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index d9ba49c..08e4462 100644
> --- a/include/linux/pci_ids.h
On Wed, Sep 2, 2015 at 12:46 PM, Sean O. Stalley wrote:
> Would it be better to modify pci_claim_resource() to support EA instead of
> adding pci_ea_claim_resource()?
> That way, EA entries would be claimed at the same time as traditional BARs.
Yes, I think so.
Why wouldn't pci_claim_resource(
On Wed, Sep 02, 2015 at 01:01:27PM -0700, Sean O. Stalley wrote:
> On Wed, Sep 02, 2015 at 02:25:50PM -0500, Bjorn Helgaas wrote:
> > On Wed, Sep 2, 2015 at 12:46 PM, Sean O. Stalley
> > wrote:
> >
> > > Would it be better to modify pci_claim_resource() to suppo
On Fri, Aug 14, 2015 at 04:08:10PM -0500, Rob Herring wrote:
> On Fri, Aug 14, 2015 at 11:19 AM, Marc Zyngier wrote:
> > Both pci-host-generic and Pseries parse the "linux,pci-probe-only"
> > to engage the PCI_PROBE_ONLY mode, and both have a subtle bug that
> > can be triggered if the property ha
On Wed, Sep 2, 2015 at 5:01 PM, Daniel Drake wrote:
> Hi,
>
> Working with a sample for a new laptop based on Intel Skylake, the
> kernel logs are full of these messages:
>
> pcieport :00:1c.5: AER: Corrected error received: id=00e5
> pcieport :00:1c.5: PCIe Bus Error: severity=Corrected
On Wed, Sep 02, 2015 at 05:29:38PM -0700, Sean O. Stalley wrote:
> On Wed, Sep 02, 2015 at 04:21:59PM -0500, Bjorn Helgaas wrote:
> > On Wed, Sep 02, 2015 at 01:01:27PM -0700, Sean O. Stalley wrote:
> > > On Wed, Sep 02, 2015 at 02:25:50PM -0500, Bjorn Helgaas wrote:
> > &g
[+cc Geert]
On Fri, Oct 02, 2015 at 11:25:03AM +0100, Phil Edworthy wrote:
> Fixes and changes to get PCIe working on ARM64 with mulitple instances.
>
> I've tested these on ARM (Koelsch board), and it works fine.
> I've also tested on ARM64 (Salvator-X board), but I currently have an issue
> wit
On Tue, Oct 13, 2015 at 06:53:28PM -0500, Suravee Suthikulanit wrote:
> Bjorn / Rafael,
>
> On 10/13/2015 10:52 AM, Suravee Suthikulpanit wrote:
> >
> >On 09/14/2015 09:34 AM, Bjorn Helgaas wrote:
> >>[..]
> >>I think acpi_check_dma_coherency() is better, b
On Tue, Oct 20, 2015 at 08:00:10AM +, Phil Edworthy wrote:
> Hi Geert,
>
> On 20 October 2015 08:37, Geert wrote:
> > On Tue, Oct 20, 2015 at 3:36 AM, Simon Horman wrote:
> > > On Mon, Oct 19, 2015 at 06:16:34PM -0500, Bjorn Helgaas wrote:
> > >> [+cc
Hi David,
On Tue, Oct 06, 2015 at 04:50:35PM -0700, David Daney wrote:
> From: "Sean O. Stalley"
>
> Add registers defined in PCI-SIG's Enhanced allocation ECN.
>
> Signed-off-by: Sean O. Stalley
> [david.da...@cavium.com: Added more definitions for PCI_EA_BEI_*]
> Signed-off-by: Signed-off-by
On Tue, Oct 06, 2015 at 04:50:36PM -0700, David Daney wrote:
> From: "Sean O. Stalley"
>
> Add support for devices using Enhanced Allocation entries instead of BARs.
> This patch allows the kernel to parse the EA Extended Capability structure
> in PCI configspace and claim the BAR-equivalent reso
On Tue, Oct 06, 2015 at 04:50:37PM -0700, David Daney wrote:
> From: David Daney
>
> The new Enhanced Allocation (EA) capability support creates resources
> with the IORESOURCE_PCI_FIXED set. This causes a couple of problems:
>
> 1) Since these resources cannot be relocated or resized, their
>
0-0x8007]
(bus address [0x1-0x7])
pci :00:01.0: bridge window [mem 0x8001-0x8004afff
64bit pref]
[bhelgaas: changelog, URL to David's report]
Fixes: d63e2e1f3df9 ("sparc/PCI: Clip bridge windows to fit in upstream
windows"
On Thu, Oct 08, 2015 at 02:38:21PM -0700, Yinghai Lu wrote:
> After we add 64bit mmio parsing, we got some "no compatible bridge window"
> warning on anther new model that support 64bit resource.
>
> It turns out that we can not use mem_space.start as 64bit mem space
> offset, aka mem_space.start
On Thu, Oct 08, 2015 at 02:38:21PM -0700, Yinghai Lu wrote:
> After we add 64bit mmio parsing, we got some "no compatible bridge window"
> warning on anther new model that support 64bit resource.
>
> It turns out that we can not use mem_space.start as 64bit mem space
> offset, aka mem_space.start
Hi Ley,
On Thu, Oct 22, 2015 at 05:27:28PM +0800, Ley Foon Tan wrote:
> This patch adds the Altera PCIe host controller driver.
> +static void altera_pcie_fixups(struct pci_bus *bus)
> +{
> + struct pci_dev *dev;
> +
> + list_for_each_entry(dev, &bus->devices, bus_list) {
> +
On Thu, Oct 22, 2015 at 02:47:42PM +1100, Benjamin Herrenschmidt wrote:
> On Wed, 2015-10-21 at 18:27 -0700, David Miller wrote:
> > From: Yinghai Lu
> > Date: Wed, 21 Oct 2015 11:16:53 -0700
> >
> > > otherwise we need to compare res with pbm->mem_space or pbm
> > ->mem64_space
> > > to get dire
PCI fixes:
- Fix integer overflow in new mobiveil driver (Dan Carpenter)
- Fix race during NVMe removal/rescan (Hari Vyas)
The following changes since commit bd91b56cb3b27492963caeb5fccefe20a986ca8d:
PCI/AER: Work around use-after-free in pcie_do_fatal_recovery() (2018-07-26
12:13:04 -0
On Mon, Aug 6, 2018 at 1:39 PM wrote:
>
> On 08/05/2018 02:06 AM, Tal Gilboa wrote:
> > On 7/31/2018 6:10 PM, Alex G. wrote:
> >> On 07/31/2018 01:40 AM, Tal Gilboa wrote:
> >> [snip]
> >> @@ -2240,6 +2258,9 @@ static void pci_init_capabilities(struct
> >> pci_dev *dev)
> >>/*
On Wed, Aug 01, 2018 at 11:05:09AM -0700, Sinan Kaya wrote:
> On 8/1/2018 9:44 AM, Bharat Kumar Gogada wrote:
> > Xilinx ZynqMP PS PCIe does not report AER interrupts using Advanced
> > Error Interrupt Message Number. The controller has dedicated interrupt line
> > for reporting PCIe errors along w
On Wed, Aug 01, 2018 at 10:14:48PM +0530, Bharat Kumar Gogada wrote:
> Xilinx ZynqMP PS PCIe does not report AER interrupts using Advanced
> Error Interrupt Message Number. The controller has dedicated interrupt line
> for reporting PCIe errors along with AER.
>
> Using pci_dev->sysdata of root po
he IOAPIC is
"higher priority" than the bridge window? This is the reverse of what
your paragraph seems to say.
> This patch claims the resources of firmware enabled IOAPIC before
> children bus. Then kernel gets a chance to reassign the resources of
> children bus to avoid the confli
On Mon, Jul 30, 2018 at 06:35:31PM -0500, Alexandru Gagniuc wrote:
> When we don't own AER, we shouldn't touch the AER error bits. Clearing
> error bits willy-nilly might cause firmware to miss some errors. In
> theory, these bits get cleared by FFS, or via ACPI _HPX method. These
> mechanisms are
, maybe we should add a comment in the kernel and a
note in the lspci man page).
I'm not sure yet where to go beyond that.
On Wed, May 30, 2018 at 07:41:35AM -0700, Bjorn Helgaas wrote:
> [+cc linux-pci, linux-kernel, linux-pm]
>
> I'm not sure I understand the problem yet
[+cc Alex]
On Tue, Jun 19, 2018 at 06:21:43PM -0400, Sinan Kaya wrote:
> On 6/19/2018 5:43 PM, Bjorn Helgaas wrote:
> >> Hotplug driver removes the device from system when a link down interrupt
> >> is observed and performs re-enumeration when link up interrupt is obs
hings up so they make a
little more sense.
Bjorn
commit 7780896578a93fdec2b345def554355168cceee4
Author: Bjorn Helgaas
Date: Mon Jun 25 08:17:33 2018 -0500
PCI: shpchp: Manage SHPC unconditionally on non-ACPI systems
If CONFIG_ACPI=y but the current hardware/firmware platform doesn
[+cc EDAC folks, LKML]
On Sat, Aug 25, 2018 at 10:58:57PM +0800, Zihan Yang wrote:
> Hi all,
>
> I'm trying to use multiple pci domain in qemu q35, but I find there
> might be some issues in peer bridge fixup.
>
> In short, pcibios_fixup_peer_bridges function assumes only one pci
> domain (0) by
[+cc linux-pci, linux-kernel]
On Thu, Aug 2, 2018 at 9:33 AM Lorenzo Pieralisi
wrote:
>
> On Wed, Aug 01, 2018 at 02:38:51PM -0500, Jeremy Linton wrote:
> > Hi,
> >
> > +CC Jiang Lui
>
> Jiang Liu does not work on the kernel anymore so we won't know
> anytime soon the reasoning behind commit 965c
On Wed, Aug 08, 2018 at 03:44:03PM +0100, Punit Agrawal wrote:
> Bjorn Helgaas writes:
> > On Thu, Aug 2, 2018 at 9:33 AM Lorenzo Pieralisi
> > wrote:
> >> On Wed, Aug 01, 2018 at 02:38:51PM -0500, Jeremy Linton wrote:
> >>
> >> Jiang Liu does not w
On Wed, Aug 08, 2018 at 01:48:37PM +0800, AceLan Kao wrote:
> There are some 0 resource size pci devices, and it leads to the
> accumulator fails to maintain the correct value.
> It results in a strange issue on my machine that xhci_hcd failed to init.
>[2.437278] xhci_hcd :05:00.0: ini
I think sb_edac.c (and probably other EDAC stuff) lacks PCI domain
support. I notice messages like this:
[ 14.370256] pci :ff:13.5: [8086:6fad] type 00 class 0x088000
[ 14.980481] pci :bf:13.5: [8086:6fad] type 00 class 0x088000
[ 15.590646] pci :7f:13.5: [8086:6fad] type
On Wed, Aug 08, 2018 at 11:53:18PM +0800, joeyli wrote:
> Hi Bjorn,
>
> First, thanks for your review!
>
> On Mon, Aug 06, 2018 at 04:48:07PM -0500, Bjorn Helgaas wrote:
> > On Tue, Jul 24, 2018 at 07:01:44PM +0800, Lee, Chun-Yi wrote:
> > > I got a machine that th
On Tue, Jul 17, 2018 at 10:31:23AM -0500, Alexandru Gagniuc wrote:
> When we don't own AER, we shouldn't touch the AER error bits. This
> happens unconditionally on device probe(). Clearing AER bits
> willy-nilly might cause firmware to miss errors. Instead
> these bits should get cleared by FFS, o
On Thu, Aug 09, 2018 at 04:46:32PM +, alex_gagn...@dellteam.com wrote:
> On 08/09/2018 09:16 AM, Bjorn Helgaas wrote:
> > On Tue, Jul 17, 2018 at 10:31:23AM -0500, Alexandru Gagniuc wrote:
> >> When we don't own AER, we shouldn't touch the AER error bits. This
>
On Thu, Aug 09, 2018 at 02:00:23PM -0500, Alex G. wrote:
> On 08/09/2018 01:29 PM, Bjorn Helgaas wrote:
> > On Thu, Aug 09, 2018 at 04:46:32PM +, alex_gagn...@dellteam.com wrote:
> > > On 08/09/2018 09:16 AM, Bjorn Helgaas wrote:
> (snip_
> > &
On Tue, Jul 24, 2018 at 10:18:48AM -0600, Alex Williamson wrote:
> On Tue, 24 Jul 2018 10:14:46 -0600
> Alex Williamson wrote:
>
> > Add a device specific reset for Intel DC P3700 NVMe device which
> > exhibits a timeout failure in drivers waiting for the ready status to
> > update after NVMe ena
On Thu, Aug 09, 2018 at 02:04:03PM -0600, Alex Williamson wrote:
> v4: Fix 0-day i386 build error for readq, simply use readl
> instead, the bits we're interested in are 24:31 and the NVMe
> spec indicates that smaller, aligned accesses are allowed.
> Update bz links for both device spe
On Mon, Jul 30, 2018 at 10:18:36AM -0600, Logan Gunthorpe wrote:
> Changes since v6:
> * Fixed order of operations for device specific disable function as
> noticed by Alex
> * Rebased onto v4.18-rc5 (no conflicts)
>
> Changes since v5:
> * Add a quirk to handle the Intel SPT PCH case (as pointe
On Fri, Aug 10, 2018 at 05:25:01PM +0800, joeyli wrote:
> On Wed, Aug 08, 2018 at 04:23:22PM -0500, Bjorn Helgaas wrote:
> ...
> The lspci log shows "Normal decode" on the bridge, I think that means
> positively decode.
Right.
> hm... I have another question that i
On Sun, Aug 12, 2018 at 08:15:45AM +0800, joeyli wrote:
> On Fri, Aug 10, 2018 at 08:58:37AM -0500, Bjorn Helgaas wrote:
> > On Fri, Aug 10, 2018 at 05:25:01PM +0800, joeyli wrote:
> > > On Wed, Aug 08, 2018 at 04:23:22PM -0500, Bjorn Helgaas wrote:
> > > ...
> [...sn
uthor: Bjorn Helgaas
Date: Mon Aug 13 14:30:41 2018 -0500
PCI: Add function 1 DMA alias quirk for Marvell 88SS9183
Add function 1 DMA alias quirk for Marvell 88SS9183 PCIe SSD Controller.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134
Reported-by:
Signe
ids.h
> @@ -511,6 +511,8 @@
> #define PCI_DEVICE_ID_AMI_MEGARAID 0x9010
> #define PCI_DEVICE_ID_AMI_MEGARAID2 0x9060
>
> +#define PCI_VENDOR_ID_HYGON 0x1d94
Please add this entry so pci_ids.h remains sorted by Vendor ID, then Device
ID, as the comment at the top suggests.
With t
[+cc Mizuma-san, linux-pci]
On Wed, Aug 08, 2018 at 08:18:03PM +, Luck, Tony wrote:
> > I think sb_edac.c (and probably other EDAC stuff) lacks PCI domain
> > support
>
> There's a patch queued to fix this.
>
> https://marc.info/?l=linux-edac&m=153256485215534&w=2
That's excellent, thank
On Mon, Aug 13, 2018 at 02:41:23PM -0500, Bjorn Helgaas wrote:
> Hi,
>
> Thanks a lot for your new report
> (https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134).
>
> Can you confirm that the patch below is equivalent to what you tested and
> it resolves the problem
[+cc Rajat, Ashok]
On Tue, Aug 21, 2018 at 09:25:41AM +0200, Lukas Wunner wrote:
> On Tue, Aug 21, 2018 at 07:47:04AM +0200, Lukas Wunner wrote:
> > On Mon, Aug 20, 2018 at 06:06:24PM -0500, Bjorn Helgaas wrote:
> > > mmyan...@gmail.com reported a problem [1]: on v4.17
On Fri, Aug 24, 2018 at 12:16:20PM +, Bharat Kumar Gogada wrote:
> > Subject: [PATCH 0/4] Add support to register platform service IRQ
> >
> > Some platforms have dedicated IRQ lines for PCIe services like AER/PME etc.
> > The root complex on these platform will use these seperate IRQ lines to
PCI fixes:
- Fix a use-after-free error in fatal error recovery (Thomas Tai)
The following changes since commit 270ed733e68955049b693bea8f4a1efb293a96ae:
PCI: v3-semi: Fix I/O space page leak (2018-07-18 17:02:13 -0500)
are available in the Git repository at:
ssh://g...@gitolite.kernel.
[+cc Rafael, Richard, Carlos, Pali, Takashi, Andy, Colin for question
about how to expose ASPM power management in sysfs]
On Thu, May 10, 2018 at 04:39:12PM -0700, Rajat Jain wrote:
> ...
> And some suggestions from Bjorn here:
> https://www.spinics.net/lists/linux-pci/msg60541.html
>
> This patc
On Wed, Jul 04, 2018 at 11:40:52AM +0200, Rafael J. Wysocki wrote:
> On Fri, Jun 29, 2018 at 10:27 PM, Bjorn Helgaas wrote:
> > From: Bjorn Helgaas
> >
> > Add a writeup about how PCI host bridges should be described in ACPI
> > using PNP0A03/PNP0A08 devices, PNP0C02
On Sat, Jul 28, 2018 at 05:16:13PM -0700, Sinan Kaya wrote:
> On 7/27/2018 1:26 PM, Bjorn Helgaas wrote:
> > - A link can lead to a multi-function device, and the spec allows
> > those functions to have different ASPM settings (see PCIe r4.0,
> > sec 5.4.1). With t
On Mon, Jul 30, 2018 at 10:32:10AM +0200, Lukas Wunner wrote:
> On Fri, Jul 27, 2018 at 03:26:19PM -0500, Bjorn Helgaas wrote:
> > The question is where those sysfs files should be. Currently they are
> > associated with the device at the *upstream* end of the link. In the
&g
On Fri, Jun 22, 2018 at 05:58:14AM -0400, Oza Pawandeep wrote:
> We are handling ERR_FATAL by resetting the Link in software,skipping the
> driver pci_error_handlers callbacks, removing the devices from the PCI
> subsystem, and re-enumerating, because of, no need to handle
> pci_channel_io_frozen c
completely?
[1]
https://lkml.kernel.org/r/1529661494-20936-1-git-send-email-p...@codeaurora.org
[2]
https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git/?h=pci/06-22-oza-aer
---
Bjorn Helgaas (1):
PCI/AER: Clear only ERR_FATAL status bits during fatal recovery
Oza Pawandeep (6):
From: Oza Pawandeep
aer_error_resume() clears all ERR_NONFATAL error status bits. This is
exactly what pci_cleanup_aer_uncorrect_error_status(), so use that instead
of duplicating the code.
Signed-off-by: Oza Pawandeep
[bhelgaas: split to separate patch]
Signed-off-by: Bjorn Helgaas
From: Bjorn Helgaas
During recovery from fatal errors, we previously called
pci_cleanup_aer_uncorrect_error_status(), which cleared *all* uncorrectable
error status bits (both ERR_FATAL and ERR_NONFATAL).
Instead, call a new pci_aer_clear_fatal_status() that clears only the
ERR_FATAL bits (as
tatus bits.
Signed-off-by: Oza Pawandeep
[bhelgaas: split to separate patch]
Signed-off-by: Bjorn Helgaas
---
drivers/pci/pcie/aer.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index 5b4a84e3d360..6f0f131b5e6a 100644
From: Oza Pawandeep
broadcast_error_message() is only used for ERR_NONFATAL events, when the
state is always pci_channel_io_normal, so remove the unused alternate path.
Signed-off-by: Oza Pawandeep
[bhelgaas: changelog]
Signed-off-by: Bjorn Helgaas
---
drivers/pci/pcie/err.c | 11
From: Oza Pawandeep
Clear the device status bits while handling both ERR_FATAL and ERR_NONFATAL
cases.
Signed-off-by: Oza Pawandeep
[bhelgaas: rename to pci_aer_clear_device_status(), declare internal to PCI
core instead of exposing it everywhere]
Signed-off-by: Bjorn Helgaas
---
drivers/pci
From: Oza Pawandeep
In case of correctable error, the Correctable Error Detected bit in the
Device Status register is set. Clear it after handling the error.
Signed-off-by: Oza Pawandeep
Signed-off-by: Bjorn Helgaas
---
drivers/pci/pcie/aer.c |1 +
1 file changed, 1 insertion(+)
diff
emove pcie_portdrv_slot_reset() completely]
Signed-off-by: Bjorn Helgaas
---
drivers/pci/pcie/portdrv_pci.c | 25 -
1 file changed, 25 deletions(-)
diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c
index 973f1b80a038..b78840f54a9b 100644
--- a/driver
[+cc Mike (hfi1)]
On Mon, Jul 16, 2018 at 10:28:35PM +, alex_gagn...@dellteam.com wrote:
> On 7/16/2018 4:17 PM, Bjorn Helgaas wrote:
> >> ...
> >> The easiest way to detect this is with pcie_print_link_status(),
> >> since the bottleneck is usually the link
On Wed, Jul 18, 2018 at 4:49 PM Stephen Rothwell wrote:
>
> Hi Bjorn,
>
> Commits
>
> 27a6c9ebf29b ("PCI: v3-semi: Fix I/O space page leak")
> db2aff16ea70 ("PCI: mediatek: Fix I/O space page leak")
> 52022fc6f6ad ("PCI: faraday: Fix I/O space page leak")
> a9c0419ec92f ("PCI: aardvark: Fi
On Mon, Jul 02, 2018 at 06:58:54PM -0400, Sinan Kaya wrote:
> pci_reset_bus() and pci_reset_slot() functions are not being used by
> any code. Remove them from the kernel in favor of pci_try_reset_bus()
> and pci_try_reset_slot() functions.
>
> Signed-off-by: Sinan Kaya
> ---
> drivers/pci/pci.c
On Wed, Jul 18, 2018 at 03:36:29PM -0700, Sinan Kaya wrote:
> On 7/18/2018 3:30 PM, Bjorn Helgaas wrote:
> > On Mon, Jul 02, 2018 at 06:58:54PM -0400, Sinan Kaya wrote:
> > > pci_reset_bus() and pci_reset_slot() functions are not being used by
> > > any code. Remove th
PCI fixes:
- Fix crashes that happen when PHY drivers are left disabled in the V3
Semiconductor, MediaTek, Faraday, Aardvark, DesignWare, Versatile,
and X-Gene host controller drivers (Sergei Shtylyov)
- Fix a NULL pointer dereference in the endpoint library configfs support
(Kish
From: Bjorn Helgaas
Fix minor style issues in pci_sriov_set_totalvfs(). No functional change
intended.
Signed-off-by: Bjorn Helgaas
---
drivers/pci/iov.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index d0d73dbbd5ca
On Thu, Jul 19, 2018 at 09:23:47AM +0530, p...@codeaurora.org wrote:
> On 2018-07-19 01:14, Bjorn Helgaas wrote:
> > This is a v3 of Oza's patches [1]. It's available at [2] if you prefer
> > git.
> >
> > v3 changes:
> > - Add pci_aer_clear_f
On Tue, Jul 10, 2018 at 02:30:11PM -0400, Sinan Kaya wrote:
> On Mon, Jul 9, 2018 at 12:00 PM, Lukas Wunner wrote:
> > On Mon, Jul 09, 2018 at 08:48:44AM -0600, Sinan Kaya wrote:
> > > On 7/8/18, Lukas Wunner wrote:
> > > > On Tue, Jul 03, 2018 at 11:43:26AM -0400, Sinan Kaya wrote:
> > > > > My
[+cc Thomas, Christoph, LKML]
On Mon, Jul 30, 2018 at 12:03:42AM +0200, Heiner Kallweit wrote:
> If we have a threaded interrupt with the handler being NULL, then
> request_threaded_irq() -> __setup_irq() will complain and bail out
> if the IRQF_ONESHOT flag isn't set. Therefore check for the hand
On Mon, Jul 30, 2018 at 04:31:36PM +0200, Lukas Wunner wrote:
> On Thu, Jul 12, 2018 at 10:59:46AM -0500, Bjorn Helgaas wrote:
> > But on reflection, I think the overall value of this writeup is
> > minimal. It's a lot of repetition of things already documented
> > else
[+cc maintainers of possibly erroneous callers of request_threaded_irq()]
On Mon, Jul 30, 2018 at 04:30:28PM -0500, Bjorn Helgaas wrote:
> [+cc Thomas, Christoph, LKML]
>
> On Mon, Jul 30, 2018 at 12:03:42AM +0200, Heiner Kallweit wrote:
> > If we have a threaded interrupt with th
On Tue, Jul 31, 2018 at 09:01:12AM +0100, Russell King - ARM Linux wrote:
> On Tue, Jul 31, 2018 at 12:50:21AM +0200, Thomas Gleixner wrote:
> > On Mon, 30 Jul 2018, Bjorn Helgaas wrote:
> >
> > > [+cc maintainers of possibly erroneous callers of request_threaded_irq()]
On Thu, Jul 12, 2018 at 08:15:19PM +0530, Bharat Kumar Gogada wrote:
> Currently PCI_BRIDGE_CTL_SERR is being enabled only in
> ACPI flow.
> This bit is required for forwarding errors reported
> by EP devices to upstream device.
> This patch enables SERR# for Type-1 PCI device.
This does seem brok
From: Bjorn Helgaas
PCI_EXP_AER_FLAGS was defined twice (with identical definitions), once
under #ifdef CONFIG_ACPI_APEI, and again at the top level. This looks like
my merge error from these commits:
fd3362cb73de ("PCI/AER: Squash aerdrv_core.c into aerdrv.c")
41cbc9eb1a82
On Wed, Jul 18, 2018 at 09:40:35AM +0800, Shunyong Yang wrote:
> Current DMA direction definitions in pci-dma-compat.h and dma-direction.h
> are mirrored in value. Unifying them to enhance readability and avoid
> possible inconsistency.
>
> Cc: Joey Zheng
> Signed-off-by: Shunyong Yang
Applied
On Sat, Jul 21, 2018 at 11:45:56PM +0200, Anders Roxell wrote:
> When CONFIG_PCI_QUIRKS isn't enabled we get the warning below:
> drivers/pci/probe.c: In function ‘pci_bus_read_dev_vendor_id’:
> drivers/pci/probe.c:2221:18: warning: unused variable ‘bridge’
> [-Wunused-variable]
> struct pci_dev
On Mon, Jul 23, 2018 at 04:24:31PM -0600, Alex Williamson wrote:
> Take advantage of NVMe devices using a standard interface to quiesce
> the controller prior to reset, including device specific delays before
> and after that reset. This resolves several NVMe device assignment
> scenarios with two
[+cc Anders]
On Tue, Jul 24, 2018 at 4:39 AM Arnd Bergmann wrote:
>
> The newly introduced function produces a warning without CONFIG_PCI_QUIRKS:
>
> drivers/pci/probe.c: In function 'pci_bus_read_dev_vendor_id':
> drivers/pci/probe.c:2221:18: error: unused variable 'bridge'
> [-Werror=unused-va
From: Bjorn Helgaas
Several PCI core files include pci-aspm.h even though they don't need
anything provided by that file. Remove the unnecessary includes of it.
Signed-off-by: Bjorn Helgaas
---
drivers/pci/pci-sysfs.c |1 -
drivers/pci/pci.c |1 -
drivers/pci/probe.c |
Remove includes of from files that don't need
it. I'll apply all these via the PCI tree unless there's objection.
---
Bjorn Helgaas (4):
igb: Remove unnecessary include of
ath9k: Remove unnecessary include of
iwlwifi: Remove unnecessary include of
1301 - 1400 of 6735 matches
Mail list logo
