Hi Linus,
Here are a few changes for v4.8. One documentation fix, an Intel VMD IRQ
fix, and two updates to enable Christoph's MSI/legacy IRQ cleanup work.
Bjorn
The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
are availa
On Thu, Aug 25, 2016 at 03:41:35AM +, Yong, Jonathan wrote:
> Export symbol so device drivers outside of the core pci subsystem
> can use it.
>
> Signed-off-by: Yong, Jonathan
> ---
> drivers/pci/pcie/ptm.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pci/pcie/ptm.c b/dr
On Thu, Aug 25, 2016 at 04:03:34PM +0800, Shawn Lin wrote:
> This is a bug of controller found recently which makes the
> default values of L1PwrOnSc and L1PwrOnVal unreliable when
> enabling ASPM. We could work around this by reading L1 substate
> control 2 register and then write back the value a
On Thu, Aug 25, 2016 at 01:59:56PM +0800, Ley Foon Tan wrote:
> Altera PCIe IP can be configured as rootport or device and they might have
> same vendor ID. It will cause the system hang issue if Altera PCIe is in
> endpoint mode and work with other PCIe rootport that from other vendors.
> Moved re
On Fri, Aug 04, 2017 at 08:27:28PM +0530, Srinath Mannam wrote:
> Concurrency issue is observed during pci enable bridge called
> for multiple pci devices initialization in SMP system.
>
> Setup details:
> - SMP system with 8 ARMv8 cores running Linux kernel(4.11).
> - Two EPs are connected to P
On Wed, Aug 16, 2017 at 09:39:08PM +0300, Meelis Roos wrote:
> > > > I noticed that in 4.13.0-rc4 there is a new error in dmesg on my
> > > > sparc64
> > > > t5120 server: can't allocate MSI-X affinity masks.
> > > >
> > > > [ 30.274284] qla2xxx [:00:00.0]-0005: : QLogic Fibre Channel HBA
On Wed, Aug 16, 2017 at 09:33:03PM +0200, Thierry Reding wrote:
> On Tue, Aug 15, 2017 at 12:03:31PM -0500, Bjorn Helgaas wrote:
> > On Tue, Aug 15, 2017 at 11:24:48PM +0800, Ding Tianhong wrote:
> > > Eric report a oops when booting the system after applying
> > > th
T5
> Completion erratum")
> Signed-off-by: Thierry Reding
Acked-by: Bjorn Helgaas
I *think* this should work for everybody, but I can't test it personally.
> ---
> This applies on top of and was tested on next-20170817.
>
> Michael, it'd be great if you could tes
On Fri, Aug 11, 2017 at 12:56:34PM -0400, Sinan Kaya wrote:
> Kernel is hiding Configuration Request Retry Status (CRS) inside
> pci_bus_read_dev_vendor_id() function. We are looking to add support for
> Function Level Reset (FLR) where vendor id read returns ~0.
>
> Move CRS handling into its own
plies an _HPX method that
allows the kernel to enable ECRC.
Only enable ECRC if the device advertises support for it.
Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1571798
Fixes: 1302fcf0d03e ("PCI: Configure *all* devices, not just hot-added ones")
Reported-by: John Mazzie
Hi John,
Any chance you could test this patch?
I think it should fix this old bug report:
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1571798
But I haven't seen any confirmation of it.
Bjorn
On Tue, Jun 20, 2017 at 02:02:07PM -0500, Bjorn Helgaas wrote:
> John reported that
nelle.
>
> Signed-off-by: Bhumika Goyal
Acked-by: Bjorn Helgaas
Please apply this along with the rest of the series, since it depends
on an earlier patch in the series.
> ---
> * Changes in v2- Combine all the followup patches and the constification
> patches into a series.
>
On Sat, Oct 14, 2017 at 03:50:56AM +0800, Jeffy Chen wrote:
> Add support for PCIE_WAKE pin in rockchip pcie driver.
>
> Signed-off-by: Jeffy Chen
> ---
>
> Changes in v6:
> Fix device_init_wake error handling, and add some comments.
>
> Changes in v5:
> Rebase
>
> Changes in v3:
> Fix error h
[+cc David, Manish]
Please use a subject line that tells more about what's going on.
"Update quirk" doesn't really convey any useful information.
Something like "Apply Cavium ThunderX ACS quirk only to Root Ports".
On Wed, Sep 27, 2017 at 11:20:39AM -0700, Vadim Lomovtsev wrote:
> This commit mak
On Fri, Oct 13, 2017 at 06:09:04PM +0200, Niklas Cassel wrote:
> Since it is a PCIe endpoint device, rather than the CPU, that is supposed
> to write to this location, the proper way to get the address to this this
> location is really to use the DMA API, rather than virt_to_phys.
>
> Using virt_t
Would you mind capitalizing the first letter of the changelog summary,
i.e., to follow the convention of "git log --oneline
drivers/pci/dwc/pcie-designware-ep.c"? I usually fix that up
manually, but it saves me time if you do it.
On Fri, Oct 13, 2017 at 06:09:05PM +0200, Niklas Cassel wrote:
> Pr
On Fri, Oct 13, 2017 at 06:09:11PM +0200, Niklas Cassel wrote:
> Signed-off-by: Niklas Cassel
> ---
> .../devicetree/bindings/pci/axis,artpec6-pcie.txt | 3 +-
> drivers/pci/dwc/Kconfig| 41 +++--
> drivers/pci/dwc/Makefile | 4 +-
> dri
On Tue, Sep 26, 2017 at 11:49:19AM -0600, Khuong Dinh wrote:
> This patch set enables ACPI MSI support for X-Gene PCIe v1 hardware
> and provides the proper MSI driver initialization ordering.
>
> Signed-off-by: Khuong Dinh
> ---
> v4:
> - Remove Marc Zyngier ACK in v2
> - Use acpi_bus_scan on
On Sat, Oct 07, 2017 at 02:08:44PM +0200, Bodo-Merle Sandor wrote:
> From: Sandor Bodo-Merle
>
> Add support for allocating multiple MSIs at the same time, so that the
> MSI_FLAG_MULTI_PCI_MSI flag can be added to the msi_domain_info
> structure.
>
> Avoid storing the hwirq in the low 5 bits of
On Wed, Oct 11, 2017 at 02:14:35PM +0530, Kishon Vijay Abraham I wrote:
> This series fixes module removal/insertion cycle of pci_endpoint_test.
>
> Without this series, when trying to modprobe pci_endpoint_test after
> rmmod pci_endpoint_test results in the following errors.
>
> pci-endpoint-tes
s/PCI: dwc: dra7xx: Add support for SoC specific compatible strings/
PCI: dra7xx: Add dra726 and dra746 compatible strings/
I think including "dwc" makes sense for things that involve the DW
core, but this is really dra7xx-specific. And I think the *support*
for SoC-specific strings was alrea
s/PCI: dwc: pci-dra7xx: Enable x2 mode support/
PCI: dra7xx: Enable x2 mode support for dra74x and dra76x/
Looks OK to me otherwise, but Rob had a comment about the DT names, so
I'll wait for that resolution.
On Tue, Oct 10, 2017 at 03:46:06PM +0530, Kishon Vijay Abraham I wrote:
> Perform sysc
c: dra7xx: Create functional dependency between PCIe and PHY
s/PCI: dwc: dra7xx: Create functional dependency between PCIe and PHY/
PCI: dra7xx: Create functional dependency between PCIe and PHY/
Should these be merged together? If it makes sense for you to merge them
together, here's my ack for
PCI fixes:
- fix PCI_ENDPOINT build error (merged for v4.12)
- fix Switchtec driver (merged for v4.12)
- fix imx6 config read timeouts, fallout from changing to non-postable
reads
- add PM "needs_resume" flag for i915 suspend issue
The following changes since commit 2ea659a9ef4881
Hi Srinath,
Thanks for chasing this down! It must have been a real hassle to find
this.
On Mon, May 08, 2017 at 08:39:50PM +0530, Srinath Mannam wrote:
> We found a concurrency issue in NVMe Init when we initialize
> multiple NVMe connected over PCIe switch.
>
> Setup details:
> - SMP system w
Hi Jakub,
On Mon, May 22, 2017 at 03:50:23PM -0700, Jakub Kicinski wrote:
> PCI core sets the driver pointer before calling ->probe() and only
> clears it after ->remove(). This means driver's ->sriov_configure()
> callback will happily race with probe() and remove(), most likely
> leading to BUG
.
> This patch adapts the corresponding code to match the changes introduced
> by LOGIC_IO.
>
> Signed-off-by: zhichang.yuan
> Signed-off-by: Gabriele Paoloni
> Signed-off-by: Arnd Bergmann #earlier draft
Not sure how you plan to merge this, but here's my ack:
On Thu, May 25, 2017 at 12:37:22PM +0100, Gabriele Paoloni wrote:
> From: "zhichang.yuan"
>
> In 'commit 41f8bba7f555 ("of/pci: Add pci_register_io_range() and
> pci_pio_to_address()")' a new I/O space management was supported. With that
> driver, the I/O ranges configured for PCI/PCIE hosts on s
he same time, which is done quite often in the new
> code (and will be done elsewhere going forward too).
>
> Signed-off-by: Rafael J. Wysocki
> Acked-by: Greg Kroah-Hartman
Acked-by: Bjorn Helgaas
> ---
>
> -> v2: Implement the entire handling of DPM_FLAG_SMART_S
On Tue, Oct 24, 2017 at 02:09:14PM +0300, Mika Westerberg wrote:
> During surprise hot-unplug the device is not there anymore. When that
> happens we read 0x from the registers and pciehp_unconfigure_device()
> might inadvertently think the device is a display device because bridge
> contro
On Wed, Oct 18, 2017 at 03:58:16PM +0200, Christian König wrote:
> Hi everyone,
>
> This is the ninth and hopefully last incarnation of this set of patches. It
> enables device drivers to resize and most likely also relocate the PCI BAR of
> devices they manage to allow the CPU to access all of th
On Thu, Oct 19, 2017 at 06:13:29PM +0530, Faiz Abbas wrote:
> Enable support for printing the LTSSM link state for debugging PCI
> when link is down.
>
> Signed-off-by: Faiz Abbas
Applied with Kishon's ack to pci/host-dra7xx for v4.15, thanks!
I tweaked the "link up" testing as follows (what I
On Thu, Oct 12, 2017 at 09:27:57AM +0530, Pankaj Dubey wrote:
> controller_group allocation in pci_ep_cfs_init function can fail
> so we should have a check while using it in pci_ep_cfs_add_epc_group
> for registering group, else we will hit NULL pointer access.
>
> This patch adds required check
Include "PCIe WAKE#" signal in the subject, since this is specifically
about that wire.
On Mon, Oct 23, 2017 at 04:02:53PM -0700, Brian Norris wrote:
> + PM folks
>
> Hi Jeffy,
>
> It's probably good if you send the whole thing to linux-pm@ in the
> future, if you're really trying to implement g
On Mon, Oct 23, 2017 at 07:59:58PM +0200, Romain Perier wrote:
> From: Romain Perier
>
> Now that all the drivers use dma pool API, we can remove the macro
> functions for PCI pool.
>
> Signed-off-by: Romain Perier
> Reviewed-by: Peter Senna Tschudin
Acked-by: Bjorn
Run "git log --oneline drivers/pci/host" and make yours match, e.g.,
s/PCI: host: brcmstb: Broadcom PCIe Host Controller/
PCI: brcmstb: Add Broadcom STB PCIe host controller driver/
On Tue, Oct 24, 2017 at 02:15:44PM -0400, Jim Quinlan wrote:
> This commit adds the basic Broadcom STB PCIe contr
On Tue, Oct 24, 2017 at 02:15:47PM -0400, Jim Quinlan wrote:
> This commit adds MSI to the Broadcom STB PCIe host controller. It does
> not add MSIX since that functionality is not in the HW. The MSI
> controller is physically located within the PCIe block, however, there
> is no reason why the MS
On Wed, Oct 25, 2017 at 01:51:53PM +0530, Faiz Abbas wrote:
> Bjorn,
>
> On Wednesday 25 October 2017 01:29 AM, Bjorn Helgaas wrote:
> > On Thu, Oct 19, 2017 at 06:13:29PM +0530, Faiz Abbas wrote:
> >> Enable support for printing the LTSSM link state for debugging PC
[+cc Alex]
On Mon, Oct 23, 2017 at 05:36:48PM -0400, Sinan Kaya wrote:
> The return codes from various reset types are not consistent. The code is
> assuming that all reset types will return -ENOTTY when things go wrong.
> Instead of relying on negative error status, let's bail out if the
> operat
On Wed, Oct 11, 2017 at 03:35:56PM -0600, Alex Williamson wrote:
> When removing a device, for example a VF being removed due to SR-IOV
> teardown, a "soft" hot-unplug via 'echo 1 > remove' in sysfs, or an
> actual hot-unplug, we first remove the procfs and sysfs attributes
> for the device before
[+cc Ray, Scott, Jon]
On Wed, Oct 25, 2017 at 11:28:07AM -0400, Jim Quinlan wrote:
> On Tue, Oct 24, 2017 at 2:57 PM, Florian Fainelli
> wrote:
> > Hi Jim,
> >
> > On 10/24/2017 11:15 AM, Jim Quinlan wrote:
> >> This commit adds MSI to the Broadcom STB PCIe host controller. It does
> >> not add
On Wed, Oct 25, 2017 at 11:40:47AM -0700, Scott Branden wrote:
> Hi Bjorn,
>
>
> On 17-10-25 10:23 AM, Bjorn Helgaas wrote:
> >[+cc Ray, Scott, Jon]
> >
> >On Wed, Oct 25, 2017 at 11:28:07AM -0400, Jim Quinlan wrote:
> >>On Tue, Oct 24, 2017 at 2:57 PM, Fl
On Wed, Oct 25, 2017 at 11:28:05PM +0200, Alex Williamson wrote:
> On Wed, 25 Oct 2017 08:45:11 -0500
> Bjorn Helgaas wrote:
>
> > [+cc Alex]
> >
> > On Mon, Oct 23, 2017 at 05:36:48PM -0400, Sinan Kaya wrote:
> > > The return codes from various reset t
On Thu, Oct 26, 2017 at 05:28:17PM +0300, Alexander Shishkin wrote:
> On some integrations of the Intel(R) Trace Hub (for a reference and
> overview see Documentation/trace/intel_th.txt) the reported size of
> one of its resources (RTIT_BAR) doesn't match its actual size, which
> leads to overlaps
t; Fixes: 0e4c2eeb758a ("alpha/PCI: Replace pci_fixup_irqs() call with host
> bridge IRQ mapping hooks")
> Link: http://lkml.kernel.org/r/alpine.lrh.2.21.1710251043170.7...@math.ut.ee
> Reported-by: Meelis Roos
> Signed-off-by: Lorenzo Pieralisi
> Cc: Bjorn Helgaas
> Cc: Ri
On Fri, Nov 10, 2017 at 10:40:35AM +, Lorenzo Pieralisi wrote:
> On Fri, Nov 10, 2017 at 08:46:29AM +0800, Shawn Lin wrote:
> > On 2017/11/9 23:05, Bjorn Helgaas wrote:
> > >diff --git a/MAINTAINERS b/MAINTAINERS
> > >index db412a627d96..6ce341e86fec 100644
> &
The first two patches fix typos that cause incorrect L1 substate
configuration. The last two are cosmetic for maintainability.
These are minor enough that I'd like to squeeze them into v4.15 unless
anybody objects.
---
Bjorn Helgaas (4):
PCI/ASPM: Account for downstream device&#
From: Bjorn Helgaas
Previously we programmed the LTR_L1.2_THRESHOLD in the parent (upstream)
device using the capability pointer of the *child* (downstream) device,
which corrupted some random word of the parent's config space.
Use the parent's L1 SS capability pointer to p
From: Bjorn Helgaas
Every Port that supports the L1.2 substate advertises its Port
Common_Mode_Restore_Time, i.e., the time the Port requires to re-establish
common mode when exiting L1.2 (see PCIe r3.1, sec 7.33.2).
Per sec 5.5.3.3.1, when exiting L1.2, the Downstream Port (the device at
the
From: Bjorn Helgaas
Reformat register field definitions in the style used elsewhere and align
comments with names used in the spec. No functional change intended.
Signed-off-by: Bjorn Helgaas
---
include/uapi/linux/pci_regs.h | 28 ++--
1 file changed, 14 insertions
From: Bjorn Helgaas
Add and use #defines for L1 Substate register fields instead of hard-coding
the masks. Also update comments to use names from the spec. No functional
change intended.
Signed-off-by: Bjorn Helgaas
---
drivers/pci/pcie/aspm.c | 34
jorn,
>
> Should i send a next version or just a fix patch on top of this?
Either way is fine. I'll just fold it in or replace the existing patch.
> > On Wed, Oct 11, 2017 at 9:32 PM, Bjorn Helgaas wrote:
> >> On Wed, Sep 20, 2017 at 10:54:15AM +0530, Keerthy wrote:
On Thu, Oct 05, 2017 at 04:16:50PM -0500, Bjorn Helgaas wrote:
> On Mon, Sep 25, 2017 at 06:56:58PM -0500, Bjorn Helgaas wrote:
> > On Mon, Aug 28, 2017 at 05:25:17PM +0200, Jan Luebbe wrote:
> > > The sum of the DRAM windows may exceed 4GB (at least on Armada XP).
> > &
On Sat, Oct 28, 2017 at 04:13:56PM +0530, Pankaj Dubey wrote:
> On 25 October 2017 at 17:32, Kishon Vijay Abraham I wrote:
> > Hi,
> >
> > On Wednesday 25 October 2017 01:32 AM, Bjorn Helgaas wrote:
> >> On Thu, Oct 12, 2017 at 09:27:57AM +0530, Pankaj Dubey
On Fri, Oct 20, 2017 at 01:19:17PM -0500, Bjorn Helgaas wrote:
> On Fri, Oct 13, 2017 at 09:10:38AM +0530, Pankaj Dubey wrote:
> >
> >
> > On 10/12/2017 04:09 PM, David Laight wrote:
> > >From: Pankaj Dubey
> > >>Sent: 12 October 2017 08:55
> > &
On Tue, Oct 24, 2017 at 07:10:55PM +0530, Pankaj Dubey wrote:
> On 20 October 2017 at 23:11, Bjorn Helgaas wrote:
> >
> > On Thu, Oct 12, 2017 at 10:11:08AM +0530, Pankaj Dubey wrote:
> > > IATU unroll feature can be enabled in EP mode as well, so we need to
>
On Tue, Oct 24, 2017 at 01:04:26PM -0700, Jeff Kirsher wrote:
> From: Liang-Min Wang
>
> When a SR-IOV supported device is bound with vfio-pci, the driver
> could not create SR-IOV instance through /sys/bus/pci/devices/...
> /sriov_numvfs. This patch re-activates this capability for a PCIe
> dev
On Tue, Oct 17, 2017 at 06:03:14PM -0700, Brian Norris wrote:
> On Mon, Oct 16, 2017 at 03:03:50PM -0500, Bjorn Helgaas wrote:
> > On Sat, Oct 14, 2017 at 03:50:56AM +0800, Jeffy Chen wrote:
> > > Add support for PCIE_WAKE pin in rockchip pcie driver.
> > >
>
On Tue, Oct 17, 2017 at 04:39:05PM -0700, Brian Norris wrote:
> On Fri, Oct 13, 2017 at 11:51:52AM -0500, Bjorn Helgaas wrote:
> > On Thu, Oct 12, 2017 at 01:52:18PM -0700, Brian Norris wrote:
> > > The patch is self-descriptive. I've found that we may need
> > > pl
y of PCIe Root Ports does not advertise
an ACS capability. However, the RTL internally implements similar
protection as if ACS had Request Redirection, Completion Redirection,
Source Validation, and Upstream Forwarding features enabled.
Change Cavium ACS capabilities quirk flags acco
On Thu, Oct 19, 2017 at 04:59:21AM -0700, Vadim Lomovtsev wrote:
> On Thu, Oct 19, 2017 at 06:26:45AM -0500, Bjorn Helgaas wrote:
> > On Tue, Oct 17, 2017 at 05:47:37AM -0700, Vadim Lomovtsev wrote:
> > > From: Vadim Lomovtsev
> > >
> > > version 7:
> >
PCI fixes:
- move alpha PCI IRQ map/swizzle functions out of initdata to fix
regression from PCI core IRQ mapping changes (Lorenzo Pieralisi)
The following changes since commit 407dae1e4415acde2d9f48bb76361893c4653756:
PCI: aardvark: Move to struct pci_host_bridge IRQ mapping functions
On Mon, Oct 05, 2015 at 08:03:45AM +0200, Ruud wrote:
> Hello all,
>
> Looking at the changes in this sundays rc, it seems the PCI patches of
> Yinghai do not get picked up in RC2 and later. I did see some patches
> from helgaas.
>
> git://git.kernel.org/pub/scm/linux/kernel/git/yinghai/linux-yin
Hi William and Linus,
On Mon, Oct 5, 2015 at 3:29 AM, Linus Walleij wrote:
> On Thu, Oct 1, 2015 at 3:58 AM, William Breathitt Gray
> wrote:
>
>> The ACCES 104-IDIO-16 family of PC/104 utility boards
>
> Sounds like a PC104 keyboard :D
>
>> feature 16
>> optically isolated inputs and 16 opticall
si
> Tested-by: Tony Luck
> Signed-off-by: Jiang Liu
Acked-by: Bjorn Helgaas
Some minor structuring comments below, but my ack is valid even if you
don't address them.
> ---
> drivers/acpi/pci_root.c | 204
> ++
> include
On Mon, Sep 14, 2015 at 04:07:34PM +0800, Jiang Liu wrote:
> Reset acpi_root_dev->domain to 0 when pci_ignore_seg is set to keep
> consistence between ACPI PCI root device and PCI host bridge device.
>
> Signed-off-by: Jiang Liu
Acked-by: Bjorn Helgaas
> ---
> arch/
On Mon, Sep 14, 2015 at 04:07:35PM +0800, Jiang Liu wrote:
> Use common interface to simplify ACPI PCI host bridge implementation.
>
> Signed-off-by: Jiang Liu
> Reviewed-by: Hanjun Guo
Is there a corresponding ia64 patch? If we're really consolidating
this code (which I completely support), w
.)
>
> We've essentially cloned the former to make the latter, and taken
> out the remove/module_exit parts since those never get used in a
> non-modular build of the code.
>
> Cc: Bjorn Helgaas
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Paul Gortmaker
Applie
Hi Sasha,
On Sun, Oct 04, 2015 at 05:49:29PM -0400, Sasha Levin wrote:
> Commit 63692df1 ("PCI: Allow numa_node override via sysfs") didn't check that
> the numa node provided by userspace is valid. Passing a node number too high
> would attempt to access invalid memory and trigger a kernel panic.
Hi Keith,
I have a few comments scattered below.
On Thu, Oct 01, 2015 at 11:44:14AM -0600, Keith Busch wrote:
> The Intel Volume Management Device (VMD) is an integrated endpoint on the
> platform's PCIe root complex that acts as a host bridge to a secondary
> PCIe domain. BIOS can reassign one o
On Wed, Oct 07, 2015 at 04:52:55PM +0800, Hanjun Guo wrote:
> On 10/07/2015 02:01 AM, Bjorn Helgaas wrote:
> >On Mon, Sep 14, 2015 at 04:07:35PM +0800, Jiang Liu wrote:
> >>Use common interface to simplify ACPI PCI host bridge implementation.
> >>
> >>Signe
On Wed, Oct 07, 2015 at 10:07:33AM -0400, Sasha Levin wrote:
> > On 10/06/2015 03:36 PM, Bjorn Helgaas wrote:
> >> Hi Sasha,
> >>
> >> On Sun, Oct 04, 2015 at 05:49:29PM -0400, Sasha Levin wrote:
> >>> Commit 63692df1 ("PCI: Allow numa_node overr
Hi Prarit,
On Tue, Oct 06, 2015 at 04:02:22PM -0400, Prarit Bhargava wrote:
> On 10/06/2015 03:36 PM, Bjorn Helgaas wrote:
> > On Sun, Oct 04, 2015 at 05:49:29PM -0400, Sasha Levin wrote:
> >> Commit 63692df1 ("PCI: Allow numa_node override via sysfs") didn't ch
Hi Ben,
On Fri, Sep 11, 2015 at 04:55:00PM -0500, Ben Shelton wrote:
> For some SR-IOV devices, the number of available virtual functions
> increases after enabling ARI. Currently, SRIOV_NUM_VF is read and saved
> off before the ARI control bit is enabled. This causes an issue when VFs
> are ena
Hi David,
On Fri, Oct 02, 2015 at 11:43:59AM -0700, David Daney wrote:
> From: David Daney
>
> pci_bus_fixup_irqs() works like pci_fixup_irqs(), except it only does
> the fixups for devices on the specified bus.
>
> Follow-on patch will use the new function.
>
> Signed-off-by: David Daney
> -
[+cc Matthew]
On Wed, Oct 07, 2015 at 01:08:40PM -0700, David Daney wrote:
> On 10/07/2015 12:44 PM, Bjorn Helgaas wrote:
> >Hi David,
> >
> >On Fri, Oct 02, 2015 at 11:43:59AM -0700, David Daney wrote:
> >>From: David Daney
> >>
> >>pci_bus_fix
On Wed, Oct 07, 2015 at 03:21:36PM -0500, Ben Shelton wrote:
> Hi Bjorn,
>
> On Wed, Oct 07, 2015 at 02:29:40PM -0500, Bjorn Helgaas wrote:
> > Hi Ben,
> >
> > On Fri, Sep 11, 2015 at 04:55:00PM -0500, Ben Shelton wrote:
> > > For some SR-IOV devices, the n
;private_data;
^
Make these drivers depend on ARM unconditionally.
[bhelgaas: changelog]
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Bjorn Helgaas
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index c132bdd..3745c63 100644
---
ndow:
Enumeration
Allocate ATS struct during enumeration (Bjorn Helgaas)
Embed ATS info directly into struct pci_dev (Bjorn Helgaas)
Reduce size of ATS structure elements (Bjorn Helgaas)
Stop caching ATS Invalidate Queue Depth (Bjorn Helgaas)
iommu/vt-d: Cache PCI ATS state and In
[+cc Arnd, Rob]
Hi Zhou,
I have a few minor comments and two questions: one about the fact
all the config accesses are 32 bits, and another about the use of the
"msi-parent" node.
On Sat, Oct 10, 2015 at 10:59:15AM +0800, Zhou Wang wrote:
> This patch adds PCIe host support for HiSilicon SoC Hip
Hi Jiang,
I object to subject lines like "Correctly do such and such." Nobody
writes code to do things *incorrectly*, so the word "correctly" takes
up space without contributing meaning. In this case, it's at least
debatable whether this is even the "correct" approach; see below.
On Tue, Sep 08
On Wed, Sep 9, 2015 at 1:38 AM, Jiang Liu wrote:
> On 2015/7/30 4:37, Bjorn Helgaas wrote:
>> On Tue, Jun 09, 2015 at 12:20:43AM +0800, Jiang Liu wrote:
>>> Enhance ACPI resource parsing interfaces to support sparse IO space,
>>> which will be used to share common code
Hi Thierry,
On Wed, Sep 9, 2015 at 10:11 AM, Thierry Reding
wrote:
> Hi,
>
> There's currently an issue with PCI configuration space accesses on
> Tegra. The PCI host controller driver's ->map_bus() implementation
> remaps I/O memory on-demand to avoid potentially wasting 256 MiB of
> virtual add
On Tue, Sep 8, 2015 at 11:49 AM, Jiang Liu wrote:
> Hi Bjorn,
> We have used another draft version to fix this issue by changing
> eata driver as below. But that needs to export pcibios_alloc_irq. And
> I'm not sure whether there are other drivers having the same behavior.
> If we think it
Hi Wenlin,
On Thu, Oct 15, 2015 at 06:46:44PM +0800, Wenlin Kang wrote:
> This patch restricts 64-bit pci device to assign resource from behind of
> max_pfn when kernel config enables CONFIG_64BIT.
>
> On some system that pci device requires assignment of large resource(eg,
> 1GB or larger), some
On Wed, Oct 14, 2015 at 09:26:09AM -0700, David Daney wrote:
> On 10/14/2015 09:17 AM, Sean O. Stalley wrote:
> >Signed-off-by: Sean O. Stalley
> >
>
> Thanks a lot Sean.
>
> I think you cannot SOB if the patches are not flowing through you
> (as may be the case for my two additions). Perhaps a
On Tue, Oct 13, 2015 at 11:00:31PM +0200, Arnd Bergmann wrote:
> On Tuesday 13 October 2015 13:11:34 Ray Jui wrote:
> > >> diff --git a/drivers/pci/host/pcie-iproc.c
> > >> b/drivers/pci/host/pcie-iproc.c
> > >> index f3481ddff344..abcb4be2ee19 100644
> > >> --- a/drivers/pci/host/pcie-iproc.c
> >
offset/stride, computing max_bus, then setting NUM_VF to zero
again.
Bjorn
commit 8e20e89658f23b8d16b1e21810e9f63c8625129c
Author: Bjorn Helgaas
Date: Thu Oct 15 11:31:21 2015 -0500
PCI: Set SR-IOV NumVFs to zero after enumeration
The enumeration path should leave NumVFs set to ze
Hi Ben,
On Thu, Oct 08, 2015 at 10:20:17AM -0500, Ben Shelton wrote:
> For some SR-IOV devices, the number of available virtual functions increases
> after enabling ARI. Currently, SRIOV_NUM_VF is read and saved off before the
> ARI control bit is enabled in SRIOV_CTRL. This causes an issue when
.6,
which says TotalVFs is HwInit, but we don't need TotalVFs before setting
the ARI Capable bit anyway.
Set the ARI Capable Hierarchy bit (if ARI is enabled in the upstream
bridge) before reading TotalVFs.
[bhelgaas: changelog]
Signed-off-by: Ben Shelton
>
> Initially supports mapping the RID via OF device tree. In the future,
> this could be extended to use ACPI _IORT tables as well.
>
> Reviewed-by: Marc Zyngier
> Signed-off-by: David Daney
Acked-by: Bjorn Helgaas
I assume Thomas will take these (or at least, somebody
On Tue, Oct 06, 2015 at 06:03:58PM +0100, Marc Zyngier wrote:
> Now that we have a function that implements the complexity of the
> "msi-parent" property parsing, switch to that.
>
> Signed-off-by: Marc Zyngier
Acked-by: Bjorn Helgaas
> ---
> drivers/pci/of.c
that assumption, add pci_dev_msi_domain
> which is the equivalent of pci_host_bridge_msi_domain, but for
> a single device.
>
> Other than moving things around a bit, this patch on its own
> has no effect.
>
> Signed-off-by: Marc Zyngier
Acked-by: Bjorn He
nctionnality as a first
> implementation.
>
> Signed-off-by: Marc Zyngier
Acked-by: Bjorn Helgaas
I assume somebody other than me will merge this series.
> ---
> drivers/pci/msi.c | 17 +
> drivers/pci/probe.c | 8
> include/linux/msi.h | 6 ++
>
On Wed, Oct 14, 2015 at 02:29:41PM +0800, Jiang Liu wrote:
> Use common interface to simplify ACPI PCI host bridge implementation.
>
> Signed-off-by: Jiang Liu
> Reviewed-by: Hanjun Guo
> Signed-off-by: Liu Jiang
Acked-by: Bjorn Helgaas
> ---
> arch/
elp ARM64 in future.
>
> Reviewed-by: Lorenzo Pieralisi
> Tested-by: Tony Luck
> Signed-off-by: Jiang Liu
> Signed-off-by: Liu Jiang
Acked-by: Bjorn Helgaas
> ---
> drivers/acpi/pci_root.c | 204
> ++
> include/linux/pci-
On Wed, Oct 14, 2015 at 02:29:35PM +0800, Jiang Liu wrote:
> From: Liu Jiang
>
> This patch set consolidates common code to support ACPI PCI root on x86
> and IA64 platforms into ACPI core, to reproduce duplicated code and
> simplify maintenance. And a patch set based on previous version to suppo
8eb6c.
90e4032eeaf2 added the "if (size % ob->window_size)".
Is this more subtle than that?
> ---
> On Thursday 15 October 2015 09:19:27 Ray Jui wrote:
> > On 10/15/2015 9:00 AM, Bjorn Helgaas wrote:
> > >
> > > Ping; I can easily fix up the static, but it&#
On Thu, Oct 15, 2015 at 01:00:55PM -0700, Alexander Duyck wrote:
> On 10/15/2015 10:58 AM, Bjorn Helgaas wrote:
> >Hi Ben,
> >
> >On Thu, Oct 08, 2015 at 10:20:17AM -0500, Ben Shelton wrote:
> >>For some SR-IOV devices, the number of available virtual functions in
On Fri, Oct 16, 2015 at 11:47:42AM +0200, Arnd Bergmann wrote:
> On Thursday 15 October 2015 16:01:13 Bjorn Helgaas wrote:
> > On Thu, Oct 15, 2015 at 09:40:45PM +0200, Arnd Bergmann wrote:
> > > The iproc PCI driver tries to figure out whether the MMIO window has
> > >
1201 - 1300 of 6735 matches
Mail list logo
