On Mon, Apr 04, 2005 at 03:46:20PM -0700, Nathan Lynch wrote:
>
>Hi Nigel!
>
>On Tue, Apr 05, 2005 at 08:14:25AM +1000, Nigel Cunningham wrote:
>>
>> On Tue, 2005-04-05 at 01:33, Nathan Lynch wrote:
>> > > Yes, exactly. Someone who understand do_exit please help clean
>
>
s,
>card->hw.alloc_ramsize);
>
>-
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>
next update.
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Ashok Raj
- Open Source Technology Center
This provides a working default config file for Intel systems.
Tested on harwich (4p + ht systems), if more are required either add
to this config, or create new defconfig's as required.
Signed-off-by: Ashok Raj &l
Folks,
Iam getting this on the recent 2.6.12-rc5-mm1 kernel built with defconfig.
Cheers,
Ashok Raj
--- [cut here ] - [please bite here ] -
Kernel BUG at "include/linux/list.h":165
invalid operand: [1] SMP
CPU 2
Modules linked in:
Pid: 1, comm: swapper N
On Mon, Aug 08, 2005 at 07:11:26PM +0200, Andi Kleen wrote:
> On Mon, Aug 08, 2005 at 09:48:19AM -0700, Ashok Raj wrote:
> > Folks,
> >
> > Iam getting this on the recent 2.6.12-rc5-mm1 kernel built with defconfig.
> >
> > Cheers,
> > Ashok Raj
> >
rio was the driver tried to probe, found nothing, and tries
to de-reg resulting in the BUG().
I will try to get the recompile and entire dmesg log in the meantime.
>
> James
>
>
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Ashok Raj
- Open Source Technology Center
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ic7xxx_osm.c
> @@ -2331,8 +2331,6 @@ ahc_platform_dump_card_state(struct ahc_
> {
> }
>
> -static void ahc_linux_exit(void);
> -
> static void ahc_linux_set_width(struct scsi_target *starget, int width)
> {
> struct Scsi_Host *shost = dev_to_shost(starget->dev.pare
ts in send IPI to a cpu that is offline which can trip when the
cpu is in the process of being kicked alive.
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
---
arch/x86_64/kernel/genapic_flat.c |8
1 files changed, 8 insertion
No need to enforce_max_cpus when hotplug code is enabled. This
nukes out cpu_present_map and cpu_possible_map making it impossible to add
new cpus in the system.
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
arch/x86_64/kernel/smpboot.c
Auto selection of bigsmp patch removed this check from a shared common file
in arch/i386/kernel/acpi/boot.c. We still need to call this to determine
the right genapic code for x86_64.
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
---
support (for no-broadcast) is required.
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
arch/x86_64/kernel/genapic.c | 52 +
arch/x86_64/kernel/genapic_cluster.c
lat mode.
Andi: Do you think this is acceptable?
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
---
arch/x86_64/kernel/genapic.c |9 +
1 files changed, 1 insertion(+), 8 deletions(-)
Index: linux-2.6.13-rc4-mm1/ar
On Mon, Aug 01, 2005 at 01:20:18PM -0700, Ashok Raj wrote:
> Auto selection of bigsmp patch removed this check from a shared common file
> in arch/i386/kernel/acpi/boot.c. We still need to call this to determine
> the right genapic code for x86_64.
>
Thanks venki,
missed the che
Delivery mode should be APIC_DM_FIXED when using physical mode.
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
arch/x86_64/kernel/genapic_flat.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: linux-2.6.13-rc4-mm
On Thu, Aug 04, 2005 at 12:41:10PM +0200, Andi Kleen wrote:
> On Mon, Aug 01, 2005 at 01:20:20PM -0700, Ashok Raj wrote:
> > No need to enforce_max_cpus when hotplug code is enabled. This
> > nukes out cpu_present_map and cpu_possible_map making it impossible to add
> > n
On Thu, Aug 04, 2005 at 12:43:02PM +0200, Andi Kleen wrote:
> On Mon, Aug 01, 2005 at 01:20:21PM -0700, Ashok Raj wrote:
> > Need to ensure we dont get prempted when we clear ourself from mask when
> > using
> > clustered mode genapic code.
>
> It's not needed
s still needs the num_online_cpus()s check.
Opps missed that... Thanks for spotting it.
I will send an updated one to Andrew.
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Ashok Raj
- Open Source Technology Center
-
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the body of a message to [EMAIL PROT
ill needs the num_online_cpus()s check.
>
> -Andi
Modified patch attached.
Andrew: the filename in your -mm queue is below, with the attached
patch.
x86_64dont-do-broadcast-ipis-when-hotplug-is-enabled-in-flat-mode.patch
--
Cheers,
Ashok Raj
- Open Source Technology Center
Note: Rece
h_online_cpu(j)
> seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
> #endif
> seq_printf(p, " %14s", irq_desc[i].handler->typename);
> @@ -276,12 +276,12 @@ skip:
> spin_unlock_irqrestore(&irq_desc[i].lock, flags);
> } e
On Thu, Sep 01, 2005 at 10:45:10AM +0200, Andi Kleen wrote:
> Hallo Natalie,
>
> On Wednesday 31 August 2005 14:13, [EMAIL PROTECTED] wrote:
> > Current IA32 CPU hotplug code doesn't allow bringing up processors that
> > were not present in the boot configuration. To make existing hot plug
> > fac
find that the CPU
is now present and functional as reported by _STA, then the CPU is onlinable.
So if _STA can work favorably in your case you can use it to override the
disabled setting at boot time which would be prefectly fine.
>
--
Cheers,
Ashok Raj
- Open Source Technology Center
-
To un
Hi Andi
On Mon, Sep 05, 2005 at 06:48:21AM +0200, Andi Kleen wrote:
> On Sat, Sep 03, 2005 at 02:33:26PM -0700, [EMAIL PROTECTED] wrote:
> >
> > From: Ashok Raj <[EMAIL PROTECTED]>
> >
> > No need to enforce_max_cpus when hotplug code is enabled. This
On Tue, Sep 06, 2005 at 01:18:08AM +0200, Andi Kleen wrote:
> On Sat, Sep 03, 2005 at 02:33:30PM -0700, [EMAIL PROTECTED] wrote:
> >
> > From: Ashok Raj <[EMAIL PROTECTED]>
> >
> > It is not required to choose the physflat mode when CPU hotplug is enabled
&
On Tue, Sep 06, 2005 at 01:16:28AM +0200, Andi Kleen wrote:
> On Sat, Sep 03, 2005 at 02:33:30PM -0700, [EMAIL PROTECTED] wrote:
> >
> > From: Ashok Raj <[EMAIL PROTECTED]>
> >
> > Newly introduced physflat_* shares way too much with cluster with only a
we dont end up reworking some trivial patches for a long time.
If you feel that way, i deeply apologize, and repeat, thats not my intend.
>
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- Open Source Technology Center
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the body of
h hotplug) would make
IPI performance worse, since it would do one cpu at a time, and requires 2
writes per cpu for each IPI v.s just 2 for a flat mode mask version of the API.
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- Open Source Technology Center
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On Fri, Sep 09, 2005 at 01:41:58PM -0700, Christopher Beppler wrote:
>
>[1.] One line summary of the problem:
>If I deactivate a CPU with /sys/devices/system/cpux and try to
>reactivate it, then the CPU doesn't start and the kernel prints out an
>oops.
>
Could you try this on 2.6
r the cross post to lia64 ]
--
Cheers,
Ashok Raj
- Open Source Technology Center
---
fix_ia64_smp_affinity - Make GENERIC_HARDIRQ work for IPF and CPU Hotplug
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
Made GENERIC_HARDIRQ mechanism work for IPF and CPU hotplug. When write to
/proc/irq
On Mon, Mar 14, 2005 at 03:59:23PM -0800, Andrew Morton wrote:
> Ashok Raj <[EMAIL PROTECTED]> wrote:
> >
>
> "ia64" is preferred, please. Nobody knows what an IPF is.
Right!. Sorry about that.
>
>
> Is it not possible for ia64's ->set_affini
Hi Michael
have you thought about how this infrastructure would play well with
existing CPU hotplug code for ia64?
Once you return to user mode via the iret, is it possible that user mode
thread could get switched due to a pending cpu quiese attempt to remove
a cpu? (Current cpu removal code wou
On Mon, Jun 11, 2007 at 02:14:49PM -0700, Andrew Morton wrote:
> >
> > Again, if dma_map_{single|sg} API's fails due to
> > failure to allocate memory, the only thing that can
> > be done is to panic as this is what few of the other
> > IOMMU implementation is doing today.
>
> If the only opti
On Tue, Jun 12, 2007 at 12:25:57AM +0200, Andi Kleen wrote:
>
> > Please advice.
>
> I think the short term only safe option would be to fully preallocate an
> aperture.
> If it is too small you can try GFP_ATOMIC but it would be just
> a unreliable fallback. For safety you could perhaps have so
es to Documentation area for startup options and some basics.
7. Workaround to provide unity map for ISA bridge device to enable floppy disk.
8. Ability to preserve some mappings for devices not able to address entire
range.
Please help review and provide feedback.
Cheers,
Ashok Raj & Shaohu
devices under a p2p share the same
domain in a DMAR.
We just cache the type of device, if its a native PCIe device
or not for later use.
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
Signed-off-by: Shaohua Li <[EMAIL PROTECTED]>
-
Index:
provides a workaround for some drivers that request
a write-only mapping when they really should request a read-write.
(We ran into one such case in eepro100.c in handling rx_ring_dma)
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
Signed-off-by: Shaohua Li <[EMAIL
ole memory for gfx devices, that is physical address equals to
virtual address.In this way, gfx will use physical address for DMA, this
is primarily for add-in card GFX device.
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
Signed-off-by: Shaohua Li <[EMAIL PROTECTED]>
Index: linux-
Document Intel IOMMU driver boot option.
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
Signed-off-by: Shaohua Li <[EMAIL PROTECTED]>
Index: linux-2.6.21-rc5/Documentation/Intel-IOMMU.txt
===
--- /dev/null 1970
-off-by: Ashok Raj <[EMAIL PROTECTED]>
Signed-off-by: Shaohua Li <[EMAIL PROTECTED]>
Index: linux-2.6.21-rc5/Documentation/kernel-parameters.txt
===
--- linux-2.6.21-rc5.orig/Documentation/kernel-parameters.txt 2007-
This patch contains basic ACPI parsing and enumeration support.
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
Signed-off-by: Shaohua Li <[EMAIL PROTECTED]>
Index: linux-2.6.21-rc5/arch/x86_64/Kconfig
===
--- linux-2.6.21-r
Floppy disk drivers dont work well with DMA remapping. Its possible to
extend the current use for x86_64, but the gain is very little. If someone
feels compelled to clean this up, its up for grabs. Since these use 16M, we
just provide a unity map for the ISA bridge device.
Signed-off-by: Ashok
On Mon, Apr 09, 2007 at 11:39:19PM -0400, Len Brown wrote:
> On Monday 09 April 2007 17:55, Ashok Raj wrote:
> > This patch contains basic ACPI parsing and enumeration support.
>
> AFAICS, ACPI supplies the envelope which delivers the table,
> and ACPI has some convenience str
On Tue, Apr 10, 2007 at 09:49:55AM +0200, Andi Kleen wrote:
> On Monday 09 April 2007 23:55:52 Ashok Raj wrote:
>
> > Please help review and provide feedback.
>
> High level question: how did you solve the "user X server needs IOMMU bypass"
> problem?
There is no
On Tue, Apr 10, 2007 at 04:34:48AM -0400, Jeff Garzik wrote:
> Shaohua Li wrote:
> >DMA remapping just uses ACPI table to tell which dma remapping engine a
> >pci device is controlled by at boot time. At run time, DMA remapping
> >hasn't any interactive with ACPI.
>
> The Linux kernel _really_ wan
devices under a p2p share the same
domain in a DMAR.
We just cache the type of device, if its a native PCIe device
or not for later use.
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
Signed-off-by: Shaohua Li <[EMAIL PROTECTED]>
-
Index
provides a workaround for some drivers that request
a write-only mapping when they really should request a read-write.
(We ran into one such case in eepro100.c in handling rx_ring_dma)
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
Signed-off-by: Shaohua Li <[EMAIL
devices under a p2p share the same
domain in a DMAR.
We just cache the type of device, if its a native PCIe device
or not for later use.
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
Signed-off-by: Shaohua Li <[EMAIL PROTECTED]>
-
Index
Floppy disk drivers dont work well with DMA remapping. Its possible to
extend the current use for x86_64, but the gain is very little. If someone
feels compelled to clean this up, its up for grabs. Since these use 16M, we
just provide a unity map for the ISA bridge device.
Signed-off-by: Ashok
Document Intel IOMMU driver boot option.
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
Signed-off-by: Shaohua Li <[EMAIL PROTECTED]>
Index: linux-2.6.21-rc5/Documentation/Intel-IOMMU.txt
===
--- /dev/null 1970
ole memory for gfx devices, that is physical address equals to
virtual address.In this way, gfx will use physical address for DMA, this
is primarily for add-in card GFX device.
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
Signed-off-by: Shaohua Li <[EMAIL PROTECTED]>
Index: 2.6.21-
-off-by: Ashok Raj <[EMAIL PROTECTED]>
Signed-off-by: Shaohua Li <[EMAIL PROTECTED]>
Index: linux-2.6.21-rc5/Documentation/kernel-parameters.txt
===
--- linux-2.6.21-rc5.orig/Documentation/kernel-parameters.txt 2007-
Floppy disk drivers dont work well with DMA remapping. Its possible to
extend the current use for x86_64, but the gain is very little. If someone
feels compelled to clean this up, its up for grabs. Since these use 16M, we
just provide a unity map for the ISA bridge device.
Signed-off-by: Ashok
This patch contains basic ACPI parsing and enumeration support.
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
Signed-off-by: Shaohua Li <[EMAIL PROTECTED]>
Index: linux-2.6.21-rc5/arch/x86_64/Kconfig
===
--- linux-2.6.21-r
d.
Cheers,
Ashok Raj
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Please read the FAQ at http://www.tux.org/lkml/
hand, this will provide more compatibility, but we will lose
oppertunity to identify broken device drivers that dont use dma api's
and fix them Depending on who you talk to.. some like it.. some just
hate it! and would like to fix the broken ones instead.
Cheers,
Ashok Raj
--
-
To unsubs
provides a workaround for some drivers that request
a write-only mapping when they really should request a read-write.
(We ran into one such case in eepro100.c in handling rx_ring_dma)
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
Signed-off-by: Shaohua Li <[EMAIL
This patch contains basic ACPI parsing and enumeration support.
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
Signed-off-by: Shaohua Li <[EMAIL PROTECTED]>
Index: linux-2.6.21-rc5/arch/x86_64/Kconfig
===
--- linux-2.6.21-r
Document Intel IOMMU driver boot option.
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
Signed-off-by: Shaohua Li <[EMAIL PROTECTED]>
Index: linux-2.6.21-rc5/Documentation/Intel-IOMMU.txt
===
--- /dev/null 1970
ole memory for gfx devices, that is physical address equals to
virtual address.In this way, gfx will use physical address for DMA, this
is primarily for add-in card GFX device.
Signed-off-by: Ashok Raj <[EMAIL PROTECTED]>
Signed-off-by: Shaohua Li <[EMAIL PROTECTED]>
Index: 2.6.21-
-off-by: Ashok Raj <[EMAIL PROTECTED]>
Signed-off-by: Shaohua Li <[EMAIL PROTECTED]>
Index: linux-2.6.21-rc5/Documentation/kernel-parameters.txt
===
--- linux-2.6.21-rc5.orig/Documentation/kernel-parameters.txt 2007-
On Tue, Apr 24, 2007 at 08:50:48PM +0200, Andi Kleen wrote:
>
> > +
> > +LIST_HEAD(dmar_drhd_units);
> > +LIST_HEAD(dmar_rmrr_units);
>
> Comment describing what lock protects those lists?
> In fact there seems to be no locking. What about hotplug?
>
There is no support to handle an IOMMU hotpl
On Tue, Apr 24, 2007 at 09:33:15PM +0200, Andi Kleen wrote:
> On Tuesday 24 April 2007 08:03:07 Ashok Raj wrote:
> > Some devices may not support entire 64bit DMA. In a situation where such
> > devices are co-located in a shared domain, we need to ensure there is some
> > a
On Tue, Apr 24, 2007 at 09:31:09PM +0200, Andi Kleen wrote:
> On Tuesday 24 April 2007 08:03:06 Ashok Raj wrote:
> > Floppy disk drivers dont work well with DMA remapping.
>
> What is the problem? You can't allocate mappings <16MB?
No.. these drivers dont call DMA ma
On Tue, Apr 24, 2007 at 09:28:11PM +0200, Andi Kleen wrote:
> On Tuesday 24 April 2007 08:03:03 Ashok Raj wrote:
> > PCI specs permit zero length reads (ZLR) even if the mapping for that
> > region
> > is write only. Support for this feature is indicated by the presence of a
On Tue, Apr 24, 2007 at 09:27:08PM +0200, Andi Kleen wrote:
> On Tuesday 24 April 2007 08:03:02 Ashok Raj wrote:
> >
> > +#ifdef CONFIG_DMAR
> > +#ifdef CONFIG_SMP
> > +static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
>
>
> Why does it nee
On Tue, Apr 24, 2007 at 11:17:55PM +0200, Markus Rechberger wrote:
> >+We also allocate gaurd pages with each mapping, so we can attempt to catch
> >+any overflow that might happen.
> >+
>
> guess you probably mean guard tables here...
>
So there is a good chance i can be "The Governor of Califo
On Tue, Apr 24, 2007 at 02:23:51PM -0700, David Miller wrote:
> From: Andi Kleen <[EMAIL PROTECTED]>
> Date: Tue, 24 Apr 2007 23:12:54 +0200
>
> > We already have a couple of other IOMMU architectures who essentially have
> > the same
> > problem. Have you checked how they solve this?
>
> Sparc6
On Wed, Apr 25, 2007 at 12:03:57AM +0200, Andi Kleen wrote:
> On Tuesday 24 April 2007 23:50:26 David Miller wrote:
> > From: Ashok Raj <[EMAIL PROTECTED]>
> > Date: Tue, 24 Apr 2007 14:38:35 -0700
> >
> > > Its not clear if we have a very generic device br
From: Jean-Philippe Brucker
Device drivers need to check if an IOMMU enabled ATS, PRI and PASID in
order to know when they can use the SVM API. Cache PRI and PASID bits in
the pci_dev structure, similarly to what is currently done for ATS.
Signed-off-by: Jean-Philippe Brucker
---
drivers/pci/a
Resending Jean's patch so it can be included earlier than his large
SVM commits. Original patch https://patchwork.kernel.org/patch/9593891
was ack'ed by Bjorn. Let's commit these separately since we need
functionality earlier.
Resending this series as requested by Jean.
CQ Tang (1):
PCI: Save p
Cc: David Woodhouse
Cc: io...@lists.linux-foundation.org
Signed-off-by: CQ Tang
Signed-off-by: Ashok Raj
---
drivers/pci/ats.c | 65 +
drivers/pci/pci.c | 3 +++
include/linux/pci-ats.h | 10
include/linux/pci.h | 6
ny unknown regressions.
Signed-off-by: Ashok Raj
Reviewed-by: Tony Luck
Tested-by: Serge Ayoun
---
arch/x86/kernel/cpu/mcheck/mce.c | 38 --
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/m
le anymore.
- Consolidated some code to use sharing
- Minor changes to some prototypes to fit usage.
- Left handling same for non-Intel CPU models to avoid any unknown regressions.
- Fixed review comments from Boris
Signed-off-by: Ashok Raj
Reviewed-by: Tony Luck
Tested-by: Serge Ayoun
---
arch/x86/
much longer for the rebase to be complete in tip/x86/pti.
Ashok Raj (4):
x86/ibrs: Introduce native_rdmsrl, and native_wrmsrl
x86/ibrs: Add new helper macros to save/restore MSR_IA32_SPEC_CTRL
x86/ibrs: Add direct access support for MSR_IA32_SPEC_CTRL
x86/feature: Detect the x86 feature Ind
y the CPU.
[Ashok: Modified to reuse V3 spec-ctrl patches from Tim]
Signed-off-by: Paolo Bonzini
Signed-off-by: Ashok Raj
---
arch/x86/kvm/svm.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 0e68f0b..7c1
- Remove including microcode.h, and use native macros from asm/msr.h
- added license header for spec_ctrl.c
Signed-off-by: Ashok Raj
---
arch/x86/include/asm/spec_ctrl.h | 17 -
arch/x86/kernel/cpu/spec_ctrl.c | 1 +
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git
Note this MSR is only writable and does not carry any state. Its a barrier
so the code should perform a wrmsr when the barrier is needed.
Signed-off-by: Ashok Raj
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/include/asm/msr-index.h | 3 +++
arch/x86/kernel/cpu/spec_ctrl.c| 7 +++
Add direct access to MSR_IA32_SPEC_CTRL from a guest. Also save/restore
IBRS values during exits and guest resume path.
Rebasing based on Tim's patch
Signed-off-by: Ashok Raj
---
arch/x86/kvm/cpuid.c | 3 ++-
arch/x86/kvm/vmx.c | 41 +
arch/x8
- same as spec_ctrl_unprotected_begin
spec_ctrl_restriction_on - same as spec_ctrl_unprotected_end
Signed-off-by: Ashok Raj
---
arch/x86/include/asm/spec_ctrl.h | 12
arch/x86/kernel/cpu/spec_ctrl.c | 11 +++
2 files changed, 23 insertions(+)
diff --git a/arch/x86/include
Hi Paolo
Do you assume that host isn't using IBRS and only guest uses it?
On Mon, Jan 8, 2018 at 10:08 AM, Paolo Bonzini wrote:
> Direct access to MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD is important
> for performance. Allow load/store of MSR_IA32_SPEC_CTRL, restore guest
> IBRS on VM entry
commit 30ec26da9967d0d785abc24073129a34c3211777 upstream
Avoid loading microcode if any of the CPUs are offline, and issue a
warning. Having different microcode revisions on the system at any time
is outright dangerous.
[ Borislav: Massage changelog. ]
Signed-off-by: Ashok Raj
Signed-off-by
Gleixner
Tested-by: Tom Lendacky
Tested-by: Ashok Raj
Cc: Arjan Van De Ven
Cc: Tom Lendacky
Cc: Asit K Mallick
Cc: sta...@vger.kernel.org
Link: https://lkml.kernel.org/r/20180228102846.13447-6...@alien8.de
---
arch/x86/kernel/cpu/microcode/intel.c | 11 +--
1 file changed, 5 insertions
Tested-by: Tom Lendacky
Tested-by: Ashok Raj
Reviewed-by: Tom Lendacky
Cc: Arjan Van De Ven
Cc: Asit K Mallick
Cc: sta...@vger.kernel.org
Link: https://lkml.kernel.org/r/20180228102846.13447-7...@alien8.de
---
arch/x86/kernel/cpu/microcode/core.c | 11 +--
1 file changed, 5 insertions
From: Borislav Petkov
commit 854857f5944c59a881ff607b37ed9ed41d031a3b upstream
It is a useless remnant from earlier times. Use the ucode_state enum
directly.
No functional change.
Signed-off-by: Borislav Petkov
Signed-off-by: Thomas Gleixner
Tested-by: Tom Lendacky
Tested-by: Ashok Raj
Cc
CPU before performing a microcode
update and thus save us the WRMSR 0x79 because it is a particularly
expensive operation.
[ Borislav: Massage changelog and coding style. ]
Signed-off-by: Ashok Raj
Signed-off-by: Borislav Petkov
Signed-off-by: Thomas Gleixner
Tested-by: Tom Lendacky
Tested-by
.
[ Borislav: Massage it and use native_wbinvd() in both cases. ]
Signed-off-by: Ashok Raj
Signed-off-by: Borislav Petkov
Signed-off-by: Thomas Gleixner
Tested-by: Tom Lendacky
Tested-by: Ashok Raj
Cc: Arjan Van De Ven
Cc: Tom Lendacky
Cc: Asit K Mallick
Cc: sta...@vger.kernel.org
Link:
http
Petkov
Signed-off-by: Ashok Raj
Signed-off-by: Borislav Petkov
Signed-off-by: Thomas Gleixner
Tested-by: Tom Lendacky
Tested-by: Ashok Raj
Reviewed-by: Tom Lendacky
Cc: Arjan Van De Ven
Cc: Asit K Mallick
Cc: sta...@vger.kernel.org
Link: https://lkml.kernel.org/r/20180228102846.13447-8...@alien8
rking on a 4.9 backport, will send those once i get them to
work. stop_machine differences seem big enough that i might choose a
different approach for the 4.9 backport.
Cheers,
Ashok
Ashok Raj (4):
x86/microcode/intel: Check microcode revision before updating sibling
threads
x86/micro
on, do not do the exit sync if microcode wasn't
updated.
Reported-by: Emanuel Czirai
Signed-off-by: Borislav Petkov
Signed-off-by: Thomas Gleixner
Tested-by: Emanuel Czirai
Tested-by: Ashok Raj
Tested-by: Tom Lendacky
Cc: Asit K Mallick
Cc: sta...@vger.kernel.org
Link: https://lk
-by: Thomas Gleixner
Tested-by: Emanuel Czirai
Tested-by: Ashok Raj
Tested-by: Tom Lendacky
Cc: Tom Lendacky
Cc: Asit K Mallick
Cc: sta...@vger.kernel.org
Link: https://lkml.kernel.org/r/20180314183615.17629-1...@alien8.de
---
arch/x86/include/asm/microcode.h | 1 +
arch/x86/kernel/cpu
visible features.
Originally-by: Ashok Raj
Tested-by: Ashok Raj
Signed-off-by: Borislav Petkov
Reviewed-by: Ashok Raj
Cc: Andy Lutomirski
Cc: Arjan van de Ven
Cc: Borislav Petkov
Cc: Dan Williams
Cc: Dave Hansen
Cc: David Woodhouse
Cc: Greg Kroah-Hartman
Cc: Josh Poimboeuf
Cc: Linus
From: Borislav Petkov
commit 3f1f576a195aa266813cbd4ca70291deb61e0129 upstream
... so that callers can know when microcode was updated and act
accordingly.
Tested-by: Ashok Raj
Signed-off-by: Borislav Petkov
Reviewed-by: Ashok Raj
Cc: Andy Lutomirski
Cc: Arjan van de Ven
Cc: Borislav
From: Borislav Petkov
commit 1008c52c09dcb23d93f8e0ea83a6246265d2cce0 upstream
Add a callback function which the microcode loader calls when microcode
has been updated to a newer revision. Do the callback only when no error
was encountered during loading.
Tested-by: Ashok Raj
Signed-off-by
Add required definitions to support Local Machine Check Exceptions.
See http://www.intel.com/sdm Volume 3, System Programming Guide, chapter 15
for more information on MSR's and documentation on Local MCE.
Signed-off-by: Ashok Raj
---
arch/x86/include/asm/mce.h| 5 +
arc
to
perform rendezvous with other logical processors unlike earlier processors
that would broadcast machine check errors.
See http://www.intel.com/sdm Volume 3, Chapter 15 for more information
on MSR's and documentation on Local MCE.
Signed-off-by: Ashok Raj
---
arch/x86/kernel/cpu/mcheck/
s and documentation on Local MCE.
Signed-off-by: Ashok Raj
---
Documentation/x86/x86_64/boot-options.txt | 3 ++
arch/x86/include/asm/mce.h| 5 +++
arch/x86/kernel/cpu/mcheck/mce.c | 3 ++
arch/x86/kernel/cpu/mcheck/mce_intel.c| 59 +++
4 files ch
the fault.
For more details see Vol3, Chapter 15, Machine Check Architecture.
Modified to incorporate feedback from Boris on V1 patches.
Ashok Raj (3):
x86, mce: Add LMCE definitions.
x86, mce: Add infrastructure required to support LMCE
x86, mce: Handling LMCE events
Documentation/x86/x
Add required definitions to support Local Machine Check Exceptions.
See http://www.intel.com/sdm Volume 3, System Programming Guide, chapter 15
for more information on MSR's and documentation on Local MCE.
Signed-off-by: Ashok Raj
---
arch/x86/include/asm/mce.h| 5 +
arc
, Machine Check Architecture.
Ashok Raj (3):
x86, mce: Add LMCE definitions.
x86, mce: Add infrastructure required to support LMCE
x86, mce: Handling LMCE events
Documentation/x86/x86_64/boot-options.txt | 3 ++
arch/x86/include/asm/mce.h| 10
arch/x86/include/uapi/asm/msr
to
perform rendezvous with other logical processors unlike earlier processors
that would broadcast machine check errors.
See http://www.intel.com/sdm Volume 3, Chapter 15 for more information
on MSR's and documentation on Local MCE.
Signed-off-by: Ashok Raj
---
arch/x86/kernel/cpu/mcheck/
s and documentation on Local MCE.
Signed-off-by: Ashok Raj
---
Documentation/x86/x86_64/boot-options.txt | 3 ++
arch/x86/include/asm/mce.h| 5 +++
arch/x86/kernel/cpu/mcheck/mce.c | 3 ++
arch/x86/kernel/cpu/mcheck/mce_intel.c| 75 +++
4
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