On 04/16/2013 01:18 PM, Borislav Petkov wrote:
On Tue, Apr 16, 2013 at 12:15:47PM -0500, Aravind wrote:
This one case in point, please redo it against tip/master.
I had based off bp.git's master... and it misses an additional
'PCI_DEVICE' line (Hence the conflict)
On 04/17/2013 04:20 PM, Borislav Petkov wrote:
[ trim CC-list ]
On Wed, Apr 17, 2013 at 02:57:13PM -0500, Aravind Gopalakrishnan wrote:
Add code to handle ECC decoding for fam16h. Support exists for
previous families already, so code has been reused werever applicable
and some code has been
On 04/15/2013 11:11 AM, Borislav Petkov wrote:
On Mon, Apr 15, 2013 at 09:56:08AM -0600, Bjorn Helgaas wrote:
On Mon, Apr 15, 2013 at 9:17 AM, Aravind Gopalakrishnan
@@ -172,7 +176,12 @@
*/
#define PCI_DEVICE_ID_AMD_15H_NB_F10x1601
#define PCI_DEVICE_ID_AMD_15H_NB_F20x1602
On 04/15/2013 11:45 AM, Aravind wrote:
On 04/15/2013 11:11 AM, Borislav Petkov wrote:
On Mon, Apr 15, 2013 at 09:56:08AM -0600, Bjorn Helgaas wrote:
On Mon, Apr 15, 2013 at 9:17 AM, Aravind Gopalakrishnan
@@ -172,7 +176,12 @@
*/
#define PCI_DEVICE_ID_AMD_15H_NB_F10x1601
#define
On 04/16/2013 09:24 AM, Borislav Petkov wrote:
On Mon, Apr 15, 2013 at 01:56:00PM -0500, Aravind Gopalakrishnan wrote:
Add code to handle ECC decoding for fam16h. Support exists for
previous families already, so code has been reused werever applicable
and some code has been added to handle
The condition check 'channel < 0' is needless since channel is unsigned.
Reported by Dave Jones here:
http://marc.info/?l=linux-kernel&m=137839225430844&w=2
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/amd64_edac.c |2 +-
1 file changed, 1 insertion(+), 1 de
.
update: corrections to code from previous versions involve few cosmetic
changes, reusing f10_read_dct_pci_cfg and basing off tip/master
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/kernel/amd_nb.c |4 +-
drivers/edac/amd64_edac.c | 100
There are some newer error signatures in Family 15h models 30h-3fh.
Code has been added in the patch to support these new signatures.
Patch has been tested on Fam15h using mce_amd_inj facility and
has been verified to work correctly.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac
On 6/5/2013 4:32 PM, Borislav Petkov wrote:
On Wed, Jun 05, 2013 at 03:50:03PM -0500, Aravind Gopalakrishnan wrote:
There are some newer error signatures in Family 15h models 30h-3fh.
Code has been added in the patch to support these new signatures.
Patch has been tested on Fam15h using
een from
the bug report. In the patch, we rectify this by casting chan_addr to u64
and by comparing dct_base and dct_limit against (sys_addr >> 27)
Tested on F15h, M30h with ECC turned on and works fine.
Signed-off-by: Aravind Gopalakrishnan
diff --git a/drivers/edac/amd64_edac.c
Aravind Gopalakrishnan (1):
AMD64_EDAC: Fix incorrect wrap arounds due to left shift beyond 32
bits.
drivers/edac/amd64_edac.c |9 +
1 file changed, 5 insertions(+), 4 deletions(-)
--
1.7.10.4
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Aravind Gopalakrishnan (1):
EDAC, AMD64_EDAC: Add ECC decoding support for newer F15h models.
arch/x86/kernel/amd_nb.c | 14 ++-
drivers/edac/amd64_edac.c | 277 +
drivers/edac/amd64_edac.h | 108 +-
include/linux/pci_ids.h
ested on Fam15h M30h with ECC turned on using mce_amd_inj facility and
verified to be functionally correct.
Signed-off-by: Aravind Gopalakrishnan
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 3048ded..3ee7a4d 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/am
On 8/2/2013 11:25 AM, Borislav Petkov wrote:
On Fri, Aug 02, 2013 at 10:33:12AM -0500, Aravind Gopalakrishnan wrote:
Adding support for handling ECC error decoding for new F15 models.
On newer models, support has been included for upto 4 DCT's,
however, only DCT0 and DCT3 are curr
Adding code to check for specific model (F15h, M30h) and if yes,
do not add flag AMD_NB_GART. Also check cpuid_edx(0x8006) for
prescence of L3. If no L3, do not add any L3 flags.
Signed-off-by: Aravind Gopalakrishnan
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index
Changes from V1:
- Splitting up the patch
- Remove unnecessary helper functions
- Add family/model to amd64_pvt
- Cleanup indent issues
Aravind Gopalakrishnan (3):
EDAC, AMD64_EDAC: Add PCI Device ID Functions 3 and 4 for newer F15h
models.
EDAC, AMD64_EDAC
On 8/2/2013 12:02 PM, Aravind Gopalakrishnan wrote:
On 8/2/2013 11:25 AM, Borislav Petkov wrote:
On Fri, Aug 02, 2013 at 10:33:12AM -0500, Aravind Gopalakrishnan wrote:
Adding support for handling ECC error decoding for new F15 models.
On newer models, support has been included for upto 4
ested on Fam15h M30h with ECC turned on using mce_amd_inj facility and
verified to be functionally correct.
Signed-off-by: Aravind Gopalakrishnan
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 8b6a034..42dab12 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/ed
Adding PCI_DEVICE_ID_AMD_15H_NB_M30H_F3 and PCI_DEVICE_ID_AMD_15H_NB_M30H_F4
for F15h model 30h. This is required for the file amd_nb.c
Signed-off-by: Aravind Gopalakrishnan
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 3bed2e8..d1fe5d0 100644
--- a/include/linux
On 8/23/2013 4:37 PM, Borislav Petkov wrote:
On Mon, Aug 19, 2013 at 07:27:52PM -0500, Aravind Gopalakrishnan wrote:
Link to the bug report:
http://marc.info/?l=linux-edac&m=137692201732220&w=2
dct_base and dct_limit obtain 32 bit register values when they read their
respective pc
een from
the bug report. In the patch, we rectify this by casting chan_addr to
u64 and by comparing dct_base and dct_limit against (sys_addr >> 27)
Change from V1:
- Fix chan_offset to use left-shifted version of dct_base.
Signed-off-by: Aravind Gopalakrishnan
diff --git
On 8/6/2013 3:23 PM, Borislav Petkov wrote:
On Fri, Aug 02, 2013 at 05:43:04PM -0500, Aravind Gopalakrishnan wrote:
Adding support for handling ECC error decoding for new F15 models.
On newer models, support has been included for upto 4 DCT's,
however, only DCT0 and DCT3 are curr
On 8/6/2013 3:19 PM, Borislav Petkov wrote:
On Fri, Aug 02, 2013 at 05:43:03PM -0500, Aravind Gopalakrishnan wrote:
Adding code to check for specific model (F15h, M30h) and if yes,
do not add flag AMD_NB_GART. Also check cpuid_edx(0x8006) for
prescence of L3. If no L3, do not add any L3
On 8/6/2013 3:17 PM, Borislav Petkov wrote:
On Fri, Aug 02, 2013 at 05:43:02PM -0500, Aravind Gopalakrishnan wrote:
Adding PCI_DEVICE_ID_AMD_15H_NB_M30H_F3 and PCI_DEVICE_ID_AMD_15H_NB_M30H_F4
for F15h model 30h. This is required for the file amd_nb.c
... and amd64_edac.c
Also, remember to
On 8/6/2013 3:55 PM, Aravind Gopalakrishnan wrote:
On 8/6/2013 3:23 PM, Borislav Petkov wrote:
On Fri, Aug 02, 2013 at 05:43:04PM -0500, Aravind Gopalakrishnan wrote:
Adding support for handling ECC error decoding for new F15 models.
On newer models, support has been included for upto 4 DCT&#
s.
* Erratum 637: Not fixed.
Signed-off-by: Aravind Gopalakrishnan
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 8b6a034..2f05f62 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -123,7 +123,7 @@ static void f15h_select_dct(s
will send out changes in V3;
Thanks,
Aravind.
Corrected the indentations; Removed unnecessary comments;
Sending out changes in [PATCH 3/3 V3].
Thanks,
-Aravind.
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ddr, get_dram_limit(pvt, range));
…
The rest looks ok.
Ok,
I have removed the compiler warnings now and function-tested it as well.
(Works fine.)
Sending out changes in [PATCH 3/3 V4]
Thanks,
-Aravind.
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o not need the workaround.
Signed-off-by: Aravind Gopalakrishnan
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 8b6a034..bf07ae7 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -123,7 +123,7 @@ static void f15h_select_dct(struct amd64_pvt *pvt, u8
On Aug 10, 2013, at 10:15 AM, Borislav Petkov
wrote:
> On Fri, Aug 09, 2013 at 11:54:49AM -0500, Aravind Gopalakrishnan wrote:
>> Adding support for handling ECC error decoding for new F15 models.
>> On newer models, support has been included for upto 4 DCT's, however,
>&
.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/kernel/amd_nb.c |4 +-
drivers/edac/amd64_edac.c | 96 +++--
drivers/edac/amd64_edac.h | 12 +-
include/linux/pci_ids.h |2 +
4 files changed, 109 insertions(+), 5 deletions(-)
diff
.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/kernel/amd_nb.c |4 +-
drivers/edac/amd64_edac.c | 96 +++--
drivers/edac/amd64_edac.h |8 +++-
include/linux/pci_ids.h |2 +
4 files changed, 105 insertions(+), 5 deletions(-)
diff --git
.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/kernel/amd_nb.c |4 +-
drivers/edac/amd64_edac.c | 96 +++--
drivers/edac/amd64_edac.h |4 +-
include/linux/pci_ids.h |2 +
4 files changed, 101 insertions(+), 5 deletions(-)
diff --git a
, Aravind; Andre Przywara; r...@sisk.pl;
cpuf...@vger.kernel.org; linux...@vger.kernel.org; linux-kernel@vger.kernel.org
Cc: Andreas
Subject: Re: [PATCH] drivers/cpufreq: Warn user when powernow-k8 tries to fall
back to acpi-cpufreq and it is unavailable.
Adding bugreporter from BZ to CC.
On Fri
: Gopalakrishnan, Aravind; Andre Przywara; r...@sisk.pl;
cpuf...@vger.kernel.org; linux...@vger.kernel.org; linux-kernel@vger.kernel.org
Cc: Andreas
Subject: Re: [PATCH] drivers/cpufreq: Warn user when powernow-k8 tries to fall
back to acpi-cpufreq and it is unavailable.
Adding bugreporter from BZ to CC.
On
clarify that the CPU is unsupported and prints a warning message when there is
no acpi-cpufreq
present.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/cpufreq/powernow-k8.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/powernow-k8.c b/drivers
ional change is introduced.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/amd_nb.h | 2 +-
drivers/edac/amd64_edac.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index 1a5da2e..319843d 100644
On 10/14/2015 8:51 AM, Borislav Petkov wrote:
This is in preparation for future changes anyway so the name had to
be not so generic and hint at the PCI dev argument. I'll change it to
amd_pci_dev_to_node_id() when applying.
Thanks Boris.
-Aravind.
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Patch1: Add Scalable MCA feature identification
Patch2: Add CLZERO feature
Aravind Gopalakrishnan (2):
x86/mcheck: Add Scalable MCA cpuid bit
x86/cpufeature: Add CLZERO feature
arch/x86/include/asm/cpufeature.h | 5 -
arch/x86/include/asm/mce.h| 13 -
arch/x86
CLZERO instruction introduced in AMD Fam17h processors
zero's out a 64 byte cache line specified in RAX.
Add the bit here to allow /proc/cpuinfo to list the feature
Signed-off-by: Wan Zongshun
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/cpufeature.h | 5 -
arc
SMCA is enabled before
enabling the new features.
Adding code to detect if it SMCA is enabled in this patch
and store that info in mce_vendor_flags structure.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 13 -
arch/x86/kernel/cpu/mcheck/mce.c | 2 ++
2
On 10/25/2015 5:37 AM, Borislav Petkov wrote:
On Fri, Oct 23, 2015 at 06:18:33AM -0500, Aravind Gopalakrishnan wrote:
CLZERO instruction introduced in AMD Fam17h processors
zero's out a 64 byte cache line specified in RAX.
Add the bit here to allow /proc/cpuinfo to list the feature
Signe
(removing peter.p.waskiewicz...@intel.com as email bounced)
On 10/25/2015 5:37 AM, Borislav Petkov wrote:
On Fri, Oct 23, 2015 at 06:18:33AM -0500, Aravind Gopalakrishnan wrote:
CLZERO instruction introduced in AMD Fam17h processors
zero's out a 64 byte cache line specified in RAX.
Ad
On 10/26/2015 3:22 PM, Borislav Petkov wrote:
On Mon, Oct 26, 2015 at 10:12:59AM -0500, Aravind Gopalakrishnan wrote:
For large part yes, wrapped code in patch form with commit message etc.
And modified comment a little bit.
Does that still require his address in "From"?
Yes,
On 12/22/2014 5:19 PM, Borislav Petkov wrote:
On Mon, Dec 22, 2014 at 02:56:47PM -0600, Aravind Gopalakrishnan wrote:
On 12/22/2014 2:15 PM, Borislav Petkov wrote:
On Mon, Dec 22, 2014 at 02:10:09PM -0600, Aravind Gopalakrishnan wrote:
When a MCE happens that is to be logged onto bank 4 of
The caller of force_ibs_eilvt_setup() is ibs_eilvt_setup()
which does not care about the return values.
So, marking it void and cleaning up the return statements.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/kernel/cpu/perf_event_amd_ibs.c | 12 +---
1 file changed, 5 insertions
(IntP is set)
- interrupt_enable is set by default
- echo 0 > interrupt_enable clears IntType of respective register
- Forcing error count to go over threshold_limit generates APIC
interrupt and edac mce_amd catches it fine
Signed-off-by: Aravind Gopalakrishnan
---
perf actually collects info)
Or is this the way -D flag is intended to work?
Thanks for the clarifications,
-Aravind.
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On 12/23/2014 1:41 PM, Aravind Gopalakrishnan wrote:
On 12/22/2014 5:19 PM, Borislav Petkov wrote:
On Mon, Dec 22, 2014 at 02:56:47PM -0600, Aravind Gopalakrishnan wrote:
On 12/22/2014 2:15 PM, Borislav Petkov wrote:
On Mon, Dec 22, 2014 at 02:10:09PM -0600, Aravind Gopalakrishnan
wrote
On 1/7/2015 11:06 AM, Borislav Petkov wrote:
On Tue, Jan 06, 2015 at 05:54:15PM -0600, Aravind Gopalakrishnan wrote:
But we still need to change the error injection interfaces in mce_amd_inj:
mce_amd_inj triggers a #MC on the cpu number that the user specifies on
debugfs.
For any error other
Identifiers
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/kernel/cpu/amd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index a220239..9942b83 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
the patch.
Would you prefer the changes be in a separate patch or lump it in along
with current version?
Thanks,
-Aravind.
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On 3/19/2015 10:53 AM, Borislav Petkov wrote:
On Thu, Mar 19, 2015 at 09:41:01AM -0500, Aravind Gopalakrishnan wrote:
Ok, I'll work on this and prepend the changes to the current version
of the patch. Would you prefer the changes be in a separate patch or
lump it in along with current ve
int (*mce_severity) (struct mce *m, int tolerant, char **msg, bool
is_excp) =
mce_severity_default;
How much of grading should '_default' do if at all?
Thanks,
-Aravind.
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Patch1: Introduce AMD severities function
Patch2: Initialise mce_severity function pointer to choose between
Intel or AMD grading mechanisms
Aravind Gopalakrishnan (2):
x86, mce, severities: Add AMD severities function
x86, mce, severities: Define mce_severity function pointer
arch
flags field.
This is based off of work by Boris Petkov.
Testing details:
Tested the patch for any regressions on F15hM0h-0fh (Orochi)
and F15hM60h-6fh (Carrizo) and it works fine.
Signed-off-by: Aravind Gopalakrishnan
---
Changes from V1:
- Test mce_flags.overflow_recov once instead of multiple
x27;s cleaner to do it this way.
Suggested-by: Tony Luck
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h| 2 ++
arch/x86/kernel/cpu/mcheck/mce-internal.h | 3 ++-
arch/x86/kernel/cpu/mcheck/mce-severity.c | 35 ++-
arch/x86/kerne
check
and default_threshold_interrupt
are assigned to the respective function pointers when they are defined.
So, I just followed a similar assignment for mce_severity_default.
I can do that in the default statement if you prefer.
Thanks,
-Aravind.
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On 4/2/2015 5:01 AM, Ingo Molnar wrote:
* Aravind Gopalakrishnan wrote:
GART registers are not present in newer processors (Fam15h, Model 10h
and later). So, avoid accesses to GART registers in PCI config
space by returning early in early_gart_iommu_check() and
gart_iommu_hole_init() if GART
e() 64MB of RAM.
Also, we can avoid having to loop through all PCI buses, devices (twice)
searching for AGP bridge if we bail out early.
Makes sense. Mind adding this info to the changelog and resend?
Sure, will do that and resend.
Thanks,
-Aravind.
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On 4/2/2015 11:53 AM, Borislav Petkov wrote:
On Thu, Apr 02, 2015 at 11:23:17AM -0500, Aravind Gopalakrishnan wrote:
Sure, will do that and resend.
No need - I can amend the local copy I have here.
Okay.
Thanks!
-Aravind.
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correctly only if BIOS did
the right thing with setting up aperture space.
If !early_pci_allowed() and BIOS did not setup aperture correctly, that
would have caused problems already.
But it has not been an issue so far right?
Thanks,
-Aravind.
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ML is gone now. But there might be some plans to revive it,
who knows...
Maybe Aravind does?
Yeah, that ML is gone now.
The archives until 2012 was revived and made available here:
http://www.x86-64.org/pipermail/amd64-microcode/
Thanks,
-Aravind.
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is.
No functional changes are introduced by the patch
Reported-by: Dan Carpenter
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/kernel/cpu/mcheck/mce-severity.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce-severity.c
b/arch/x86
function
so we can use it here as well as in amd_nb.c
Tested the patch on Fam10h and Fam15h Model 00h-fh and this code
runs fine. On Fam15h Model 60h-6fh and on Fam16h, we bail early
as they don't have GART.
Signed-off-by: Aravind Gopalakrishnan
Reviewed-by: Suravee Suthikulpanit
---
arc
safely postulate that future
AMD processors will support 8-bit APIC IDs and we can simply set that
feature bit on them, without the PCI access.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/kernel/cpu/amd.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch
On 4/7/2015 7:34 AM, Borislav Petkov wrote:
On Mon, Apr 06, 2015 at 06:10:22PM -0500, Aravind Gopalakrishnan wrote:
So what happens if !early_pci_allowed() but the GART is present? We'll
set amd_northbridges.flags |= AMD_NB_GART, but won't run any of the
setup code in aperture_64.c,
On 4/7/2015 9:57 AM, Borislav Petkov wrote:
On Tue, Apr 07, 2015 at 09:46:26AM -0500, Aravind Gopalakrishnan wrote:
Okay. I'll do that and correct the typos Ingo pointed out earlier and
resend.
Btw, I think you should do the same in early_gart_iommu_check() too.
Doing the testing thi
Fam16h, we bail early
as they don't have GART.
Signed-off-by: Aravind Gopalakrishnan
Reviewed-by: Suravee Suthikulpanit
Cc: Joerg Rodel
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: H. Peter Anvin
Cc: Bjorn Helgaas
Cc: x86-ml
---
Changes in V2:
- move amd_gart_present() before any other check
that.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/iommu_table.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/iommu_table.h
b/arch/x86/include/asm/iommu_table.h
index f42a047..16845d4 100644
--- a/arch/x86/include/asm/iommu_table.h
++
introduced.
Aravind Gopalakrishnan (4):
x86/mce: Define 'SUCCOR' cpuid bit
x86/mce/amd: Introduce deferred error interrupt handler
x86, irq: Cleanup ordering of vector numbers
x86/mce/amd: Rename setup_APIC_mce
arch/x86/include/asm/entry_arch.h| 3 +
arch/x86/include/asm
'setup_APIC_mce' doesn't give us an indication of why we are
going to program LVT. Make that explicit by renaming it to
setup_APIC_mce_threshold so we know.
No functional change is introduced.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/kernel/cpu/mcheck/mce_amd.c |
Enforcing proper descending order of vector number assignments here.
No functional change.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/irq_vectors.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/x86/include/asm/irq_vectors.h
b/arch/x86
-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 3 ++-
arch/x86/kernel/cpu/mcheck/mce.c | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 1f5a86d..dfcb664 100644
--- a/arch/x86/include/asm/mce.h
- Provide Deferred error interrupt stats on
/proc/interrupts by incrementing irq_deferred_count
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/entry_arch.h| 3 +
arch/x86/include/asm/hardirq.h | 3 +
arch/x86/include/asm/hw_irq.h| 2 +
arch/x86/i
logged or reported only on NBC, we make sure that
we inject on the correct core here.
Aravind Gopalakrishnan (6):
edac, mce_amd_inj: Use MCE_INJECT_GET for bank
edac, mce_amd_inj: Rework sanity check for inj_bank_set
edac, mce_amd_inj: Modify flags attrigute to use string argument
The number of banks for a given processor is encoded in
MSR_IA32_MCG_CAP. So, use this to obtain the value and
for sanity checking in inj_bank_set() instead of requiring a
family/model check.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/mce_amd_inj.c | 14 +-
1 file
Provides information about each file and the usages.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/mce_amd_inj.c | 68 +-
1 file changed, 61 insertions(+), 7 deletions(-)
diff --git a/drivers/edac/mce_amd_inj.c b/drivers/edac/mce_amd_inj.c
ient and removes the
dependency. Also, we can introduce new flags as and when needed without
having to worry about conflicting with the flags already defined
in asm/mce.h
Also, modify do_inject() to use the newly defined injection_type enum
to figure out the injection mechanism we need to use
Si
would not have any effect on the system.
(i.e), we would not see any relevant output on kernel logs for
the error we just injected.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/mce_amd_inj.c | 76 ++
1 file changed, 76 insertions(+)
diff
With this extension to the flags attribute, deferred error interrupts
and threshold interrupts can be triggered to test the apic interrupt
handler functionality for these type of errors
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/mce_amd_inj.c | 35
inj_bank_get is generic enough that we can use the
macro in it's place. Doing that here.
No functional change.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/mce_amd_inj.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/edac/mce_amd_inj.c b/dr
rnel build will fail.
Tested the .config that broke the build against latest tip with
changes in for-next branch of bp.git and it builds fine now.
Reported-by: kbuild test robot
Cc: kbuild-...@01.org
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/mce_amd_inj.c | 1 +
1 file changed, 1
arate patch (Patch 5)
and README file in the following patch (Patch 6)
- Remove CONFIG_X86_HT ifdefs and factor out number of nodes calculation
- Provide accessor function in amd.c
Aravind Gopalakrishnan (9):
edac, mce_amd_inj: Use MCE_INJECT_GET for bank
edac, mce_amd_inj: Rew
: Aravind Gopalakrishnan
---
drivers/edac/mce_amd_inj.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/edac/mce_amd_inj.c b/drivers/edac/mce_amd_inj.c
index 377fd6c..ad18913 100644
--- a/drivers/edac/mce_amd_inj.c
+++ b/drivers/edac/mce_amd_inj.c
Provides information about each file and the usages.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/mce_amd_inj.c | 53 ++
1 file changed, 53 insertions(+)
diff --git a/drivers/edac/mce_amd_inj.c b/drivers/edac/mce_amd_inj.c
index ad18913
ixner
Cc: Ingo Molnar
Cc: "H. Peter Anvin"
Cc: Borislav Petkov
Cc: Jacob Shin
Cc: Dave Hansen
Cc: Andy Lutomirski
Cc: Paolo Bonzini
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/kernel/cpu/amd.c | 36 +++-
1 file changed, 27 insertions(+), 9 deleti
inj_bank_get is generic enough that we can use the
macro in it's place. Doing that here.
No functional change.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/mce_amd_inj.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/edac/mce_amd_inj.c b/dr
The number of banks for a given processor is encoded in
MSR_IA32_MCG_CAP. So, use this to obtain the value and
for sanity checking in inj_bank_set() instead of requiring a
family/model check.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/mce_amd_inj.c | 14 +-
1 file
With this extension to the flags attribute, deferred error interrupts
and threshold interrupts can be triggered to test the apic interrupt
handler functionality for these type of errors
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/mce_amd_inj.c | 41
ggested-by: Borislav Petkov
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/mce_amd_inj.c | 82 --
1 file changed, 72 insertions(+), 10 deletions(-)
diff --git a/drivers/edac/mce_amd_inj.c b/drivers/edac/mce_amd_inj.c
index 15f6aa1..c129a8d 10064
not have any effect on the system.
(i.e), we would not see any relevant output on kernel logs for
the error we just injected.
Signed-off-by: Aravind Gopalakrishnan
---
drivers/edac/mce_amd_inj.c | 55 ++
1 file changed, 55 insertions(+)
diff --git a
Cc: Andy Lutomirski
Cc: Paolo Bonzini
Cc: Denys Vlasenko
Cc: Hector Marco-Gisbert
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/processor.h | 1 +
arch/x86/kernel/cpu/amd.c| 6 ++
2 files changed, 7 insertions(+)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/i
On 6/3/2015 9:50 AM, Borislav Petkov wrote:
On Tue, Jun 02, 2015 at 03:35:56PM -0500, Aravind Gopalakrishnan wrote:
+
+ buf[cnt - 1] = 0;
+
+ /* strip whitespaces.. */
+ strstrip(buf);
Didn't your compiler trigger that:
drivers/edac/mce_amd_inj.c: In function ‘flags_
On 6/3/2015 3:58 AM, Borislav Petkov wrote:
On Tue, Jun 02, 2015 at 03:36:00PM -0500, Aravind Gopalakrishnan wrote:
+static void amd_set_num_nodes(void)
+{
+ if (cpu_has_topoext) {
+ u32 ecx;
+
+ ecx = cpuid_ecx(0x801e
On 6/3/2015 11:00 AM, Borislav Petkov wrote:
On Wed, Jun 03, 2015 at 10:34:50AM -0500, Aravind Gopalakrishnan wrote:
Oddly, No. The only thing I got was:
arch/x86/kernel/cpu/microcode/intel_early.c: In function
âget_matching_model_microcode.isra.2.constprop.7â:
arch/x86/kernel/cpu/microcode
On 5/29/2015 8:49 AM, Borislav Petkov wrote:
On Wed, May 27, 2015 at 02:03:35PM -0500, Aravind Gopalakrishnan wrote:
+#define MAX_FLAG_OPT_SIZE 10
Why 10?
No specific reason. Just an arbitrary max value that we won't hit right
now or in the future.
This should be 2 and increased
On 5/29/2015 10:36 AM, Borislav Petkov wrote:
On Wed, May 27, 2015 at 02:03:36PM -0500, Aravind Gopalakrishnan wrote:
+static void trigger_dfr_int(void *info)
+{
+ asm volatile("int $244");
+}
+
+static void trigger_thr_int(void *info)
+{
+ asm volatile("int $249&q
+ { .name = "cpu", .fops = &extcpu_fops, S_IRUSR | S_IWUSR },
+ { .name = "README", .fops = &readme_fops, S_IRUSR | S_IRGRP |
+ S_IROTH },
... and the first one adding perm to struct dfs_node
On 5/29/2015 11:00 AM, Borislav Petkov wrote:
On Wed, May 27, 2015 at 02:03:38PM -0500, Aravind Gopalakrishnan wrote:
+static u32 amd_get_num_nodes(void)
+{
+ u32 nodes = 1;
+
+ if (cpu_has_topoext) {
+ u32 ecx;
+
+ ecx = cpuid_ecx(0x801e
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