> Now I activated the debug messages in em28xx. From the messages I
> see no correlation of the pool exhaustion and lost sync. Also I
> cannot see any error messages from the em28xx driver.
> I see a lot of init_isoc/stop_urbs (maybe EPG scan?) without
> draining the coherent pool (checked with 'ca
> static struct platform_driver restart_poweroff_driver = {
> .probe = restart_poweroff_probe,
> - .remove = __devexit_p(restart_poweroff_remove),
> + .remove = restart_poweroff_remove,
> .driver = {
> .name = "poweroff-restart",
>
nitialization from incompatible pointer type [enabled by default]
> /home/arnd/linux-arm/arch/arm/mach-mv78xx0/addr-map.c:59:2: warning: (near
> initialization for 'addr_map_cfg.win_cfg_base') [enabled by default]
>
> Signed-off-by: Arnd Bergmann
> Cc: Jason Cooper
> Cc:
On Wed, Oct 24, 2012 at 03:49:21PM +0200, Gregory CLEMENT wrote:
> From: Lior Amsalem
>
> Signed-off-by: Gregory CLEMENT
> Signed-off-by: Lior Amsalem
> ---
> arch/arm/boot/dts/armada-370-db.dts |3 +++
> arch/arm/boot/dts/armada-370-xp.dtsi | 10 ++
> arch/arm/boot/dts/armada-x
On Fri, Oct 26, 2012 at 02:30:45PM +0200, Gregory CLEMENT wrote:
> Hello,
>
> this patch set adds the SATA support for Armada 370 and Armada XP. Few
> changes have been done since the first version by taking in account
> the comments received for the first version.
>
> The evaluation boards for A
On Fri, Oct 26, 2012 at 02:48:04PM +0200, Thomas Petazzoni wrote:
>
> On Fri, 26 Oct 2012 14:39:08 +0200, Andrew Lunn wrote:
>
> > What about the openblocks-ax3?
>
> Gr??gory does not (yet) have an OpenBlocks AX3, but I'm planning to do
> the work for SATA so
On Fri, Oct 26, 2012 at 09:31:54AM -0400, Jason Cooper wrote:
> On Fri, Oct 26, 2012 at 02:30:47PM +0200, Gregory CLEMENT wrote:
> > Signed-off-by: Gregory CLEMENT
> > Signed-off-by: Lior Amsalem
> > ---
> > arch/arm/boot/dts/armada-370-xp.dtsi |9 +
> > 1 file changed, 9 insertions(
> Now, about white spaces vs tab, I don't know what is the rule for .dts
> file.
I personally use tabs, but i don't see anything in the
Documentation/CodingStyle.
Maybe ask on the device tree mailing list?
Andrew
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+++ b/Documentation/devicetree/bindings/mmc/sdhci-dove.txt
@@ -0,0 +1,12 @@
+* Marvell sdhci-dove controller
+
+Required properties:
+- compatible: Should be "marvell,dove-sdhci".
+
+Example:
+
+sdio0: sdio@92000 {
+ compatible = "marvell,dove-sdhci";
+ reg = <0x92000 0x100>;
+ in
On Tue, Sep 25, 2012 at 03:22:04AM +0200, Sebastian Hesselbarth wrote:
> On 09/25/2012 02:02 AM, Sebastian Hesselbarth wrote:
> >During the review process of dove DT patches, Tauros2 cache
> >init call was changed and DT support added. This patch fixes
> >the call to Tauros2 init and adds a DT node
On Tue, Sep 25, 2012 at 02:02:17AM +0200, Sebastian Hesselbarth wrote:
> The watchdog on dove requires an interrupt that is not yet
> available on DT. Therefore, the watchdog DT node is removed
> until the corresponding chained intc is available.
Hi Sebastian
Just for my understanding: Is the pro
ertions(+), 21 deletions(-)
Its a bit late, Jason has already sent the pull request. But:
Acked-by: Andrew Lunn
None of my questions should be considered as NACKs for these patches.
Andrew
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the body of a m
On Tue, Sep 25, 2012 at 11:18:26AM +0200, Thomas Petazzoni wrote:
> Dear Sebastian Hesselbarth,
>
> On Tue, 25 Sep 2012 11:11:42 +0200, Sebastian Hesselbarth wrote:
>
> > I didn't try to post all the dove on mach-mvebu patches in the current
> > release cycle, because mach-mvebu is still evolving
On Tue, Sep 25, 2012 at 12:14:39PM +0200, Thomas Petazzoni wrote:
> Dear Andrew Lunn,
>
> On Tue, 25 Sep 2012 11:46:10 +0200, Andrew Lunn wrote:
>
> > I principle, i agree. However, i'm not too sure about mach-orion5x &
> > mach-mv78xx0. orion5x has probably be
> diff --git a/arch/arm/boot/dts/mbx001.dts b/arch/arm/boot/dts/mbx001.dts
> new file mode 100644
> index 000..88a5a11
> --- /dev/null
> +++ b/arch/arm/boot/dts/mbx001.dts
Hi Gregory
Maybe it would be good to prefix this with armada-370. It then fits
with armada-370-db.dts, and all the kirkwo
If the gpio_request_one() fails, or returns EPROBE_DEFER, the
regulator must be device_unregister()ed. When this is not done,
there are WARNING: from sysfs:
WARNING: at fs/sysfs/file.c:343 sysfs_open_file+0x238/0x268()
Signed-off-by: Andrew Lunn
---
drivers/regulator/core.c |3 ++-
1 file
g/cgit/linux/kernel/git/davem/net.git/commit/?id=569943d0639c85a451ea853087cbd5f738247dd9
>
> Cc: Jason Cooper
> Cc: Andrew Lunn
> Cc: Russell King
> Cc: Grant Likely
> Cc: Benjamin Herrenschmidt
> Cc: Jason Gunthorpe
> Cc: Ezequiel Garcia
> Cc: linux-arm-ker...@lists.infradead.org
> Cc:
> Sebastian, does __clk_enabled work properly for the mvebu clock
> provider? I don't see a clk_ops.is_enabled for mvebu.. (don't know
> much about clk)
Hi Jason
It is implemented in drivers/clk/clk-gate.c, which is what mvebu is
using.
Andrew
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To unsubscribe from this list: send the line "
; Signed-off-by: Sebastian Hesselbarth
Tested-by: Andrew Lunn
Andrew
> ---
> Cc: Mike Turquette
> Cc: Russell King
> Cc: Jason Cooper
> Cc: Andrew Lunn
> Cc: Grant Likely
> Cc: Benjamin Herrenschmidt
> Cc: Jason Gunthorpe
> Cc: Ezequiel Garcia
>
2->v3:
> - make use of new public clk_is_enabled (adds dependency [1])
> - add warning about gated clock && missing MAC property
> (Suggested by Jason Gunthorpe)
> v1->v2:
> - check for gated clock before accessing eth registers
> (Suggested by Andrew Lunn)
>
On Sat, Oct 05, 2013 at 10:24:30PM +0200, Uwe Kleine-König wrote:
> On Fri, Oct 04, 2013 at 12:08:30PM +0200, Sebastian Hesselbarth wrote:
> > To determine if a clk has been previously enabled, provide a public
> > clk_is_enabled function. This is especially helpful to check the state
> > of clk-ga
On Sun, Oct 06, 2013 at 11:06:09AM +0200, Gerhard Sittig wrote:
> On Sat, Oct 05, 2013 at 22:42 +0200, Andrew Lunn wrote:
> >
> > On Sat, Oct 05, 2013 at 10:24:30PM +0200, Uwe Kleine-König wrote:
> > > On Fri, Oct 04, 2013 at 12:08:30PM +0200, Sebastian Hesselbarth wrote:
> Andrew has mentioned, that some bootloaders might disable clocks but
> leave the nodes enabled. Reading those registers would lock up
> the HW, of course. So we thought about to check clk gate status first,
> which this patch is about.
>
> Of course, we can do clk_enable, read, clk_disable as sa
ch uses these generic routines for this driver.
>
> Cc: Andrew Lunn
> Signed-off-by: Viresh Kumar
> ---
> drivers/cpufreq/kirkwood-cpufreq.c | 22 +++---
> 1 file changed, 3 insertions(+), 19 deletions(-)
Hi Viresh
You can add:
Tested-by: Andrew Lunn
to
[PATCH
On Fri, Sep 13, 2013 at 06:32:21PM +0530, Viresh Kumar wrote:
> - if (freqs.old != freqs.new) {
> - local_irq_disable();
> -
> - /* Disable interrupts to the CPU */
> - reg = readl_relaxed(priv.base);
> - reg |= CPU_SW_INT_BLK;
> - wr
t; Cc: Olof Johansson
> Cc: Arnd Bergmann
> Cc: Jason Cooper
> Cc: Andrew Lunn
> Cc: Russell King
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
> arch/arm/mach-dove/board-dt.c | 11 ---
> 1 file changed, 11 deletions(-)
; Cc: Jason Cooper
> Cc: Andrew Lunn
> Cc: Russell King
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
> arch/arm/mach-kirkwood/board-dt.c |8
> 1 file changed, 8 deletions(-)
Hi Sebastian
Boot tested on a Kirkwood Topkick
On Sun, Sep 22, 2013 at 02:20:28PM +0200, Sebastian Hesselbarth wrote:
> On 09/21/2013 02:22 PM, Andrew Lunn wrote:
> >On Wed, Sep 18, 2013 at 07:53:44PM +0200, Sebastian Hesselbarth wrote:
> >>With arch/arm calling of_clk_init(NULL) from time_init(), we can now
> >>rem
kely
> Cc: Thomas Petazzoni
> Cc: Sebastian Hesselbarth
> Cc: Andrew Lunn
> Signed-off-by: Linus Walleij
> ---
> ChangeLog v1->v2:
> - Keep irq_create_mapping() and do not replace with
> irq_find_mapping() - if a linear domain is the outcome,
> we really need to all
On Fri, Dec 07, 2012 at 03:55:07PM -0700, Jason Gunthorpe wrote:
> The intent of this patch is to expose the other bridge cause
> interrupts to users in the kernel.
>
> - Add orion_bridge_irq_init to create a new edge triggered interrupt
> chip based on the bridge cause register
> - Remove all i
On Sat, Dec 08, 2012 at 07:57:48PM -0700, Jason Gunthorpe wrote:
> On Sat, Dec 08, 2012 at 12:26:24PM +0100, Andrew Lunn wrote:
>
> > 1) It should have an IRQ domain, like the other IRQ chips we have.
> > 2) It should have a DT binding, like the other IRQ chips we have.
>
On Mon, Nov 12, 2012 at 10:48:02AM +0100, Soeren Moch wrote:
> On 11.11.2012 18:22, Andrew Lunn wrote:
> > On Thu, Nov 08, 2012 at 07:38:57AM +0100, Marek Szyprowski wrote:
> >> dmapool always calls dma_alloc_coherent() with GFP_ATOMIC flag,
> regardless
> >> the flag
On Tue, Nov 06, 2012 at 10:28:45PM +0100, S?ren Moch wrote:
> resent as plain text, sorry.
>
>
> > For Armada 370/XP we have the same problem that for the commit
> > cb01b63, so we applied the same solution: "The default 256 KiB
> > coherent pool may be too small for some of the Kirkwood devices,
oni
> Signed-off-by: Marek Szyprowski
Tested-by: Andrew Lunn
I tested this on a Kirkwood QNAP after removing the call to
init_dma_coherent_pool_size().
Andrew
> ---
> mm/dmapool.c | 27 +++
> 1 file changed, 7 insertions(+), 20 deletions(-)
>
Hi Gregory
Nice work
On Fri, Nov 16, 2012 at 07:01:59PM +0100, Gregory CLEMENT wrote:
> Signed-off-by: Gregory CLEMENT
> ---
> .../bindings/clock/mvebu-gated-clock.txt | 43 ++
> arch/arm/mach-mvebu/Kconfig|1 +
> drivers/clk/mvebu/clk-gating-
> > What is the ddr clock for? Does bad things happen if you turn it off?
> > Kirkwood has a similar clock, dunit, which i decided not to export,
> > since when you turn it off, the whole SoC locks up.
>
> Well of course if you code run in DDR then it could be a problem. But
> I think it could be
r/0/0x40000500
>
> Working with Andrew Lunn we dug in further with full stack traces:
>
> [ 53.173973] IPv6: ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready
> [ 54.191655] BUG: scheduling while atomic: crond/144/0x4300
> [ 54.197537] Modules linked in: rmd160 sha1_gene
> >> diff -ruN a/drivers/staging/rtl8712/rtl871x_sta_mgt.c
> >> b/drivers/staging/rtl8712/rtl871x_sta_mgt.c
> >> --- a/drivers/staging/rtl8712/rtl871x_sta_mgt.c 2012-11-05
> >> 03:57:06.0 -0500
> >> +++ b/drivers/staging/rtl8712/rtl871x_sta_mgt.c 2012-11-13
> >> 12:54:28.0 -0500
> >
On Sun, Nov 18, 2012 at 02:18:37PM -0600, Larry Finger wrote:
> On 11/18/2012 12:11 PM, Andrew Lunn wrote:
> >
> >Just to clarify the issue here:
> >
> >union pn48 {
> > u64 val;
> >#if defined(__BIG_ENDIAN)
> > struct {
> >
On Mon, Nov 19, 2012 at 04:46:11PM +0100, Thomas Petazzoni wrote:
> Dear Andrew Lunn,
>
> On Sat, 17 Nov 2012 14:54:35 +0100, Andrew Lunn wrote:
> > > > What is the ddr clock for? Does bad things happen if you turn it off?
> > > > Kirkwood has a similar clock, dun
ll also work on Dove and it is
> messing
> with shared registers. It has done it before, so I consider it broken
> anyway.
> I (or somebody else) will take care of proper watchdog later.
> - An updated branch can be found on
> git://github.com/shesselba/linux-dove.git orion-ir
On Thu, Mar 21, 2013 at 05:26:15PM +0100, Gregory CLEMENT wrote:
> From: Lior Amsalem
>
> For mvebu IOs are 32 bits and we have 40 bits memory due to LPAE so
> make sure we give 32 bits addresses to the IOs.
Hi Gregory, Lior
I don't really understand what this comment is supposed to mean. I
wou
> /*
> - * 4 GB of plug-in RAM modules by default but only 3GB
> - * are visible, the amount of memory available can be
> - * changed by the bootloader according the size of the
> - * module actually plugged
> + * 8 GB o
On Thu, Mar 21, 2013 at 09:22:36PM +0100, Thomas Petazzoni wrote:
> Dear Andrew Lunn,
>
> On Thu, 21 Mar 2013 21:15:33 +0100, Andrew Lunn wrote:
>
> > Could you recommend a document which introduces LPAE.
> >
> > Only being able to address 7GB seems a bit odd to
On Thu, Mar 21, 2013 at 05:12:01PM -0400, Alan Stern wrote:
> On Thu, 21 Mar 2013, Alan Stern wrote:
>
> > On Thu, 21 Mar 2013, Soeren Moch wrote:
> >
> > > Now I found out what is going on here:
> > >
> > > In itd_urb_transaction() we allocate 9 iTDs for each URB with
> > > number_of_packets =
reaking nand by configuring mpp0
> to gpio, while used also by nand (nand_io2 on mpp0).
>
> Signed-off-by: Sebastian Hesselbarth
> Tested-by: Soeren Moch
Acked-by: Andrew Lunn
> ---
> Cc: Soeren Moch
> Cc: Jason Cooper
> Cc: Andrew Lunn
> Cc: Russell King
On Sat, Mar 23, 2013 at 01:58:22PM +0100, Sebastian Hesselbarth wrote:
> This patch just adds the missing MACH_GURUPLUG_DT to kirkwood_defconfig.
>
> Signed-off-by: Sebastian Hesselbarth
> Reported-by: Soeren Moch
Acked-by: Andrew Lunn
> ---
> Cc: Soeren Moch
> C
On Sat, Mar 23, 2013 at 04:06:51PM +0100, Sebastian Hesselbarth wrote:
> The CPU used in Marvell Dove SoCs is a PJ4 Sheeva core. Using
> CONFIG_CPU_PJ4 instead of CONFIG_CPU_V7 will also allow to enable
> iWMMXt extensions on Dove.
>
> Signed-off-by: Sebastian Hesselbarth
Acked-
On Wed, Jul 17, 2013 at 10:09:10AM +0800, Wei Yongjun wrote:
> From: Wei Yongjun
>
> Convert to use devm_* APIs to avoid resources leak on error handling case.
>
> Signed-off-by: Wei Yongjun
> ---
> drivers/mtd/nand/orion_nand.c | 29 +
> 1 file changed, 9 insertion
T parsing and uses cpu->of_node instead.
>
> Cc: Andrew Lunn
> Cc: Jason Cooper
> Acked-by: Viresh Kumar
> Signed-off-by: Sudeep KarkadaNagesha
> ---
> drivers/cpufreq/kirkwood-cpufreq.c | 14 --
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
&
On Mon, Jul 29, 2013 at 02:29:06PM +0200, Sebastian Hesselbarth wrote:
> This adds an initial DT file for the Globalscale D2Plug with Dove SoC.
> Currently, one LED is missing and I have not been able to get SD8787 driver
> working. Those will be taken care of later.
Hi Sebastion
I took a hard lo
On Mon, Jul 29, 2013 at 12:21:22PM -0300, Ezequiel Garcia wrote:
> If CONFIG_HAVE_CLK is not selected, then all the clk API turn out
> into stubs, so there's no need to have the ifdefs.
> The only side-effect of this patch is the extra tiny kmalloc,
> but that's not enough reason to have such ugly
On Tue, Jul 30, 2013 at 10:03:56AM +0200, Sebastian Hesselbarth wrote:
> On 07/29/2013 08:45 PM, Andrew Lunn wrote:
> >On Mon, Jul 29, 2013 at 02:29:06PM +0200, Sebastian Hesselbarth wrote:
> >>This adds an initial DT file for the Globalscale D2Plug with Dove SoC.
> >>Cu
On Thu, Aug 08, 2013 at 07:18:19PM +0530, Viresh Kumar wrote:
> Lets use cpufreq_table_validate_and_show() instead of calling
> cpufreq_frequency_table_cpuinfo() and cpufreq_frequency_table_get_attr().
>
> Cc: Andrew Lunn
> Signed-off-by: Viresh Kumar
> ---
> drivers/cpufr
rsing and uses cpu->of_node instead.
>
> Cc: Andrew Lunn
> Cc: Jason Cooper
> Acked-by: Viresh Kumar
> Signed-off-by: Sudeep KarkadaNagesha
> ---
> drivers/cpufreq/kirkwood-cpufreq.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --gi
On Thu, May 02, 2013 at 09:48:50PM +0200, Sebastian Hesselbarth wrote:
> On 05/02/2013 09:35 PM, Jason Gunthorpe wrote:
> >I have kirkwood HW but I haven't had time to make newer kernels run on
> >it, otherwise I'd test it too :(
>
> I also have kirkwood HW but that will cut me from email as I use
support for mv643xx_eth.
>
> Signed-off-by: Sebastian Hesselbarth
> ---
> Changelog:
> v1->v2:
> - split off DT changes (Suggested by Jason Cooper)
>
> Cc: Grant Likely
> Cc: Rob Herring
> Cc: Rob Landley
> Cc: Thomas Gleixner
> Cc: Russell King
> Cc: Arnd
per-board
> basis.
>
> Signed-off-by: Sebastian Hesselbarth
> ---
> Changelog:
> v3->v4:
> - convert to new device tree binding
>
> Cc: David Miller
> Cc: Lennert Buytenhek
> Cc: Jason Cooper
> Cc: Andrew Lunn
> Cc: Benjamin Herrenschmid
On Tue, May 21, 2013 at 06:41:38PM +0200, Sebastian Hesselbarth wrote:
> This patch set picks up work by Florian Fainelli bringing full DT
> support to mv643xx_eth and Marvell SoCs using it.
Hi Sebastian
I tested on my QNAP and topkick. Works great.
Tested-by: Andrew Lunn
Andrew
> > Why are you not keen on this? It seems like normal device driver
> > practice, that is what the data field of of_device_id is typically
> > used for..
>
> I'm not keen on it because we don't have a document saying "All kirkwood
> SoCs need PSC1 set to X after reset." We know it, but have we t
all explicit
> error messages can be removed from the failure code paths.
>
> Signed-off-by: Silviu-Mihai Popescu
> ---
Acked-by: Andrew Lunn
Thanks
Andrew
> drivers/cpufreq/kirkwood-cpufreq.c |8 +++-
> drivers/cpuidle/cpuidle-kirkwood.c |
tree and commit "rtc:
> rtc-mv: use devm_rtc_device_register()" from the akpm tree.
>
> I fixed it up (I think - see below) and can carry the fix as necessary
> (no action is required).
Hi Stephan
Looks O.K. to me.
Acked-by: Andrew Lunn
>
> --
> Cheers
On Mon, Aug 20, 2012 at 11:09:51AM +0200, Linus Walleij wrote:
> On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
> wrote:
>
> > This patch adds a pinctrl driver core for Marvell SoCs plus DT
> > binding documentation. This core driver will be used by SoC family
> > specific drivers, i.e. A
On Sat, Aug 25, 2012 at 03:01:33PM +0200, Mikael Pettersson wrote:
> My Kirkwood-based QNAP TS-119P+ boots fine with the 3.5 kernel. With
> 3.6-rc2 and 3.6-rc3 however sata_mv complains:
>
> sata_mv sata_mv.0: cannot get optional clkdev
> sata_mv sata_mv.0: slots 32 ports 2
>
> and then the kern
> +++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
> @@ -0,0 +1,279 @@
> +* Marvell Kirkwood SoC pinctrl driver for mpp
> +
> +Please refer to marvell,mvebu-pinctrl.txt in this directory for common
> binding
> +part and usage.
> +
> +Required properties:
> +- compatible
> I had a closer look at how kirkwood probes its id. I mentionend kirkwood_id()
> earlier but in fact it is kirkwood_pcie_id(). I assume pcie registers are shut
> down with pcie clk gated? That would require to have pcie running at least at
> boot-time on all boards.
>
> While it is still possible
s v3 patch set
Since Linus Walleij thinks that autoprobing is not going to happen,
Tested-by: Andrew Lunn
However, i still think it would be nice to have auto probing.
Andrew
> Cc: Sebastian Hesselbarth
> Cc: Thomas Petazzoni
> Cc: Grant Likely
> Cc: Rob Herring
> Cc: Ro
Hi Thomas
> Hum, which patches are stalling the integration into the Marvell tree?
l2 cache, I think.
The trees Jason built for pull requests in the direction of arm-soc
had the l2 cache patch as the very first in the series. Now that these
patches have run into some trouble, its blocking all th
On Thu, Sep 20, 2012 at 03:30:40PM +, Arnd Bergmann wrote:
> On Monday 17 September 2012, Linus Walleij wrote:
> > You found the weak spot between two consolidation tracks.
> >
> > Getting rid of a broadcast autodetect functions from say
> > is nominally done by passing the data
> > to the dr
> So, wouldn't we need a small, architecture-independent, infrastructure,
> through which architecture-specific code could "register" at boot
> time which SoC we are running on, and drivers could query this
> information from the common infrastructure?
>
> Of course, the major problem is to figure
Hi Sebastian
> -static void __init clk_init(void)
> +static void __init dove_clk_init(void)
> {
> tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
> -get_tclk());
> +dove_tclk);
>
> orion_clkdev_i
both enabled/disabled at the same time.
>
> Signed-off-by: Sebastian Hesselbarth
> ---
> Cc: Russell King
> Cc: Jason Cooper
> Cc: Andrew Lunn
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Cc: Rabeeh Khoury
> Cc: Ian Molton
>
arch/arm/mach-mv78xx0/addr-map.c:59:2: warning: (near initialization for
> 'addr_map_cfg.win_cfg_base') [enabled by default]
>
> Signed-off-by: Arnd Bergmann
> Cc: Andrew Lunn
> Cc: Michael Walle
> Cc: Nicolas Pitre
> ---
> arch/arm/mach-mv78xx0/addr-map.c |
On Thu, Jan 17, 2013 at 08:26:45PM +, Arnd Bergmann wrote:
> On Thursday 17 January 2013, Soeren Moch wrote:
> > On 17.01.2013 11:49, Arnd Bergmann wrote:
> > > On Wednesday 16 January 2013, Soeren Moch wrote:
> > I will see what I can do here. Is there an easy way to track the buffer
> >
> Please find attached a debug log generated with your patch.
>
> I used the sata disk and two em28xx dvb sticks, no other usb devices,
> no ethernet cable connected, tuners on saa716x-based card not used.
>
> What I can see in the log: a lot of coherent mappings from sata_mv
> and orion_ehci, a
On Wed, Jan 23, 2013 at 04:30:53PM +0100, Soeren Moch wrote:
> On 19.01.2013 19:59, Andrew Lunn wrote:
> >>Please find attached a debug log generated with your patch.
> >>
> >>I used the sata disk and two em28xx dvb sticks, no other usb devices,
> >>no ethe
> >>
> >
> >Now (in the last hour) stable, occasionally lower numbers:
> >3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396
> >3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396
> >3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396
> >3396 3
On Tue, Jan 15, 2013 at 01:13:12PM +0100, Stefan Peter wrote:
> In order to be able to use the ecc-mode, add the bch module to the default
> settings for the kirwood boards and enable the activation in orin-nand.c
>
> Signed-off-by: Stefan Peter
> ---
> diff --git a/arch/arm/configs/kirkwood_defc
On Thu, Dec 13, 2012 at 03:51:59PM -0500, Dave Jones wrote:
> On Thu, Dec 13, 2012 at 08:21:57PM +, Linux Kernel wrote:
> > Gitweb:
> http://git.kernel.org/linus/;a=commit;h=96ff0f5c7efd4a2205c48a76a6a1fcd2731e6128
> > Commit: 96ff0f5c7efd4a2205c48a76a6a1fcd2731e6128
> > Parent:
> > I think it needs to be on the menuconfig, rather than the child options.
> > I don't have OF_GPIO, but I still got asked for the former.
>
> The menuconfig enables a class of drivers (at least theoretically in the
> future, when more such drivers turn up), and there's no reason to
> believe th
> > Its a generic driver. I know its useful on various Marvell kirkwood
> > and orion5x devices. I've also heard it useful on some Tegra boards.
> >
> > Are you asking i list these boards?
>
> No, but at least mentioning the architecture might have clued me in
> quicker that this wasn't some
u &= ~(1 << pin); /* rising */
> writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
> + break;
> }
> }
> return 0;
Hi Axel
Good catch, thanks.
Acked-by: Andrew Lunn
Andrew
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On Wed, Jan 16, 2013 at 12:43:57PM +0100, Stefan Peter wrote:
> Hi Andrew
>
> on 15.01.2013 13:51, Andrew Lunn wrote:
> > On Tue, Jan 15, 2013 at 01:13:12PM +0100, Stefan Peter wrote:
> >> In order to be able to use the ecc-mode, add the bch module to the default
>
On Mon, Jul 18, 2016 at 08:45:40PM -0400, Vivien Didelot wrote:
> Implement the DSA driver function to configure the bridge ageing time.
>
> Signed-off-by: Vivien Didelot
Reviewed-by: Andrew Lunn
Andrew
top of a physical
> switch and ageing time are switch-wide, call the driver function with
> the fastest ageing time in use on the chip instead of the requested one.
>
> Signed-off-by: Vivien Didelot
Reviewed-by: Andrew Lunn
Andrew
gt; models. E.g. 88E6060, 88E6352 and 88E6390 use respectively 16, 15 and
> 3.75 seconds.
>
> Add a age_time_coeff to the info structure to handle this and a Global 1
> helper to set the default age time of 5 minutes in the setup code.
>
> Signed-off-by: Vivien Didelot
Reviewed-by: Andrew Lunn
Andrew
On Wed, Jul 20, 2016 at 06:26:41PM -0400, Vivien Didelot wrote:
> This patch simply moves the legacy DSA code from dsa.c to legacy.c,
> except the few shared symbols which remain in dsa.c.
I think it is a bit early for this. Lets convert all in kernel users
to the new binding first.
> Signed-off-
On Wed, Jul 20, 2016 at 06:18:34PM -0400, Vivien Didelot wrote:
> Only reg_lock is necessary now and phy_mutex is dead. Remove it.
>
> Signed-off-by: Vivien Didelot
Reviewed-by: Andrew Lunn
Andrew
| \
> MV88E6XXX_FLAG_G2_EEPROM_ADDR)
>
> Signed-off-by: Vivien Didelot
Reviewed-by: Andrew Lunn
Andrew
t
Reviewed-by: Andrew Lunn
Andrew
On Thu, Jul 21, 2016 at 02:43:56PM +0200, Grzegorz Jaszczyk wrote:
Hi Grzegorz
Some of these patches are missing a commit log entry. Please add at
least one line.
Andrew
On Thu, Jul 21, 2016 at 10:46:56AM -0400, Vivien Didelot wrote:
> Florian Fainelli writes:
>
> > Le 20/07/2016 à 17:35, Andrew Lunn a écrit :
> >> On Wed, Jul 20, 2016 at 06:26:41PM -0400, Vivien Didelot wrote:
> >>> This patch simply moves the legac
On Mon, Sep 19, 2016 at 03:28:00PM +0200, John Crispin wrote:
> commit 83c0afaec7b730b ("net: dsa: Add new binding implementation")
> has a duplicate invocation of the set_addr() operation callback. Remove one
> of them.
Upps. My error...
>
> Signed-off-by: John Cris
On Mon, Sep 19, 2016 at 03:27:59PM +0200, John Crispin wrote:
> The Marvell driver is the only one that actually sets the switches HW
> address. All other drivers have an empty stub. fix this by making the
> callback optional.
Hi John
Thanks for doing this,
Reviewed-by: Andrew Lunn
Andrew
Hi Vivien
> + do {
> + err = _mv88e6xxx_atu_getnext(chip, fid, &next);
> + if (err)
> + return err;
> +
> + if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
> + break;
> +
> + if (ether_addr_equal(next.mac,
On Mon, Sep 19, 2016 at 08:29:40PM -0400, Vivien Didelot wrote:
> Hi Andrew,
>
> Andrew Lunn writes:
>
> > Hi Vivien
> >
> >> + do {
> >> + err = _mv88e6xxx_atu_getnext(chip, fid, &next);
> >> + if (err)
> &
y for the old port?
> Signed-off-by: Vivien Didelot
Reviewed-by: Andrew Lunn
Andrew
On Tue, Sep 20, 2016 at 10:13:14PM +1000, Benjamin Herrenschmidt wrote:
> On Tue, 2016-09-20 at 16:00 +0930, Joel Stanley wrote:
> > On Aspeed SoC with a direct PHY connection (non-NSCI), we receive
> > continual PHYSTS interrupts:
> >
> > [ 20.28] ftgmac100 1e66.ethernet eth0: [ISR] =
On Mon, Sep 19, 2016 at 09:07:16PM -0400, Vivien Didelot wrote:
> Hi Andrew,
>
> Andrew Lunn writes:
>
> > On Mon, Sep 19, 2016 at 07:56:11PM -0400, Vivien Didelot wrote:
> >> An address can be loaded in the ATU with multiple ports, for instance
> >> when
rting the (indirect)
> Multi-chip Addressing Mode, and a low-level API to access the registers
> via SMI.
>
> Other accesses (like Ethernet management frames) may be added later.
>
> Signed-off-by: Vivien Didelot
Reviewed-by: Andrew Lunn
This series is now ready for merging.
Thanks
Andrew
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