On Mon, 14 Jan 2013 18:08:45 +0100
Stefan Bader wrote:
> On 14.01.2013 17:34, Borislav Petkov wrote:
> > On Mon, Jan 14, 2013 at 04:58:54PM +0100, Stefan Bader wrote:
> >> Starting with kernel v3.7 the following commit added a quirk
> >> to obtain the real frequencies of certain AMD systems:
> >>
Hi Maxime,
On 26/07/16 21:30, Maxime Ripard wrote:
> Hi,
>
> Here is the previous A64 patches made by Andre [1], reworked to use
> the new sunxi-ng clock framework.
>
> This uses the current H3 clock code, as both are really similar. The
> first patches are just meant to rework slightly the H3 c
On 09/09/16 21:10, Maxime Ripard wrote:
Hi Maxime,
> From: Andre Przywara
>
> The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores
> and the typical tablet / TV box peripherals.
> The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of
> the peripherals and the memor
Hi Maxime,
thanks for your answer, much appreciated!
On 23/08/16 20:31, Maxime Ripard wrote:
> Hi Andre,
>
> On Mon, Aug 01, 2016 at 02:43:06AM +0100, André Przywara wrote:
>> Hi Maxime,
>>
>> On 26/07/16 21:30, Maxime Ripard wrote:
>>> Hi,
>>>
>&
On 12/05/17 18:14, Tony Lindgren wrote:
> * Tony Lindgren [170512 08:39]:
>> * Linus Walleij [170512 02:28]:
>>> On Thu, May 11, 2017 at 4:20 PM, Andre Przywara
>>> wrote:
Linus, can you shed some light if this array creation serves some purpose?
>>>
>>> Tony [author of this function] can
On 12/03/18 16:10, Harald Geyer wrote:
> Add the proper pin group node to reference in board files.
>
> Signed-off-by: Harald Geyer
That looks correct to me, so:
Reviewed-by: Andre Przywara
But out of curiosity, what is this used for? In patch 5/5 I see it being
used, but without a clue for w
On 12/03/18 16:10, Harald Geyer wrote:
Hi,
> Add a watchdog node for the A64, automatically enabled on all boards.
> Tested on Olimex Teres I.
>
> Signed-off-by: Harald Geyer
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/a
On 05/11/2018 03:27 AM, Samuel Holland wrote:
> The Allwinner A64 SoC is known [1] to have an unstable architectural
> timer, which manifests itself most obviously in the time jumping forward
> a multiple of 95 years [2][3]. This coincides with 2^56 cycles at a
> timer frequency of 24 MHz, implying
On 01/15/2015 02:47 PM, Eric Auger wrote:
> CONFIG_HAVE_KVM_IRQCHIP is needed to support IRQ routing (along
> with irq_comm.c and irqchip.c usage). This is not the case for
> arm/arm64 currently.
>
> This patch unsets the flag for both arm and arm64.
>
> Signed-off-by: Eric Auger
> Acked-by: Chr
On 01/15/2015 02:47 PM, Eric Auger wrote:
> On arm/arm64 the VGIC is dynamically instantiated and it is useful
> to expose its state, especially for irqfd setup.
>
> This patch defines __KVM_HAVE_ARCH_INTC_INITIALIZED and
> implements kvm_arch_intc_initialized.
>
> Signed-off-by: Eric Auger
> Ac
Hi Eric,
On 01/15/2015 02:47 PM, Eric Auger wrote:
> Introduce __KVM_HAVE_ARCH_INTC_INITIALIZED define and
> associated kvm_arch_intc_initialized function. This latter
> allows to test whether the virtual interrupt controller is initialized
> and ready to accept virtual IRQ injection. On some arch
Hi Eric,
On 01/15/2015 02:47 PM, Eric Auger wrote:
> This patch enables irqfd on arm/arm64.
>
> Both irqfd and resamplefd are supported. Injection is implemented
> in vgic.c without routing.
>
> This patch enables CONFIG_HAVE_KVM_EVENTFD and CONFIG_HAVE_KVM_IRQFD.
>
> KVM_CAP_IRQFD is now adver
On 27/04/18 10:23, Icenowy Zheng wrote:
>
>
> 于 2018年4月27日 GMT+08:00 下午5:18:23, Andre Przywara 写到:
>> Hi,
>>
>> On 27/04/18 09:36, Icenowy Zheng wrote:
>>>
>>>
>>> 于 2018年4月27日 GMT+08:00 上午12:45:38, Andre Przywara
>> 写到:
Hi,
On 26/04/18 15:07, Icenowy Zheng wrote:
> The Allwi
On 06/02/2019 19:24, Jeremy Linton wrote:
> Hi,
>
>
> I just realized I replied to this off-list.
>
> On 01/30/2019 12:02 PM, Andre Przywara wrote:
>> On Fri, 25 Jan 2019 12:07:00 -0600
>> Jeremy Linton wrote:
>>
>> Hi,
>>
>>> For a while Arm64 has been capable of force enabling
>>> or disablin
On 03/12/2020 16:20, Chen-Yu Tsai wrote:
Hi,
> On Thu, Dec 3, 2020 at 11:45 PM André Przywara wrote:
>>
>> On 03/12/2020 15:02, Chen-Yu Tsai wrote:
>>> On Thu, Dec 3, 2020 at 6:54 PM André Przywara
>>> wrote:
>>>>
>>>> On 03/12/2020 03
On 09/12/2020 14:33, Clément Péron wrote:
Hi,
> I try to review this, and compare against the vendor Kernel>
> On Wed, 2 Dec 2020 at 14:54, Andre Przywara wrote:
>>
>> While the clocks are fairly similar to the H6, many differ in tiny
>> details, so a separate clock driver seems indicated.
>>
>>
On 09/12/2020 22:20, Jernej Škrabec wrote:
> Dne sreda, 09. december 2020 ob 22:35:51 CET je André Przywara napisal(a):
>> On 09/12/2020 14:33, Clément Péron wrote:
>>
>> Hi,
>>
>>> I try to review this, and compare against the vendor Kernel>
>>>
On 10/12/2020 13:31, Icenowy Zheng wrote:
> 在 2020-12-02星期三的 13:54 +，Andre Przywara写道：
>> While the clocks are fairly similar to the H6, many differ in tiny
>> details, so a separate clock driver seems indicated.
>>
>> Derived from the H6 clock driver, and adjusted according to the
>> manual.
>
On 19/11/2020 13:41, Ard Biesheuvel wrote:
Hi,
> On Fri, 13 Nov 2020 at 19:24, Andre Przywara wrote:
>>
>> The ARM architected TRNG firmware interface, described in ARM spec
>> DEN0098, defines an ARM SMCCC based interface to a true random number
>> generator, provided by firmware.
>> This can b
On 06/12/2020 12:42, Jernej Škrabec wrote:
Hi,
> Dne nedelja, 06. december 2020 ob 13:32:49 CET je Clément Péron napisal(a):
>> Hi Andre,
>>
>> On Wed, 2 Dec 2020 at 14:54, Andre Przywara wrote:
>>> Port A is used for an internal connection to some analogue circuitry
>>> which looks like an AC20
On 06/12/2020 16:01, Icenowy Zheng wrote:
Hi,
> 于 2020年12月6日 GMT+08:00 下午10:52:17, "André Przywara"
> 写到:
>> On 06/12/2020 12:42, Jernej Škrabec wrote:
>>
>> Hi,
>>
>>> Dne nedelja, 06. december 2020 ob 13:32:49 CET je Clément Péron
>> nap
On 10/11/2020 06:40, Frank Lee wrote:
Hi,
> From: Yangtao Li
>
> Add support for a100's usb phy, which with 2 PHYs.
>
> Signed-off-by: Yangtao Li
> ---
> drivers/phy/allwinner/phy-sun4i-usb.c | 19 +++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/phy/allwinne
On 07/12/2020 01:07, André Przywara wrote:
> On 06/12/2020 16:01, Icenowy Zheng wrote:
>
> Hi,
>
>>>>>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 16)), /*
>>> PI_EINT16 */
>>>>>> +};
>>>>>> +static cons
On 02/12/2020 16:03, Icenowy Zheng wrote:
> 在 2020-12-02星期三的 13:54 +，Andre Przywara写道：
>> This (relatively) new SoC is similar to the H6, but drops the
>> (broken)
>> PCIe support and the USB 3.0 controller. It also gets the management
>> controller removed, which in turn removes *some*, but no
On 02/12/2020 15:57, Icenowy Zheng wrote:
> 在 2020-12-02星期三的 13:54 +，Andre Przywara写道：
>> The OrangePi Zero 2 is a development board with the new H616 SoC.
>>
>> It features the usual connectors used on those small boards, and
>> comes
>> with the AXP305, which seems to be compatible with the A
On 02/12/2020 21:03, Jernej Škrabec wrote:
> Dne sreda, 02. december 2020 ob 14:54:06 CET je Andre Przywara napisal(a):
>> While the clocks are fairly similar to the H6, many differ in tiny
>> details, so a separate clock driver seems indicated.
>>
>> Derived from the H6 clock driver, and adjusted
On 02/12/2020 16:33, Jernej Škrabec wrote:
Hi,
> Dne sreda, 02. december 2020 ob 14:54:08 CET je Andre Przywara napisal(a):
>> This (relatively) new SoC is similar to the H6, but drops the (broken)
>> PCIe support and the USB 3.0 controller. It also gets the management
>> controller removed, whic
On 02/12/2020 18:20, Jernej Škrabec wrote:
Hi,
> Dne sreda, 02. december 2020 ob 14:54:05 CET je Andre Przywara napisal(a):
>> The clocks itself are identical to the H6 R-CCU, it's just that the H616
>> has not all of them implemented (or connected).
>>
>> Signed-off-by: Andre Przywara
>> ---
>>
On 03/12/2020 03:16, Samuel Holland wrote:
Hi,
> On 12/2/20 7:54 AM, Andre Przywara wrote:
> ...
>> +soc {
>> +compatible = "simple-bus";
>> +#address-cells = <1>;
>> +#size-cells = <1>;
>> +ranges = <0x0 0x0 0x0 0x4000>;
>> +
>> +
On 02/12/2020 14:31, Icenowy Zheng wrote:
Hi,
> 于 2020年12月2日 GMT+08:00 下午9:54:05, Andre Przywara 写到:
>> The clocks itself are identical to the H6 R-CCU, it's just that the
>> H616
>> has not all of them implemented (or connected).
>
> For selective clocks, try to follow the practice of V3(s) dr
On 03/12/2020 15:02, Chen-Yu Tsai wrote:
> On Thu, Dec 3, 2020 at 6:54 PM André Przywara wrote:
>>
>> On 03/12/2020 03:16, Samuel Holland wrote:
>>
>> Hi,
>>
>>> On 12/2/20 7:54 AM, Andre Przywara wrote:
>>> ...
>>
On 03/01/2021 10:00, Samuel Holland wrote:
> On boards where the only peripheral connected to PL0/PL1 is an X-Powers
> PMIC, configure the connection to use the RSB bus rather than the I2C
> bus. Compared to the I2C controller that shares the pins, the RSB
> controller allows a higher bus frequency
On 13/12/2020 17:47, Icenowy Zheng wrote:
Hi Icenowy,
> 在 2020-12-11星期五的 01:19 +，Andre Przywara写道：
>> Hi,
>>
>> this is the quite expanded second version of the support series for
>> the
>> Allwinner H616 SoC.
>> Besides many fixes for the bugs discovered by the diligent reviewers
>> (many th
On 13/12/2020 18:24, Icenowy Zheng wrote:
> 在 2020-12-11星期五的 01:19 +，Andre Przywara写道：
>> Newer SoCs (A100, H616) need to clear a different bit in our
>> "unknown"
>> PMU PHY register.
>
> It looks like that the unknown PHY register is PHYCTL register for each
> individual PHY, and the bit tha
On 15/12/2020 03:25, Samuel Holland wrote:
> On 12/14/20 8:57 AM, Maxime Ripard wrote:
>> Hi Samuel,
>>
>> On Sun, Dec 13, 2020 at 05:55:03PM -0600, Samuel Holland wrote:
>>> While no information about the H6 RSB controller is included in the
>>> datasheet or manual, the vendor BSP and power manage
On 10/11/2020 06:40, Frank Lee wrote:
Hi,
> From: Yangtao Li
>
> Add support for a100's usb phy, which with 2 PHYs.
>
> Signed-off-by: Yangtao Li
> ---
> drivers/phy/allwinner/phy-sun4i-usb.c | 19 +++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/phy/allwinner
On 10/11/2020 06:46, Frank Lee wrote:
Hi,
> From: Yangtao Li
>
> This patch adds support for A100 MMC controller, which use word address
> for internal dma.
>
> Signed-off-by: Yangtao Li
> ---
> drivers/mmc/host/sunxi-mmc.c | 28 +---
> 1 file changed, 25 insertions(+
On 10/11/2020 06:48, Frank Lee wrote:
Hi,
> From: Yangtao Li
>
> The A100 has 3 MMC controllers, one of them being especially targeted to
> eMMC. Let's add nodes on dts.
>
> Signed-off-by: Yangtao Li
I don't have a datasheet nor a device for testing, but at least I could
check the pins again
On 11/11/2020 22:50, Rob Herring wrote:
Hi,
> On Tue, Nov 10, 2020 at 02:39:42PM +0800, Frank Lee wrote:
>> From: Yangtao Li
>>
>> Add a device tree binding for the A100's USB PHY.
Not your fault, Yangto, but why do we actually have a separate binding
document per SoC, when the differences betw
On 10/11/2020 06:28, Frank Lee wrote:
Hi,
> From: Yangtao Li
>
> The dma of a100 is similar to h6, with some minor changes to
> support greater addressing capabilities.
So apparently those changes are backwards compatible, right?
Why do we need then a new struct now, when this is actually iden
On 10/11/2020 06:29, Frank Lee wrote:
> From: Yangtao Li
>
> The A100 SoC has a DMA controller that supports 8 DMA channels
> to and from various peripherals.
>
> Add a device node for it.
>
> Signed-off-by: Yangtao Li
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 12
>
On 10/11/2020 06:38, Frank Lee wrote:
> From: Yangtao Li
>
> Declare A100's watchdog in the device-tree.
>
> Signed-off-by: Yangtao Li
I don't have any manual nor hardware, but this node looks alright, when
compared to the H6 one.
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> arch/arm
On 10/11/2020 06:31, Frank Lee wrote:
Hi,
> From: Yangtao Li
>
> Add the Performance Monitoring Unit (PMU) device tree node to the A100
> .dtsi, which tells DT users which interrupts are triggered by PMU overflow
> events on each core.
Have you tested that the interrupts actually work? For the
On 28/11/2020 19:56, André Przywara wrote:
> On 10/11/2020 06:46, Frank Lee wrote:
Hi,
one more thing below ...
>> From: Yangtao Li
>>
>> This patch adds support for A100 MMC controller, which use word address
>> for internal dma.
>>
>> Signed-off-by:
On 07/03/16 11:04, Stephen Rothwell wrote:
> Hi Wim,
>
> Today's linux-next merge of the watchdog tree got a conflict in:
>
> arch/arm64/boot/dts/arm/foundation-v8.dts
>
> between commit:
>
> d11a89796678 ("arm64: dts: split Foundation model dts to put the GIC
> separately")
>
> from the
On 08/03/16 23:06, Sudeep Holla wrote:
Hi Sudeep,
> On 08/03/16 15:52, André Przywara wrote:
>> On 07/03/16 11:04, Stephen Rothwell wrote:
>>> Hi Wim,
>>>
>>> Today's linux-next merge of the watchdog tree got a conflict in:
>>>
>>>
On 23/09/2019 07:36, Peng Fan wrote:
Hi Peng,
thanks for the update!
> From: Peng Fan
>
> V7:
> Typo fix
> #mbox-cells changed to 0
> Add a new header file arm-smccc-mbox.h
> Use ARM_SMCCC_IS_64
>
> Andre,
> The function_id is still kept in arm_smccc_mbox_cmd, because arm,func-id
> property
On 24/05/2019 18:56, Sudeep Holla wrote:
> On Thu, May 23, 2019 at 10:30:50AM -0700, Florian Fainelli wrote:
Hi,
>> On 5/22/19 10:50 PM, Peng Fan wrote:
>>> This is a modified version from Andre Przywara's patch series
>>> https://lore.kernel.org/patchwork/cover/812997/.
>>> [1] is a draft implem
On 14/05/2019 18:20, James Morse wrote:
Hi James,
> (thanks for digging into this!)
>
> On 10/05/2019 18:39, Andre Przywara wrote:
>> On Sat, 9 Feb 2019 18:50:39 -0800
>> Fenghua Yu wrote:
>>> From: Babu Moger
>>>
>>> RESCTRL feature is supported both on Intel and AMD now. Some features
>>> a
On 25/06/2019 08:20, Peng Fan wrote:
> Hi Jassi,
>
>> -Original Message-
>> From: Jassi Brar [mailto:jassisinghb...@gmail.com]
>> Sent: 2019年6月21日 0:50
>> To: Peng Fan
>> Cc: Rob Herring ; Mark Rutland
>> ; Sudeep Holla ; Florian
>> Fainelli ; , Sascha Hauer ;
>> dl-linux-imx ; Shawn Guo
On 18/03/18 12:52, Rob Herring wrote:
> On Thu, Mar 15, 2018 at 04:25:09PM +, Harald Geyer wrote:
>> This device is compatible with A13, so no new driver is needed.
>> A new compatible string is reserved in the binding documentation, to be
>> used together with the proper fall back. Tested on T
On 05/01/17 17:57, Maxime Ripard wrote:
> Hi Rob,
>
> On Wed, Jan 04, 2017 at 08:07:50AM -0600, Rob Herring wrote:
>> On Mon, Jan 02, 2017 at 11:03:43PM +, Andre Przywara wrote:
>>> From: Maxime Ripard
>>>
>>> Unlike the A64 user manual reports, the third MMC controller on the
>>> A64 (and th
On 05/01/17 15:35, Maxime Ripard wrote:
Hi Maxime,
> On Wed, Jan 04, 2017 at 02:16:23AM +0000, André Przywara wrote:
>> So can I ask that we start taking this seriously and stop doing things
>> which prevent Allwinner boards from being supported properly?
>> Which would f
On 05/01/17 17:47, Maxime Ripard wrote:
Hi,
> On Mon, Jan 02, 2017 at 11:03:42PM +, Andre Przywara wrote:
>> The calibration facility in the A64 MMC block seems to have been
>> misunderstood: the result value is not the value to program into the
>> delay bits, but is the number of delay cells
On 05/01/17 22:42, Maxime Ripard wrote:
> On Fri, Dec 30, 2016 at 01:55:44PM +0100, Linus Walleij wrote:
>> On Mon, Dec 26, 2016 at 3:33 PM, André Przywara
>> wrote:
>>
>>> So while this patch technically looks correct, I was wondering if we
>>> should r
On 09/01/17 16:46, Maxime Ripard wrote:
> Experience have shown that the using the autocalibration could severely
> degrade the performances of the MMC bus.
>
> Allwinner is using in its BSP a delay set to 0 for all the modes but HS400.
> Remove the calibration code for now, and add comments to d
On 09/01/17 16:46, Maxime Ripard wrote:
> The A64 only has a single set of pins for each MMC controller. Since we
> already have boards that require all of them, let's add them to the DTSI.
This matches my reworked version from the previous series, so:
Reviewed-by: Andre Przywara
Cheers,
Andre.
On 29/01/17 02:33, Icenowy Zheng wrote:
> From: Andre Przywara
(Adding DT folks to CC:)
see below ...
> The new Allwinner H5 SoC is pin-compatible to the H3 SoC, but with the
> Cortex-A7 cores replaced by Cortex-A53 cores and the MMC controller
> updated. So we should really share almost the wh
Salut,
On 11/10/16 15:28, Maxime Ripard wrote:
> Modify the current clocks we have to be able to specify the minimum for
> each clocks we support, just like we support the max.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/clk/sunxi-ng/ccu_mult.c | 7 ++-
> drivers/clk/sunxi-ng/ccu_nk.c
On 20/10/16 19:00, Maxime Ripard wrote:
Hi Maxime,
> From: Andre Przywara
>
> The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores
> and the typical tablet / TV box peripherals.
> The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of
> the peripherals and the memor
On 27/11/16 09:36, Icenowy Zheng wrote:
Hi,
> 22.11.2016, 00:26, "Icenowy Zheng" :
>> Orange Pi Zero is a board that came with the new Allwinner H2+ SoC.
>>
>> Add a device tree file for it.
>>
>> Signed-off-by: Icenowy Zheng
>> ---
>> Changes since v2:
>> - Use generic pinconf binding instead o
On 03/01/17 02:52, Chen-Yu Tsai wrote:
Hi,
> On Tue, Jan 3, 2017 at 7:03 AM, Andre Przywara wrote:
>
> A commit message explaining the mmc controllers would be nice.
OK.
>> Signed-off-by: Andre Przywara
>> ---
>> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 67
>> +++
On 03/01/17 13:28, Chen-Yu Tsai wrote:
> On Tue, Jan 3, 2017 at 6:48 PM, André Przywara wrote:
>> On 03/01/17 02:52, Chen-Yu Tsai wrote:
Hi Chen-Yu,
>>> On Tue, Jan 3, 2017 at 7:03 AM, Andre Przywara
>>> wrote:
>>>
>>> A commit message explainin
On 18/10/16 08:43, Chen-Yu Tsai wrote:
Hi Maxime, Chen-Yu,
I just stumbled over this patch in Maxime's -next tree and think I
missed it before. I guess it's a bit late, but I just wanted to express
my concerns and write out the issues with the current DT approach:
> On Tue, Oct 11, 2016 at 11:46
Hi,
On 23/12/16 12:50, Icenowy Zheng wrote:
> Based on the Allwinner H5 datasheet and the pinctrl driver of the
> backward-compatible H3 this introduces the pin multiplex assignments for
> the H5 SoC.
>
> H5 introduced some more pin functions (e.g. three more groups of TS
> pins, and one more gro
On 02/11/16 21:50, Maxime Ripard wrote:
> From: Andre Przywara
>
> The Pine64 is a cost-efficient development board based on the
> Allwinner A64 SoC.
> There are three models: the basic version with Fast Ethernet and
> 512 MB of DRAM (Pine64) and two Pine64+ versions, which both
> feature Gigabit
On 10/08/16 16:01, Icenowy Zheng wrote:
Hi,
> 09.08.2016, 19:58, "Andre Przywara" :
>> The MMC controllers in the Allwinner A64 SoC are somewhat compatible
>> with the versions used in other Allwinner SoCs.
>> Tell Linux about the three MMC clocks that the firmware implements and
>> add nodes
On 10/08/16 16:10, Icenowy Zheng wrote:
>
>
> 09.08.2016, 19:57, "Andre Przywara" :
>> Hi,
>>
>> this is a proof-of-concept series to demonstrate the usage of firmware
>> driven clocks using the SCPI protocol for Allwinner SoCs.
>> This aims to replace the tricky and highly SoC specific clocks dr
On 01/08/16 10:11, Chen-Yu Tsai wrote:
> Hi,
Hi Chen-Yu,
thanks for your comments, just found some time to come back to this.
>
> On Mon, Aug 1, 2016 at 9:43 AM, André Przywara wrote:
>> Hi Maxime,
>>
>> On 26/07/16 21:30, Maxime Ripard wrote:
>>> Hi,
>
On 03/06/16 10:56, LABBE Corentin wrote:
Hi,
first: thanks for posting this and the time and work that you spent on
it. With the respective DT nodes this works for me on the Pine64 and
turns this board eventually into something useful.
Some comments below:
> This patch add support for sun8i-ema
On 01/03/16 22:46, Andreas Färber wrote:
> Am 01.03.2016 um 13:43 schrieb Andre Przywara:
>> On 01/03/16 11:18, Andreas Färber wrote:
>>> Am 01.03.2016 um 12:01 schrieb Andre Przywara:
On 29/02/16 23:44, Andreas Färber wrote:
> reg = <0x0 0xc4301000 0 0x1000>,
> -
On 01/03/16 23:31, Andreas Färber wrote:
> Hi,
>
> Am 01.03.2016 um 13:43 schrieb Andre Przywara:
>> On 01/03/16 11:18, Andreas Färber wrote:
>>> Am 01.03.2016 um 12:01 schrieb Andre Przywara:
On 29/02/16 23:44, Andreas Färber wrote:
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.d
Hi,
On 02/03/16 01:16, Will Deacon wrote:
> On Tue, Mar 01, 2016 at 04:49:37PM +, Andre Przywara wrote:
>> When we set up GSI routing to map MSIs to KVM's GSI numbers, we
>> write the current device's MSI setup into the kernel routing table.
>> However the device driver in the guest can use PC
Hi Arnd,
On 12/22/15 22:06, Arnd Bergmann wrote:
> On Tuesday 22 December 2015, Andre Przywara wrote:
>> The min3() macro expects all arguments to be of the same type (or
>> size at least). While two arguments are ints or u32s, one is size_t,
>> which does not match on 64-bit architectures.
>> Cast
On 01/02/16 18:27, Karsten Merker wrote:
Hi Karsten,
thank you very much for your feedback!
> On Mon, Feb 01, 2016 at 05:39:24PM +, Andre Przywara wrote:
>> Based on the Allwinner A64 user manual and on the previous sunxi
>> pinctrl drivers this introduces the pin multiplex assignments for
>
On 01/02/16 18:40, Jean-Francois Moine wrote:
> On Mon, 1 Feb 2016 17:39:25 +
> Andre Przywara wrote:
>
>> The Allwinner H3 SoC introduced bus clock gates with potentially
>> different parents per clock gate. The H3 driver chose to hardcode the
>> actual parent clock relation in the code.
>>
On 01/02/16 18:45, Karsten Merker wrote:
> Hello,
>
> I by mistake pressed "send" on my previous mail when I intended
> to further edit it, so here comes a followup.
> I definitely need more coffee ;-).
Or less? ;-) vv Thinking of twitchy fingers...
> On Mon, Feb 01, 2016 at
On 01/02/16 19:05, Karsten Merker wrote:
> Hello,
>
> a few tiny spelling nitpicks in case you should do a V2:
Definitely! ;-)
>
> On Mon, Feb 01, 2016 at 05:39:29PM +, Andre Przywara wrote:
>
>> The Allwinner A64 SoC is low-cost SoC with 4 ARM Cortex-A53 cores
>
> s/is low-cost SoC/is a
On 01/02/16 19:22, Karsten Merker wrote:
Hi,
> On Mon, Feb 01, 2016 at 05:39:30PM +, Andre Przywara wrote:
>> The Pine64 is a cost-efficient development board based on the
>> Allwinner A64 SoC.
>> There are three models: the basic version with Fast Ethernet and
>> 512 MB of DRAM (Pine64) and
On 02/02/16 07:57, lists.nick.betteri...@gmail.com wrote:
> Just a quick question - will there be any support for enabling booting into
> virtualisation mode to run xen and the like?
This is a firmware issue. The SoC itself provides everything you need
and even Allwinner choosing ARM Trusted Firm
Hi,
On 18/01/16 14:28, Lee Jones wrote:
> This call matches clocks which have been marked as critical in DT
> and sets the appropriate flag. These flags can then be used to
> mark the clock core flags appropriately prior to registration.
I like the idea of having a generic property very much. Al
On 03/07/2020 06:38, kernelci.org bot wrote:
Hi Guillaume,
is this report legit? The situation didn't change from Monday, I just
repeated the test with mainline compared to my patch reverted.
What is the actual failure here? You pointed to:
<2>GIC CPU mask not found - kernel will fail to boot.
b
On 26/08/2020 19:42, Florian Fainelli wrote:
Hi,
> On 8/26/20 11:38 AM, Andre Przywara wrote:
>> The DT binding for SP804 requires to have an "arm,primecell" compatible
>> string.
>> Add this string so that the Linux primecell bus driver picks the device
>> up and activates the clock.
>>
>> Signe
On 07/10/2020 15:16, James Morse wrote:
Hi,
> On 06/10/2020 21:18, Andre Przywara wrote:
>> The ARM architected TRNG firmware interface, described in ARM spec
>> DEN0098[1], defines an ARM SMCCC based interface to a true random number
>> generator, provided by firmware.
>> This can be discovered
On 29/09/2020 14:39, Leo Yan wrote:
> Include header linux/bitops.h, directly use its BIT() macro and remove
> the self defined macros.
>
> Signed-off-by: Leo Yan
Reviewed-by: Andre Przywara
Thanks,
Andre
> ---
> tools/perf/util/arm-spe-decoder/arm-spe-decoder.c | 5 +
> tools/perf/u
On 29/09/2020 14:39, Leo Yan wrote:
> Fix a typo: s/iff/if.
>
> Signed-off-by: Leo Yan
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tools/perf/util/arm-spe-dec
On 29/09/2020 14:39, Leo Yan wrote:
Hi Leo,
> Defines macro for payload length calculation instead of static function.
What is the reason for that? I thought the kernel's direction is more
the other way: replacing macros with static functions ("Don't write CPP,
write C")? Ideally the compiler wo
On 29/09/2020 14:39, Leo Yan wrote:
> When process address packet and counter packet, if the packet contains
processing
> extended header, it misses to account the extra one byte for header
> length calculation, thus returns the wrong packet length.
>
> To correct the packet length calcul
On 29/09/2020 14:39, Leo Yan wrote:
Hi,
> When outputs strings to the decoding buffer with function snprintf(),
> SPE decoder needs to detects if any error returns from snprintf() and if
> so needs to directly bail out. If snprintf() returns success, it needs
> to update buffer pointer and reduc
On 29/09/2020 14:39, Leo Yan wrote:
Hi Leo,
> The packet header parsing uses the hard coded values and it uses nested
> if-else statements.
>
> To improve the readability, this patch refactors the macros for packet
> header format so it removes the hard coded values. Furthermore, based
> on the
On 27/09/2020 04:30, Leo Yan wrote:
Hi Leo,
> On Tue, Sep 22, 2020 at 11:12:25AM +0100, Andre Przywara wrote:
>> The Scalable Vector Extension (SVE) is an ARMv8 architecture extension
>> that introduces very long vector operations (up to 2048 bits).
>> The SPE profiling feature can tag SVE instru
On 28/09/2020 14:21, Dave Martin wrote:
Hi Dave,
> On Tue, Sep 22, 2020 at 11:12:25AM +0100, Andre Przywara wrote:
>> The Scalable Vector Extension (SVE) is an ARMv8 architecture extension
>> that introduces very long vector operations (up to 2048 bits).
>
> (8192, in fact, though don't expect t
On 26/08/2020 21:55, Florian Fainelli wrote:
> On 8/26/20 11:59 AM, Florian Fainelli wrote:
>> On 8/26/20 11:53 AM, André Przywara wrote:
>>> On 26/08/2020 19:42, Florian Fainelli wrote:
Hi Florian,
>>>
>>> Hi,
>>>
>>>> On 8/26/20 11:38
On 28/08/2020 15:03, Linus Walleij wrote:
Hi,
> On Wed, Aug 26, 2020 at 8:38 PM Andre Przywara wrote:
>
>> The SP804 DT nodes for Realview, MPS2 and VExpress were not complying
>> with the binding: it requires either one or three clocks, but does not
>> allow exactly two clocks.
>>
>> Simply du
On 28/08/2020 15:54, Linus Walleij wrote:
Hi,
> On Fri, Aug 28, 2020 at 4:20 PM Andre Przywara wrote:
>
>> This is the second attempt at converting the SP804 timer binding to yaml.
>> Compared to v1, I forbid additional properties, and included the primecell
>> binding. Also the clock-names pro
On 02/09/2020 00:04, Florian Fainelli wrote:
Hi Florian,
sorry, the mail got swamped in my inbox...
> On 8/28/2020 10:12 AM, Florian Fainelli wrote:
>> On 8/28/20 7:20 AM, Andre Przywara wrote:
>>> The DT binding for SP804 requires to have an "arm,primecell" compatible
>>> string.
>>> Add this s
On 24/08/2020 13:49, Robert Richter wrote:
> I do not have hardware anymore, nor there is ongoing development. So
> handover maintenance to Andre who already maintains the last
> remainings of Calxeda.
>
> Cc: Andre Przywara
> Signed-off-by: Robert Richter
Acked-by: Andre Przywara
Thanks!
And
On 28/08/2020 22:32, Florian Fainelli wrote:
Hi,
Florian, thanks for queueing the Broadcom specific patches!
> On 8/28/20 2:28 PM, Rob Herring wrote:
>> On Fri, Aug 28, 2020 at 1:34 PM Florian Fainelli
>> wrote:
>>>
>>> On 8/28/20 6:05 AM, Andre Przywara wrote:
This is an attempt to conve
On 04/09/2020 16:29, Florian Fainelli wrote:
Hi,
> On 9/4/2020 1:58 AM, Linus Walleij wrote:>> On Fri, Aug 28, 2020 at 9:34 PM
> Florian Fainelli
>> wrote:
>>> On 8/28/20 6:05 AM, Andre Przywara wrote:
>>
>>> What is the plan for merging this series? Should Rob pick up all changes
>>> or since
On 27/10/2020 03:09, Leo Yan wrote:
> Defines macros for operation packet header and formats (support sub
> classes for 'other', 'branch', 'load and store', etc). Uses these
> macros for operation packet decoding and dumping.
>
> Signed-off-by: Leo Yan
Looks good now, thanks!
Reviewed-by: Andr
1 - 100 of 174 matches
Mail list logo
