On 6/22/2018 6:41 AM, Ezequiel Garcia wrote:
Hey Enric,
On Fri, 2018-06-22 at 00:04 +0200, Enric Balletbo i Serra wrote:
When the devfreq driver and the governor driver are built as modules,
the call to devfreq_add_device() or governor_store() fails because
the
governor driver is not loaded a
On 6/22/2018 1:52 PM, Enric Balletbo i Serra wrote:
Hi Ezequiel and Akhil,
On 22/06/18 09:03, Akhil P Oommen wrote:
On 6/22/2018 6:41 AM, Ezequiel Garcia wrote:
Hey Enric,
On Fri, 2018-06-22 at 00:04 +0200, Enric Balletbo i Serra wrote:
When the devfreq driver and the governor driver are
driver. We can improve here by exposing a DEVFREQ API
to allow the device drivers to send generic alerts to the governor.
Signed-off-by: Akhil P Oommen
---
drivers/devfreq/devfreq.c | 21 +
drivers/devfreq/governor.h | 1 +
include/linux/devfreq.h| 5 +
3 files
governor more coupled to a
particular device driver. We can improve here by exposing a DEVFREQ API
to allow the device drivers to send generic alerts to the governor.
Signed-off-by: Akhil P Oommen
---
drivers/devfreq/devfreq.c | 21 +
drivers/devfreq/governor.h | 1
On 2/11/2021 9:32 PM, Jordan Crouse wrote:
On Thu, Feb 11, 2021 at 06:50:28PM +0530, Akhil P Oommen wrote:
On 2/10/2021 6:22 AM, Jordan Crouse wrote:
Most a6xx targets have security issues that were fixed with new versions
of the microcode(s). Make sure that we are booting with a safe version
On 2/10/2021 6:22 AM, Jordan Crouse wrote:
Most a6xx targets have security issues that were fixed with new versions
of the microcode(s). Make sure that we are booting with a safe version of
the microcode for the target and print a message and error if not.
v2: Add more informative error messages
On 2/17/2021 8:36 AM, Rob Clark wrote:
On Tue, Feb 16, 2021 at 12:10 PM Jonathan Marek wrote:
Ignore nvmem_cell_get() EOPNOTSUPP error in the same way as a ENOENT error,
to fix the case where the kernel was compiled without CONFIG_NVMEM.
Fixes: fe7952c629da ("drm/msm: Add speed-bin support to
On 2/18/2021 2:05 AM, Jonathan Marek wrote:
On 2/17/21 3:18 PM, Rob Clark wrote:
On Wed, Feb 17, 2021 at 11:08 AM Jordan Crouse
wrote:
On Wed, Feb 17, 2021 at 07:14:16PM +0530, Akhil P Oommen wrote:
On 2/17/2021 8:36 AM, Rob Clark wrote:
On Tue, Feb 16, 2021 at 12:10 PM Jonathan Marek
On 2/18/2021 9:41 PM, Rob Clark wrote:
On Thu, Feb 18, 2021 at 4:28 AM Akhil P Oommen wrote:
On 2/18/2021 2:05 AM, Jonathan Marek wrote:
On 2/17/21 3:18 PM, Rob Clark wrote:
On Wed, Feb 17, 2021 at 11:08 AM Jordan Crouse
wrote:
On Wed, Feb 17, 2021 at 07:14:16PM +0530, Akhil P Oommen
On 2/3/2021 4:22 AM, Bjorn Andersson wrote:
On Fri 08 Jan 12:15 CST 2021, Akhil P Oommen wrote:
Please align the $subject prefix with other changes in the same file.
I fixed it up while picking up the patch this time.
Will take of this in future. Thanks, Bjorn.
-Akhil.
Regards,
Bjorn
Add
gem_submit_reloc));
/* check for overflow: */
Reviewed-by: Akhil P Oommen
-Akhil.
Reviewed-by: Akhil P Oommen
On 8/18/2020 3:31 AM, Rob Clark wrote:
From: Jordan Crouse
Add support for using per-instance pagetables if all the dependencies are
available.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 63
On 12/7/2020 4:12 PM, Akhil P Oommen wrote:
Some GPUs support different max frequencies depending on the platform.
To identify the correct variant, we should check the gpu speedbin
fuse value. Add support for this speedbin detection to a6xx family
along with the required fuse details for a618
On 12/7/2020 4:12 PM, Akhil P Oommen wrote:
Add support for gpu fuse to help identify the supported opps.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
Some GPUs support different max frequencies depending on the platform.
To identify the correct variant, we should check the gpu speedbin
fuse value. Add support for this speedbin detection to a6xx family
along with the required fuse details for a618 gpu.
Signed-off-by: Akhil P Oommen
---
Changes
Add support for gpu fuse to help identify the supported opps.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index
Add support for gpu fuse to help identify the supported opps.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index
Some GPUs support different max frequencies depending on the platform.
To identify the correct variant, we should check the gpu speedbin
fuse value. Add support for this speedbin detection to a6xx family
along with the required fuse details for a618 gpu.
Signed-off-by: Akhil P Oommen
---
Changes
DRM_DEV_ERROR(dev,
"failed to read speed-bin (%d). Some OPPs may not be
supported by hardware",
ret);
Reviewed-by: Akhil P Oommen
This looks "fine" to me. ;)
-Akhil.
struct msm_drm_private *priv =
dev->dev_private;
060530f1ea6740 Rob Clark 2014-03-03 521 struct platform_device *pdev =
priv->gpu_pdev;
5785dd7a8ef0de Akhil P Oommen 2020-10-28 522 struct icc_path *ocmem_icc_path;
5785dd7a8ef0de Akhil P Oommen 2020-10-28 523 struct icc_path *ic
On 4/2/2021 3:19 AM, Rob Clark wrote:
On Thu, Apr 1, 2021 at 2:03 PM Dmitry Baryshkov
wrote:
On Thu, 1 Apr 2021 at 23:09, Rob Clark wrote:
On Mon, Feb 22, 2021 at 8:06 AM Rob Clark wrote:
On Mon, Feb 22, 2021 at 7:45 AM Akhil P Oommen wrote:
On 2/19/2021 9:30 PM, Rob Clark wrote:
On
The speedbin support requires nvmem driver api. So lets explicitly
enable CONFIG_NVMEM to have this support.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index dabb4a1
We were not programing the correct bit while clearing the perfcounter oob.
So, clear it correctly using the new 'clear' bit. This fixes the below
error:
[drm:a6xx_gmu_set_oob] *ERROR* Timeout waiting for GMU OOB set PERFCOUNTER:
0x8000
Signed-off-by: Akhil P Oommen
---
drivers/g
On 2/19/2021 9:30 PM, Rob Clark wrote:
On Fri, Feb 19, 2021 at 2:44 AM Akhil P Oommen wrote:
On 2/18/2021 9:41 PM, Rob Clark wrote:
On Thu, Feb 18, 2021 at 4:28 AM Akhil P Oommen wrote:
On 2/18/2021 2:05 AM, Jonathan Marek wrote:
On 2/17/21 3:18 PM, Rob Clark wrote:
On Wed, Feb 17, 2021
On 11/30/2020 10:32 PM, Jordan Crouse wrote:
On Fri, Nov 27, 2020 at 06:19:44PM +0530, Akhil P Oommen wrote:
So far a530v2 gpu has support for detecting its supported opps
based on a fuse value called speed-bin. This patch makes this
support generic across gpu families. This is in preparation
<< Resending since Jordan wasn't in the CC list >>
On 11/30/2020 10:32 PM, Jordan Crouse wrote:
On Fri, Nov 27, 2020 at 06:19:44PM +0530, Akhil P Oommen wrote:
So far a530v2 gpu has support for detecting its supported opps
based on a fuse value called speed-bin. This patch m
On 12/2/2020 10:00 PM, Jordan Crouse wrote:
On Wed, Dec 02, 2020 at 08:53:51PM +0530, Akhil P Oommen wrote:
On 11/30/2020 10:32 PM, Jordan Crouse wrote:
On Fri, Nov 27, 2020 at 06:19:44PM +0530, Akhil P Oommen wrote:
So far a530v2 gpu has support for detecting its supported opps
based on a
On 1/22/2021 10:15 AM, Viresh Kumar wrote:
On 22-01-21, 00:41, Dmitry Osipenko wrote:
21.01.2021 14:17, Viresh Kumar пишет:
@@ -1074,15 +1091,18 @@ int dev_pm_opp_set_rate(struct device *dev, unsigned
long target_freq)
if (!ret) {
ret = _set_opp_bw(opp_table, opp, dev, f
On 11/16/2020 9:52 PM, Rob Clark wrote:
On Mon, Nov 16, 2020 at 6:34 AM Akhil P Oommen wrote:
On 11/12/2020 10:07 PM, Rob Clark wrote:
On Thu, Nov 12, 2020 at 7:49 AM Akhil P Oommen wrote:
So far a530v2 gpu has support for detecting its supported opps
based on a fuse value called speed
Extend speed-bin support to a618 gpu.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index e0ff16c..21db7ae 100644
--- a
Add support for gpu fuse to help identify the supported opps.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index
So far a530v2 gpu has support for detecting its supported opps
based on a fuse value called speed-bin. This patch makes this
support generic across gpu families. This is in preparation to
extend speed-bin support to a6x family.
Signed-off-by: Akhil P Oommen
---
Changes from v1:
1. Added
On 11/16/2020 10:44 PM, Jordan Crouse wrote:
On Mon, Nov 16, 2020 at 07:40:03PM +0530, Akhil P Oommen wrote:
On 11/12/2020 10:05 PM, Jordan Crouse wrote:
On Thu, Nov 12, 2020 at 09:19:04PM +0530, Akhil P Oommen wrote:
So far a530v2 gpu has support for detecting its supported opps
based on a
This series adds support for GPU DDR bandwidth scaling and is based on the
bindings from Georgi [1]. This is mostly a rebase of Sharat's patches [2] on the
tip of msm-next branch.
Changes from v4:
- Squashed a patch to another one to fix Jonathan's comment
- Add back the pm_runtime_get_if_in_use()
rat Masetty
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 89 +++
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +-
drivers/gpu/drm/msm/msm_gpu.c | 3 +-
drivers/gpu/drm/msm/msm_gpu.h | 3 +-
4 files changed, 52 inserti
cke
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index a567297..8567e9e 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/b
From: Sharat Masetty
This patch adds the interconnects property to the GPU node. This enables
the GPU->DDR path bandwidth voting.
Signed-off-by: Sharat Masetty
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/a
drm driver.
Signed-off-by: Sharat Masetty
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 25 +
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 856d
: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 8eb5a31..5e9561a 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom
From: Sharat Masetty
Update documentation to list the gpu opp table bindings including the
newly added "opp-peak-kBps" needed for GPU-DDR bandwidth scaling.
Signed-off-by: Sharat Masetty
Acked-by: Rob Herring
Signed-off-by: Akhil P Oommen
---
.../devicetree/bindings/display/m
during GPU wake up during system resume.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index a6f43ff
Register GPU as a devfreq cooling device so that it can be passively
cooled by the thermal framework.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/msm_gpu.c | 13 -
drivers/gpu/drm/msm/msm_gpu.h | 2 ++
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers
Add cooling-cells property and the cooling maps for the gpu tzones
to support GPU cooling.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 29 ++---
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180
On 10/10/2020 12:06 AM, m...@chromium.org wrote:
Hi Akhil,
On Thu, Oct 08, 2020 at 10:39:07PM +0530, Akhil P Oommen wrote:
Register GPU as a devfreq cooling device so that it can be passively
cooled by the thermal framework.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/msm_gpu.c
On 10/12/2020 11:10 PM, m...@chromium.org wrote:
On Mon, Oct 12, 2020 at 07:03:51PM +0530, Akhil P Oommen wrote:
On 10/10/2020 12:06 AM, m...@chromium.org wrote:
Hi Akhil,
On Thu, Oct 08, 2020 at 10:39:07PM +0530, Akhil P Oommen wrote:
Register GPU as a devfreq cooling device so that it can
On 10/13/2020 11:10 PM, m...@chromium.org wrote:
On Tue, Oct 13, 2020 at 07:23:34PM +0530, Akhil P Oommen wrote:
On 10/12/2020 11:10 PM, m...@chromium.org wrote:
On Mon, Oct 12, 2020 at 07:03:51PM +0530, Akhil P Oommen wrote:
On 10/10/2020 12:06 AM, m...@chromium.org wrote:
Hi Akhil,
On Thu
Why don't we move the early return in a6xx_gmu_set_freq() to
msm_devfreq_target() instead?
-Akhil.
On 8/14/2020 12:24 AM, Jonathan Marek wrote:
The patch reorganizing the set_freq function made it so the gmu resume
doesn't always set the frequency, because a6xx_gmu_set_freq() exits early
when
On 8/14/2020 8:11 AM, Rob Clark wrote:
From: Jordan Crouse
Add support for using per-instance pagetables if all the dependencies are
available.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 70 +++
drivers/gpu/drm
On 10/9/2020 10:27 PM, Matthias Kaehlcke wrote:
On Fri, Oct 09, 2020 at 08:05:10AM -0700, Doug Anderson wrote:
Hi,
On Thu, Oct 8, 2020 at 10:10 AM Akhil P Oommen wrote:
Add cooling-cells property and the cooling maps for the gpu tzones
to support GPU cooling.
Signed-off-by: Akhil P Oommen
On 10/19/2020 8:29 PM, Jordan Crouse wrote:
On Mon, Oct 19, 2020 at 06:49:18PM +0530, Akhil P Oommen wrote:
On targets with a6xx gpu, there is a duplicate gpu icc node listed in
the interconnect summary. On these targets, calling
This first sentence is confusing to me. I think the following
Implement the shutdown callback for adreno gpu platform device
to safely shutdown it before a system reboot. This helps to avoid
futher transactions from gpu after the smmu is moved to bypass mode.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 6 ++
1 file
summary from the debugfs.
Signed-off-by: Akhil P Oommen
---
Changes in v2:
1. Minor updates (Jordan)
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 21 +++--
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 20 ++--
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 32
Add cooling device support to gpu. A cooling device is bound to a
thermal zone to allow thermal mitigation.
Signed-off-by: Akhil P Oommen
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings
Register GPU as a devfreq cooling device so that it can be passively
cooled by the thermal framework.
Signed-off-by: Akhil P Oommen
---
Changes in v3:
1. Minor fix in binding documentation (RobH)
Changes in v2:
1. Update the dt bindings documentation
drivers/gpu/drm/msm
Add cooling-cells property and the cooling maps for the gpu tzones
to support GPU cooling.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 30 +++---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180
On 10/29/2020 6:09 AM, m...@chromium.org wrote:
Hi Akhil,
On Wed, Oct 28, 2020 at 07:09:53PM +0530, Akhil P Oommen wrote:
Add cooling-cells property and the cooling maps for the gpu tzones
to support GPU cooling.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 30
Register GPU as a devfreq cooling device so that it can be passively
cooled by the thermal framework.
Signed-off-by: Akhil P Oommen
Reviewed-by: Matthias Kaehlcke
---
Changes in v4:
1. Fix gpu cooling map.
2. Add mka's Reviewed-by tag.
Changes in v3:
1. Minor f
Add cooling device support to gpu. A cooling device is bound to a
thermal zone to allow thermal mitigation.
Signed-off-by: Akhil P Oommen
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings
Add cooling-cells property and the cooling maps for the gpu tzones
to support GPU cooling.
Signed-off-by: Akhil P Oommen
Reviewed-by: Matthias Kaehlcke
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 30 +++---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a
On 10/30/2020 2:18 AM, m...@chromium.org wrote:
On Thu, Oct 29, 2020 at 01:37:19PM +0530, Akhil P Oommen wrote:
Register GPU as a devfreq cooling device so that it can be passively
cooled by the thermal framework.
Signed-off-by: Akhil P Oommen
Reviewed-by: Matthias Kaehlcke
Wait, I did not
Register GPU as a devfreq cooling device so that it can be passively
cooled by the thermal framework.
Signed-off-by: Akhil P Oommen
Tested-by: Matthias Kaehlcke
---
Changes in v5:
1. Update Reviewed-by/Tested-by tags
Changes in v4:
1. Fix gpu cooling map.
2. Add mka&#
Add cooling-cells property and the cooling maps for the gpu tzones
to support GPU cooling.
Signed-off-by: Akhil P Oommen
Reviewed-by: Matthias Kaehlcke
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 30 +++---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a
Add cooling device support to gpu. A cooling device is bound to a
thermal zone to allow thermal mitigation.
Signed-off-by: Akhil P Oommen
Reviewed-by: Matthias Kaehlcke
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a
From: Sharat Masetty
This patch adds the interconnects property to the GPU node. This enables
the GPU->DDR path bandwidth voting.
Signed-off-by: Sharat Masetty
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/a
dwidth vote [2].
[1] https://patchwork.freedesktop.org/series/75291/
[2]
https://kernel.googlesource.com/pub/scm/linux/kernel/git/vireshk/pm/+log/opp/linux-next/
Akhil P Oommen (1):
drm: msm: a6xx: set gpu freq through hfi
Sharat Masetty (6):
dt-bindings: drm/msm/gpu: Document gpu opp ta
drm driver.
Signed-off-by: Sharat Masetty
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 25 +
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index b547
rat Masetty
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 73 ---
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +-
drivers/gpu/drm/msm/msm_gpu.c | 3 +-
drivers/gpu/drm/msm/msm_gpu.h | 3 +-
4 files changed, 38 inserti
Newer targets support changing gpu frequency through HFI. So
use that wherever supported instead of the legacy method.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm
: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 8eb5a31..5e9561a 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom
From: Sharat Masetty
Update documentation to list the gpu opp table bindings including the
newly added "opp-peak-kBps" needed for GPU-DDR bandwidth scaling.
Signed-off-by: Sharat Masetty
Acked-by: Rob Herring
Signed-off-by: Akhil P Oommen
---
.../devicetree/bindings/display/m
cke
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index a567297..8567e9e 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/b
] kswapd+0x624/0x890
[10027.873097] kthread+0x11c/0x12c
[10027.876424] ret_from_fork+0x10/0x18
[10027.880102] Code: f9000bf3 910003fd aa0003f3 d503201f (f9400268)
[10027.886362] ---[ end trace df5849a1a3543251 ]---
[10027.891518] Kernel panic - not syncing: Fatal exception
Signed-off-by: Akhil P
On 10/16/2020 3:49 AM, Matthias Kaehlcke wrote:
Hi,
On Thu, Oct 15, 2020 at 12:07:01AM +0530, man...@codeaurora.org wrote:
On 2020-10-14 18:59, Akhil P Oommen wrote:
On 10/9/2020 10:27 PM, Matthias Kaehlcke wrote:
On Fri, Oct 09, 2020 at 08:05:10AM -0700, Doug Anderson wrote:
Hi,
On Thu
Add cooling-cells property and the cooling maps for the gpu tzones
to support GPU cooling.
Signed-off-by: Akhil P Oommen
---
The thermal policy should be set as 'step_wise' for gpu tzones from
the userspace during boot up.
arch/arm64/boot/dts/qcom/sc7180
Register GPU as a devfreq cooling device so that it can be passively
cooled by the thermal framework.
Signed-off-by: Akhil P Oommen
---
Changes in v2:
1. Update the dt bindings documentation
drivers/gpu/drm/msm/msm_gpu.c | 12
drivers/gpu/drm/msm/msm_gpu.h | 2 ++
2 files
Add cooling device support to gpu. A cooling device is bound to a
thermal zone to allow thermal mitigation.
Signed-off-by: Akhil P Oommen
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings
of_icc_get() to target specific code where it is
required.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 21 +++--
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 20 ++--
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 29
Implement the shutdown callback for adreno gpu platform device
to safely shutdown it before a system reboot. This helps to avoid
futher transactions from gpu after the smmu is moved to bypass mode.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 6 ++
1 file
So far a530v2 gpu has support for detecting its supported opps
based on a fuse value called speed-bin. This patch makes this
support generic across gpu families. This is in preparation to
extend speed-bin support to a6x family.
Signed-off-by: Akhil P Oommen
---
This patch is rebased on top of
On 11/12/2020 10:07 PM, Rob Clark wrote:
On Thu, Nov 12, 2020 at 7:49 AM Akhil P Oommen wrote:
So far a530v2 gpu has support for detecting its supported opps
based on a fuse value called speed-bin. This patch makes this
support generic across gpu families. This is in preparation to
extend
On 11/12/2020 10:05 PM, Jordan Crouse wrote:
On Thu, Nov 12, 2020 at 09:19:04PM +0530, Akhil P Oommen wrote:
So far a530v2 gpu has support for detecting its supported opps
based on a fuse value called speed-bin. This patch makes this
support generic across gpu families. This is in preparation
On 11/5/2020 2:28 AM, Rob Clark wrote:
On Wed, Nov 4, 2020 at 12:03 PM Rob Herring wrote:
On Fri, 30 Oct 2020 16:17:12 +0530, Akhil P Oommen wrote:
Add cooling device support to gpu. A cooling device is bound to a
thermal zone to allow thermal mitigation.
Signed-off-by: Akhil P Oommen
On 7/11/2020 1:11 AM, Rob Clark wrote:
On Thu, Jul 9, 2020 at 1:01 PM Akhil P Oommen wrote:
From: Sharat Masetty
This patches replaces the previously used static DDR vote and uses
dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling
GPU frequency. Also since the icc p
On 7/10/2020 1:34 AM, Jonathan Marek wrote:
On 7/9/20 4:00 PM, Akhil P Oommen wrote:
Newer targets support changing gpu frequency through HFI. So
use that wherever supported instead of the legacy method.
It was already using HFI on newer targets. Don't break it in one
commit then f
On 7/11/2020 2:43 AM, Akhil P Oommen wrote:
On 7/10/2020 1:34 AM, Jonathan Marek wrote:
On 7/9/20 4:00 PM, Akhil P Oommen wrote:
Newer targets support changing gpu frequency through HFI. So
use that wherever supported instead of the legacy method.
It was already using HFI on newer
: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 8eb5a31..1cd2dae 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom
From: Sharat Masetty
Update documentation to list the gpu opp table bindings including the
newly added "opp-peak-kBps" needed for GPU-DDR bandwidth scaling.
Signed-off-by: Sharat Masetty
Acked-by: Rob Herring
Signed-off-by: Akhil P Oommen
---
.../devicetree/bindings/display/m
This series add support for GPU DDR bandwidth scaling and is based on the
bindings from Georgi [1]. This is mostly a rebase of Sharat's patches [2] on the
tip of msm-next branch.
[1]
https://kernel.googlesource.com/pub/scm/linux/kernel/git/vireshk/pm/+log/opp/linux-next/
[2] https://patchwork.fre
From: Sharat Masetty
This patch adds the interconnects property to the GPU node. This enables
the GPU->DDR path bandwidth voting.
Signed-off-by: Sharat Masetty
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/a
cke
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 80fe54b..ff4ddf1 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/b
rat Masetty
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 89 +++
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +-
drivers/gpu/drm/msm/msm_gpu.c | 3 +-
drivers/gpu/drm/msm/msm_gpu.h | 3 +-
4 files changed, 52 inserti
drm driver.
Signed-off-by: Sharat Masetty
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 25 +
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 856d
On 7/15/2020 12:12 AM, Rob Clark wrote:
On Tue, Jul 14, 2020 at 10:10 AM Matthias Kaehlcke wrote:
On Tue, Jul 14, 2020 at 06:55:30PM +0530, Akhil P Oommen wrote:
On targets where GMU is available, GMU takes over the ownership of GX GDSC
during its initialization. So, take a refcount on the
wake up during a system resume.
Signed-off-by: Akhil P Oommen
Reported-by: Matthias Kaehlcke
Tested-by: Matthias Kaehlcke
---
Changes from v1:
- Reworded the commit text
- Added Reported-by & Tested-by tags
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 18 ++
1 file changed
point, it will result in premature purging of this BO.
To fix this, we can replace the active_list with reference counting and
move the BO to inactive list only when this count becomes zero.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/msm_drv.h | 5 ++---
drivers/gpu/drm/msm/msm_gem.c
Leave the inuse count intact on map failure to keep the accounting
accurate.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/msm_gem_vma.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c
b/drivers/gpu/drm/msm/msm_gem_vma.c
index
point, it will result in a premature purging of this BO.
To fix this, we need to refcount BO while doing submit and retire. Then,
it should be moved to inactive list when this refcount becomes 0.
Signed-off-by: Akhil P Oommen
---
Changes in v2:
1. Keep Active List around
2. Put
Leave the inuse count intact on map failure to keep the accounting
accurate.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/msm_gem_vma.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c
b/drivers/gpu/drm/msm/msm_gem_vma.c
index
On 9/23/2020 8:20 PM, Jordan Crouse wrote:
On Tue, Sep 22, 2020 at 08:25:26PM +0530, Akhil P Oommen wrote:
In the case where we have a back-to-back submission that shares the same
BO, this BO will be prematurely moved to inactive_list while retiring the
first submit. But it will be still part
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