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I tried to install my Linux Redhat the Network Monitoring system call Ntop
and the following messages is what I am getting each time I execute make.
I thought Libpcap is what is needed and I installed but it did not help.
Can any body out there help me whit this.
The following is the message th
ndary can be RAM, it's not
valid because there's no 'struct page' for it.
Cc: Andrew Morton
Cc: Mel Gorman
Cc: Vlastimil Babka
Cc: Michal Hocko
Cc: Johannes Weiner
Cc: Yaowei Bai
Cc: Dan Williams
Cc: Joe Perches
Cc: Tejun Heo
Cc: Anthony Liguori
Cc: linux...@kvack.o
ys Vlasenko
Cc: Andrew Morton
Cc: Toshi Kani
Cc: Tony Luck
Cc: linux-kernel@vger.kernel.org
Cc: k...@vger.kernel.org
Cc: x...@kernel.org
Signed-off-by: KarimAllah Ahmed
---
arch/x86/include/asm/e820.h | 1 +
arch/x86/kernel/e820.c | 18 ++
arch/x86/kvm/mmu.c |
Congratulations money was donated to you reply,harold-diam...@outlook.com. for
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Please read
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--
On Wed, 10 Jan 2018 16:32:24 +0100
Pablo Neira Ayuso wrote:
> On Fri, Dec 29, 2017 at 12:08:25PM +0100, Ahmed Abdelsalam wrote:
> > This patch adds a new exetension to iptables to supprt 'srh' match
> > The implementation considers revision 7 of the SRH draft.
> &
On 01/30/2018 10:00 AM, David Woodhouse wrote:
On Tue, 2018-01-30 at 01:10 +0100, KarimAllah Ahmed wrote:
Add direct access to speculation control MSRs for KVM guests. This allows the
guest to protect itself against Spectre V2 using IBRS+IBPB instead of a
retpoline+IBPB based approach.
It
On 01/30/2018 06:49 PM, Jim Mattson wrote:
On Mon, Jan 29, 2018 at 4:10 PM, KarimAllah Ahmed wrote:
[ Based on a patch from Ashok Raj ]
Add direct access to MSR_IA32_SPEC_CTRL for guests. This is needed for
guests that will only mitigate Spectre V2 through IBRS+IBPB and will not
be using a
On 01/30/2018 11:49 PM, Jim Mattson wrote:
On Tue, Jan 30, 2018 at 1:00 PM, KarimAllah Ahmed wrote:
Ooops! I did not think at all about nested :)
This should be addressed now, I hope:
http://git.infradead.org/linux-retpoline.git/commitdiff/f7f0cbba3e0cffcee050a8a5a9597a162d57e572
On 01/31/2018 01:27 AM, Jim Mattson wrote:
On Tue, Jan 30, 2018 at 4:19 PM, Paolo Bonzini wrote:
The new code in nested_vmx_merge_msr_bitmap should be conditional on
vmx->save_spec_ctrl_on_exit.
But then if L1 doesn't use MSR_IA32_SPEC_CTRL itself and it uses the
VM-entry MSR load list to set
Hansen
Cc: Andi Kleen
Cc: Andrea Arcangeli
Cc: Linus Torvalds
Cc: Tim Chen
Cc: Thomas Gleixner
Cc: Dan Williams
Cc: Jun Nakajima
Cc: Paolo Bonzini
Cc: David Woodhouse
Cc: Greg KH
Cc: Andy Lutomirski
Cc: Ashok Raj
Signed-off-by: KarimAllah Ahmed
Signed-off-by: David Woodhouse
---
arch
David Woodhouse
Cc: Greg KH
Cc: Andy Lutomirski
Cc: Ashok Raj
Signed-off-by: KarimAllah Ahmed
Signed-off-by: David Woodhouse
---
v4:
- Add IBRS to kvm_cpuid_8000_0008_ebx_x86_features
- Handling nested guests
v3:
- Save/restore manually
- Fix CPUID handling
- Fix a copy & paste error in th
[dwmw2: Stop using KF() for bits in it, too]
Cc: Paolo Bonzini
Cc: Radim Krčmář
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: H. Peter Anvin
Cc: x...@kernel.org
Cc: k...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Paolo Bonzini
Signed-off-by: KarimAllah Ahmed
Signed-off-by
Signed-off-by: KarimAllah Ahmed
Signed-off-by: David Woodhouse
---
arch/x86/kvm/cpuid.c | 2 +-
arch/x86/kvm/vmx.c | 15 +++
arch/x86/kvm/x86.c | 1 +
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 033004d..1909635
and IBRS_ALL.
v4:
- Add IBRS passthrough for SVM (5/5).
- Handle nested guests properly.
- expose F(IBRS) in kvm_cpuid_8000_0008_ebx_x86_features
Ashok Raj (1):
KVM: x86: Add IBPB support
KarimAllah Ahmed (4):
KVM: x86: Update the reverse_cpuid list to include CPUID_7_EDX
KVM: VMX: Emulate
-send-email-ashok@intel.com
Signed-off-by: David Woodhouse
Signed-off-by: KarimAllah Ahmed
---
arch/x86/kvm/cpuid.c | 11 ++-
arch/x86/kvm/svm.c | 27 +++
arch/x86/kvm/vmx.c | 31 ++-
3 files changed, 67 insertions(+), 2 deletions
On 01/31/2018 05:50 PM, Jim Mattson wrote:
On Wed, Jan 31, 2018 at 5:10 AM, KarimAllah Ahmed wrote:
+ vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
MSR_IA32_PRED_CMD,
+ MSR_TYPE_W);
Why not disable this intercept eage
On 01/31/2018 05:55 PM, Paolo Bonzini wrote:
On 31/01/2018 11:50, Jim Mattson wrote:
+ if (to_vmx(vcpu)->save_spec_ctrl_on_exit) {
+ nested_vmx_disable_intercept_for_msr(
+ msr_bitmap_l1, msr_bitmap_l0,
+ MSR_IA32_PR
[dwmw2: Stop using KF() for bits in it, too]
Cc: Paolo Bonzini
Cc: Radim Krčmář
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: H. Peter Anvin
Cc: x...@kernel.org
Cc: k...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Paolo Bonzini
Signed-off-by: KarimAllah Ahmed
Signed-off-by
for SVM (5/5).
- Handle nested guests properly.
- expose F(IBRS) in kvm_cpuid_8000_0008_ebx_x86_features
Ashok Raj (1):
KVM: x86: Add IBPB support
KarimAllah Ahmed (4):
KVM: x86: Update the reverse_cpuid list to include CPUID_7_EDX
KVM: VMX: Emulate MSR_IA32_ARCH_CAPABILITIES
KVM: VMX
ttp://lkml.kernel.org/r/1515720739-43819-6-git-send-email-ashok@intel.com
Signed-off-by: David Woodhouse
Signed-off-by: KarimAllah Ahmed
v5:
- Use MSR_TYPE_W instead of MSR_TYPE_R for the MSR.
- Always merge the bitmaps unconditionally.
- Add PRED_CMD to direct_access_msrs.
- Also check for
Signed-off-by: KarimAllah Ahmed
Signed-off-by: David Woodhouse
---
arch/x86/kvm/cpuid.c | 2 +-
arch/x86/kvm/vmx.c | 15 +++
arch/x86/kvm/x86.c | 1 +
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 033004d..1909635
Hansen
Cc: Andi Kleen
Cc: Andrea Arcangeli
Cc: Linus Torvalds
Cc: Tim Chen
Cc: Thomas Gleixner
Cc: Dan Williams
Cc: Jun Nakajima
Cc: Paolo Bonzini
Cc: David Woodhouse
Cc: Greg KH
Cc: Andy Lutomirski
Cc: Ashok Raj
Signed-off-by: KarimAllah Ahmed
Signed-off-by: David Woodhouse
---
v5
David Woodhouse
Cc: Greg KH
Cc: Andy Lutomirski
Cc: Ashok Raj
Signed-off-by: KarimAllah Ahmed
Signed-off-by: David Woodhouse
---
v5:
- Also check for X86_FEATURE_SPEC_CTRL for the msr reads/writes
v4:
- Add IBRS to kvm_cpuid_8000_0008_ebx_x86_features
- Handling nested guests
v3:
- Save/re
On 01/31/2018 08:53 PM, Jim Mattson wrote:
On Wed, Jan 31, 2018 at 11:37 AM, KarimAllah Ahmed wrote:
+
+ if (to_vmx(vcpu)->save_spec_ctrl_on_exit) {
+ nested_vmx_disable_intercept_for_msr(
+ msr_bitmap_l1, msr_bitmap
On 01/31/2018 09:28 PM, Konrad Rzeszutek Wilk wrote:
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index d46a61b..2e4e8af 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -2285,6 +2285,7 @@ static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
if (per_cpu(current_vmc
On 01/31/2018 09:18 PM, Jim Mattson wrote:
On Wed, Jan 31, 2018 at 12:01 PM, KarimAllah Ahmed wrote:
but save_spec_ctrl_on_exit is also set for L2 write. So once L2 writes
to it, this condition will be true and then the bitmap will be updated.
So if L1 or any L2 writes to the MSR, then
On 01/31/2018 11:52 PM, KarimAllah Ahmed wrote:
On 01/31/2018 09:18 PM, Jim Mattson wrote:
On Wed, Jan 31, 2018 at 12:01 PM, KarimAllah Ahmed
wrote:
but save_spec_ctrl_on_exit is also set for L2 write. So once L2 writes
to it, this condition will be true and then the bitmap will be updated
ki
Cc: Greg KH
Cc: Paolo Bonzini
Signed-off-by: Ashok Raj
Signed-off-by: Peter Zijlstra (Intel)
Link: http://lkml.kernel.org/r/1515720739-43819-6-git-send-email-ashok@intel.com
Signed-off-by: David Woodhouse
Signed-off-by: KarimAllah Ahmed
---
v6:
- introduce pred_cmd_used
v5:
- Use MSR_T
On 02/01/2018 03:19 PM, Konrad Rzeszutek Wilk wrote:
.snip..
+/* Is SPEC_CTRL intercepted for the currently running vCPU? */
+static bool spec_ctrl_intercepted(struct kvm_vcpu *vcpu)
+{
+ unsigned long *msr_bitmap;
+ int f = sizeof(unsigned long);
+
+ if (!cpu_has_vmx_msr_bitma
On 02/01/2018 02:25 PM, David Woodhouse wrote:
On Wed, 2018-01-31 at 23:26 -0500, Konrad Rzeszutek Wilk wrote:
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 6a9f4ec..bfc80ff 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -594,6 +594,14 @@ struct vcpu_vmx {
#endif
On 02/01/2018 06:37 PM, KarimAllah Ahmed wrote:
On 02/01/2018 02:25 PM, David Woodhouse wrote:
On Wed, 2018-01-31 at 23:26 -0500, Konrad Rzeszutek Wilk wrote:
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 6a9f4ec..bfc80ff 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm
David Woodhouse
Cc: Greg KH
Cc: Andy Lutomirski
Cc: Ashok Raj
Signed-off-by: KarimAllah Ahmed
Signed-off-by: David Woodhouse
---
v6:
- got rid of save_spec_ctrl_on_exit
- introduce msr_write_intercepted
v5:
- Also check for X86_FEATURE_SPEC_CTRL for the msr reads/writes
v4:
- Add IB
: KarimAllah Ahmed
Signed-off-by: David Woodhouse
---
arch/x86/kvm/cpuid.c | 2 +-
arch/x86/kvm/vmx.c | 15 +++
arch/x86/kvm/x86.c | 1 +
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 033004d..1909635 100644
--- a
ttp://lkml.kernel.org/r/1515720739-43819-6-git-send-email-ashok@intel.com
Signed-off-by: David Woodhouse
Signed-off-by: KarimAllah Ahmed
---
v6:
- introduce msr_write_intercepted_l01
v5:
- Use MSR_TYPE_W instead of MSR_TYPE_R for the MSR.
- Always merge the bitmaps unconditionally.
- Add PR
).
- Handle nested guests properly.
- expose F(IBRS) in kvm_cpuid_8000_0008_ebx_x86_features
Ashok Raj (1):
KVM: x86: Add IBPB support
KarimAllah Ahmed (4):
KVM: x86: Update the reverse_cpuid list to include CPUID_7_EDX
KVM: VMX: Emulate MSR_IA32_ARCH_CAPABILITIES
KVM: VMX: Allow direct access to
Hansen
Cc: Andi Kleen
Cc: Andrea Arcangeli
Cc: Linus Torvalds
Cc: Tim Chen
Cc: Thomas Gleixner
Cc: Dan Williams
Cc: Jun Nakajima
Cc: Paolo Bonzini
Cc: David Woodhouse
Cc: Greg KH
Cc: Andy Lutomirski
Cc: Ashok Raj
Signed-off-by: KarimAllah Ahmed
Signed-off-by: David Woodhouse
---
v5
: KarimAllah Ahmed
Signed-off-by: David Woodhouse
---
arch/x86/kvm/cpuid.c | 8 +++-
arch/x86/kvm/cpuid.h | 1 +
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 0099e10..c0eb337 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm
Ahmed
---
arch/x86/kvm/x86.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index abd1723..6f452bc 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -7664,7 +7664,7 @@ int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct
kvm_sregs
Please ignore. I just noticed that a similar patch is already in Radim's
tree and queued for linus.
On 01/20/2018 07:08 PM, KarimAllah Ahmed wrote:
Use the mask (X86_CR4_PAE) instead of the bit itself (X86_CR4_PAE_BIT) while
validating sregs.
Cc: Paolo Bonzini
Cc: Radim Krčmář
Cc: T
x27;d out]
Signed-off-by: Thomas Gleixner
Signed-off-by: KarimAllah Ahmed
Signed-off-by: David Woodhouse
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/include/asm/nospec-branch.h | 16
arch/x86/kernel/cpu/bugs.c | 7 +++
3 files changed, 24 inser
Woodhouse (1):
x86/speculation: Add basic IBRS support infrastructure
KarimAllah Ahmed (1):
x86: Simplify spectre_v2 command line parsing
Thomas Gleixner (4):
x86/speculation: Add basic support for IBPB
x86/speculation: Use Indirect Branch Prediction Barrier in context
switch
x86
From: Thomas Gleixner
[peterz: comment]
Signed-off-by: Thomas Gleixner
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: David Woodhouse
---
arch/x86/mm/tlb.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index a156195.
ner
Signed-off-by: KarimAllah Ahmed
Cc: Andrea Arcangeli
Cc: Andi Kleen
Cc: Peter Zijlstra
Cc: Greg KH
Cc: Dave Hansen
Cc: Andy Lutomirski
Cc: Paolo Bonzini
Cc: Dan Williams
Cc: Arjan Van De Ven
Cc: Linus Torvalds
Cc: David Woodhouse
Cc: Ashok Raj
Li
Signed-off-by: KarimAllah Ahmed
---
arch/x86/kernel/cpu/bugs.c | 106 +
1 file changed, 58 insertions(+), 48 deletions(-)
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 1d5e12f..349c7f4 100644
--- a/arch/x86/kernel/cpu
ff-by: KarimAllah Ahmed
---
Documentation/admin-guide/kernel-parameters.txt | 1 +
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/include/asm/nospec-branch.h| 2 -
arch/x86/kernel/cpu/bugs.c | 108 +++-
4 files changed, 68 inser
From: Tim Chen
Flush indirect branches when switching into a process that marked
itself non dumpable. This protects high value processes like gpg
better, without having too high performance overhead.
Signed-off-by: Andi Kleen
Signed-off-by: David Woodhouse
Signed-off-by: KarimAllah Ahmed
-off-by: Thomas Gleixner
Signed-off-by: KarimAllah Ahmed
Cc: Andi Kleen
Cc: Peter Zijlstra
Cc: Greg KH
Cc: Dave Hansen
Cc: Andy Lutomirski
Cc: Paolo Bonzini
Cc: Dan Williams
Cc: Arjan Van De Ven
Cc: Linus Torvalds
Cc: David Woodhouse
Cc: Ashok R
From: Thomas Gleixner
Indirect Branch Speculation (IBS) is controlled per physical core. If one
thread disables it then it's disabled for the core. If a thread enters idle
it makes sense to reenable IBS so the sibling thread can run with full
speculation enabled in user space.
This makes only se
Signed-off-by: Ashok Raj
Signed-off-by: Peter Zijlstra (Intel)
Link:
http://lkml.kernel.org/r/1515720739-43819-6-git-send-email-ashok@intel.com
Signed-off-by: David Woodhouse
Signed-off-by: KarimAllah Ahmed
---
arch/x86/kvm/svm.c | 14 ++
arch/x86/kvm/vmx.c | 4
2 files
it IBRS, put a reference
to the spec, and have a clear "you must be →this← tall to ride."
[karahmed: switch to using ALTERNATIVES instead of static_cpu_has]
[dwmw2: wrmsr args inside the ALTERNATIVE again, bikeshed naming]
Signed-off-by: Thomas Gleixner
Signed-off-by: KarimAllah Ah
On 01/21/2018 02:50 PM, Konrad Rzeszutek Wilk wrote:
On Sat, Jan 20, 2018 at 08:23:01PM +0100, KarimAllah Ahmed wrote:
From: Tim Chen
Stop Indirect Branch Speculation on every user space to kernel space
transition and reenable it when returning to user space./
How about interrupts?
That is
?),
switch to using ALTERNATIVES instead of static_cpu_has]
[dwmw2:set up ax/cx/dx in the asm too so it gets NOP'd out]
Signed-off-by: Thomas Gleixner
Signed-off-by: KarimAllah Ahmed
Signed-off-by: David Woodhouse
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/include/asm/n
On Thu, 04 Jan 2018 13:37:33 -0500 (EST)
David Miller wrote:
> From: Ahmed Abdelsalam
> Date: Sat, 30 Dec 2017 00:08:32 +0100
>
> > Some functions of seg6local are very useful to process SRv6
> > encapsulated packets
> >
> > This patch exports some functions
On Sun, 7 Jan 2018 00:40:03 +0100
Pablo Neira Ayuso wrote:
> Hi Ahmed,
>
> On Fri, Dec 29, 2017 at 12:07:52PM +0100, Ahmed Abdelsalam wrote:
> > It allows matching packets based on Segment Routing Header
> > (SRH) information.
> > The implementation considers
Left
(4) Last Entry
(5) Tag value of SRH
Signed-off-by: Ahmed Abdelsalam
---
include/uapi/linux/netfilter_ipv6/ip6t_srh.h | 57 ++
net/ipv6/netfilter/Kconfig | 9 ++
net/ipv6/netfilter/Makefile | 1 +
net/ipv6/netfilter/ip6t_srh.c| 161
Cc: Greg KH
Cc: Andy Lutomirski
Signed-off-by: KarimAllah Ahmed
Signed-off-by: Ashok Raj
---
arch/x86/kvm/cpuid.c | 4 +++-
arch/x86/kvm/cpuid.h | 1 +
arch/x86/kvm/vmx.c | 63
3 files changed, 67 insertions(+), 1 deletion(-)
diff
Cc: Greg KH
Cc: Andy Lutomirski
Cc: Ashok Raj
Signed-off-by: KarimAllah Ahmed
---
v2:
- remove 'host_spec_ctrl' in favor of only a comment (dwmw@).
- special case writing '0' in SPEC_CTRL to avoid confusing live-migration
when the instance never used the MSR
Cc: Paolo Bonzini
Cc: Radim Krčmář
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: H. Peter Anvin
Cc: x...@kernel.org
Cc: k...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: KarimAllah Ahmed
---
arch/x86/kvm/cpuid.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kvm
: Dan Williams
Cc: Jun Nakajima
Cc: Andy Lutomirski
Cc: Greg KH
Cc: Paolo Bonzini
Cc: Ashok Raj
Signed-off-by: KarimAllah Ahmed
---
arch/x86/kvm/cpuid.c | 4 +++-
arch/x86/kvm/vmx.c | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm
and IBRS_ALL.
Ashok Raj (1):
x86/kvm: Add IBPB support
KarimAllah Ahmed (3):
x86: kvm: Update the reverse_cpuid list to include CPUID_7_EDX
x86: vmx: Allow direct access to MSR_IA32_SPEC_CTRL
x86: vmx: Allow direct access to MSR_IA32_ARCH_CAPABILITIES
arch/x86/kvm/cpuid.c | 6 -
arch
Raj
Signed-off-by: Peter Zijlstra (Intel)
Link:
http://lkml.kernel.org/r/1515720739-43819-6-git-send-email-ashok@intel.com
Signed-off-by: David Woodhouse
Signed-off-by: KarimAllah Ahmed
---
arch/x86/kvm/svm.c | 14 ++
arch/x86/kvm/vmx.c | 4
2 files changed, 18
On 01/28/2018 09:21 PM, Konrad Rzeszutek Wilk wrote:
On January 28, 2018 2:29:10 PM EST, KarimAllah Ahmed wrote:
Add direct access to MSR_IA32_SPEC_CTRL for guests. This is needed for
guests
that will only mitigate Spectre V2 through IBRS+IBPB and will not be
using a
retpoline+IBPB based
On 01/29/2018 09:46 AM, David Woodhouse wrote:
On Sun, 2018-01-28 at 16:39 -0800, Liran Alon wrote:
Windows use IBRS and Microsoft don't have any plans to switch to retpoline.
Running a Windows guest should be a pretty common use-case no?
In addition, your handle of the first WRMSR intercept c
Attn
I was able to trace a huge sum of money in my department that bellongs
to our deceased customer according to my findings.I want to present
you as the beneficiary of this huge sum of money.I will give you the
full explanation as soon as you respond to this email.
Ahmed Zama
On 01/29/2018 11:44 AM, Paolo Bonzini wrote:
On 29/01/2018 01:58, KarimAllah Ahmed wrote:
Add direct access to MSR_IA32_SPEC_CTRL for guests. This is needed for
guests that will only mitigate Spectre V2 through IBRS+IBPB and will not
be using a retpoline+IBPB based approach.
To avoid the
On 01/29/2018 07:55 PM, Jim Mattson wrote:
Why should this MSR be pass-through? I doubt that it would be accessed
frequently.
True. Will update it to be emulated and allow user-space to set the
value exposed.
On Sun, Jan 28, 2018 at 4:58 PM, KarimAllah Ahmed wrote:
Add direct access to
wrote:
On Sun, Jan 28, 2018 at 11:29 AM, KarimAllah Ahmed wrote:
Add direct access to MSR_IA32_SPEC_CTRL for guests. This is needed for guests
that will only mitigate Spectre V2 through IBRS+IBPB and will not be using a
retpoline+IBPB based approach.
To avoid the overhead of atomically saving an
[dwmw2: Stop using KF() for bits in it, too]
Cc: Paolo Bonzini
Cc: Radim Krčmář
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: H. Peter Anvin
Cc: x...@kernel.org
Cc: k...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: KarimAllah Ahmed
Signed-off-by: David Woodhouse
---
arch/x86
-off-by: David Woodhouse
Signed-off-by: KarimAllah Ahmed
---
arch/x86/kvm/cpuid.c | 11 ++-
arch/x86/kvm/svm.c | 14 ++
arch/x86/kvm/vmx.c | 12
3 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index
unconditional]
Cc: Asit Mallick
Cc: Dave Hansen
Cc: Arjan Van De Ven
Cc: Tim Chen
Cc: Linus Torvalds
Cc: Andrea Arcangeli
Cc: Andi Kleen
Cc: Thomas Gleixner
Cc: Dan Williams
Cc: Jun Nakajima
Cc: Andy Lutomirski
Cc: Greg KH
Cc: Paolo Bonzini
Cc: Ashok Raj
Signed-off-by: KarimAllah Ahmed
David Woodhouse
Cc: Greg KH
Cc: Andy Lutomirski
Cc: Ashok Raj
Signed-off-by: KarimAllah Ahmed
Signed-off-by: David Woodhouse
---
v2:
- remove 'host_spec_ctrl' in favor of only a comment (dwmw@).
- special case writing '0' in SPEC_CTRL to avoid confusing live-migration
whe
and IBRS_ALL.
Ashok Raj (1):
KVM: x86: Add IBPB support
KarimAllah Ahmed (3):
KVM: x86: Update the reverse_cpuid list to include CPUID_7_EDX
KVM: VMX: Emulate MSR_IA32_ARCH_CAPABILITIES
KVM: VMX: Allow direct access to MSR_IA32_SPEC_CTRL
arch/x86/kvm/cpuid.c | 22 ++
arch/x86
On 01/30/2018 01:22 AM, Raj, Ashok wrote:
On Tue, Jan 30, 2018 at 01:10:27AM +0100, KarimAllah Ahmed wrote:
Future intel processors will use MSR_IA32_ARCH_CAPABILITIES MSR to indicate
RDCL_NO (bit 0) and IBRS_ALL (bit 1). This is a read-only MSR. By default
the contents will come directly from
acking the memory
region. So also enable it for memory regions that do not have a "struct page".
Cc: Paolo Bonzini
Cc: Radim Krčmář
Cc: k...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: KarimAllah Ahmed
---
virt/kvm/kvm_main.c | 2 ++
1 file changed, 2 insertions(+)
d
... to avoid reading them from the config space of all the PCI VFs. This is
specially a useful optimization when bringing up thousands of VFs.
Cc: Bjorn Helgaas
Cc: linux-...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: KarimAllah Ahmed
---
drivers/pci/iov.c | 20
acking the memory
region. So also enable it for memory regions that do not have a "struct page".
Cc: Paolo Bonzini
Cc: Radim Krčmář
Cc: k...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: KarimAllah Ahmed
---
v2:
- Move setting writable to hva_to_pfn_remapped
- Extend
... since INTx is not supported by-spec for virtual functions.
Cc: Bjorn Helgaas
Cc: linux-...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: KarimAllah Ahmed
Signed-off-by: Jan H. Schönherr
---
drivers/pci/probe.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a
On 01/17/2018 07:49 PM, Alex Williamson wrote:
On Wed, 17 Jan 2018 19:30:29 +0100
KarimAllah Ahmed wrote:
... since INTx is not supported by-spec for virtual functions.
But the spec also states that VFs must implement the interrupt pin
register as read-only zero, so either this is
()
(3) seg6_lookup_nexthop
Signed-off-by: Ahmed Abdelsalam
---
include/net/seg6.h| 5 +
net/ipv6/seg6_local.c | 37 -
2 files changed, 25 insertions(+), 17 deletions(-)
diff --git a/include/net/seg6.h b/include/net/seg6.h
index 099bad5..b637778 100644
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