dts/rk3288-evb-rk808.dts
> index 36db177..ff522f8 100644
> --- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
> +++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
> @@ -18,6 +18,7 @@
> };
>
> &i2c0 {
> + clock-frequency = <40>;
> status = "okay";
> It's convenient (and less confusing to people reading logs) if the
> eMMC port on rk3288 is consistenly marked with mmc0 and the sdmmc port
> on rk3288 is consistently marked with mmc1. Add the appropriate
> aliases.
>
> These aliases only actually do something if a patch like
> (https://patchw
, dw_mci_switch_voltage will not be
called,
That can't be right. mmc_power_up() should trigger
dw_mci_switch_voltage() to be invoked.
Hmmm, I think you're right. Addy: can you double check if it's only
the 2nd card for you? I was thinking that if a regulator is currently
3.3V and you request
Hi, Jaehoon
On 2014/11/20 18:01, Jaehoon Chung wrote:
Hi, Addy.
On 11/20/2014 06:33 PM, addy ke wrote:
Hi, Jaehoon
On 2014/11/19 13:56, addy ke wrote:
Hi Jaehoon
On 2014/11/19 09:22, Jaehoon Chung Wrote:
Hi, Addy.
On 11/18/2014 09:32 AM, Addy wrote:
On 2014年11月14日 21:18, Jaehoon Chung
On 2014年11月14日 21:18, Jaehoon Chung wrote:
Hi, Addy.
Did you use the DW_MCI_QUIRK_IDMAC_DTO?
I'm not sure, but i wonder if you get what result when you use above quirk.
DW_MCI_QUIRK_IDMAC_DTO is only for version2.0 or below.
/*
* DTO fix - version 2.10a and below, and
On 2015.02.09 12:51, Ulf Hansson wrote:
On 5 February 2015 at 12:13, Addy Ke wrote:
Because of some uncertain factors, such as worse card or worse hardware,
DAT[3:0](the data lines) may be pulled down by card, and mmc controller
will be in busy state. This should not happend when mmc
On 2015/02/10 23:22, Alim Akhtar wrote:
Hi Addy,
On Mon, Feb 9, 2015 at 12:55 PM, Addy Ke wrote:
Because of some uncertain factors, such as worse card or worse hardware,
DAT[3:0](the data lines) may be pulled down by card, and mmc controller
will be in busy state. This should not happend
On 2015/02月10日 17:34, Olof Johansson wrote:
Hi Addy,
On Mon, Jan 26, 2015 at 4:04 AM, Addy Ke wrote:
The STOP command can terminate a data transfer between a memory card and
mmc controller.
As show in Synopsys DesignWare Cores Mobile Stroage Host Databook:
Data timeout and Data end-bit
On 2015/02/09 18:01, Jaehoon Chung wrote:
Hi, Addy.
On 02/09/2015 04:25 PM, Addy Ke wrote:
Because of some uncertain factors, such as worse card or worse hardware,
DAT[3:0](the data lines) may be pulled down by card, and mmc controller
will be in busy state. This should not happend when mmc
. see:
https://chromium-review.googlesource.com/#/c/232774/
Signed-off-by: Addy Ke
---
Changes in v2:
- merged the patch that Doug submitted to chromium project
Changes in v3:
- merged the patch that Doug submitted to chromium to projectchange bindins
see: https://chromium-review.googlesource.com
-review.googlesource.com/#/c/232774/
Signed-off-by: Addy Ke
---
Changes in v2:
- merged the patch that Doug submitted to chromium project
Changes in v3:
- merged the patch that Doug submitted to chromium to projectchange bindins
see: https://chromium-review.googlesource.com/#/c/232774/
Changes in
.
We don't know why we have this problem, but we need it to fix this problem now.
And I will post a follow up change when we find the root cause.
Signed-off-by: Addy Ke
---
Changes in v2:
- fix some typo.
- remove extra timeout value (250ms).
- remove dw_mci_dto_start_monitor func.
- use "
for signals from the device tree.
This allows us to more accurately calculate timings. see:
https://chromium-review.googlesource.com/#/c/232774/
Signed-off-by: Addy Ke
---
Changes in v2:
- merged the patch that Doug submitted to chromium
Changes in v3:
- merged the patch that Doug submitted to
On 2014/12/8 10:59, Addy Ke wrote:
> high_ns calculated from the low division of CLKDIV register is the sum
> of actual measured high_ns and rise_ns. The rise time which related to
> external pull-up resistor can be up to the maximum rise time in I2C spec.
>
> In my test, if e
mmit dfac17:
idx = active = thrd->req_runnig = 0 -->
descdone = thrd->req[0] = NULL -->
list_add_tail(&descdone->rqd, &pl330->req_done); -->
got NULL pointer!!!
Signed-off-by: Addy Ke
---
drivers/dma/pl330.c | 6 ++
1 file changed, 6 insertions(+)
.
We don't know why we have this problem, but we need it to fix this problem now.
And I will post a follow up change when we find the root cause.
Signed-off-by: Addy Ke
---
Changes in v2:
- fix some typo.
- remove extra timeout value (250ms).
- remove dw_mci_dto_start_monitor func.
- use "
Addy Ke (2):
mmc: core: use card pointer as the first parameter of execute_tuning()
mmc: dw_mmc: wait until card ready if tuning fails
drivers/mmc/core/core.c | 2 +-
drivers/mmc/core/mmc_ops.h| 1 -
drivers/mmc/host/dw_mmc.c | 51
We need to take the card pointer in execute_tuning() for mmc_send_status(),
but mmc->card is NULL in tuning state. So we need change the first parameter
of execute_tuning() to card pointer(struct mmc_card * card).
Signed-off-by: Addy Ke
---
drivers/mmc/core/core.c | 2 +-
drivers/
This patch based on Alex's patch:
https://patchwork.kernel.org/patch/5516411/
Signed-off-by: Addy Ke
---
drivers/mmc/core/mmc_ops.h | 1 -
drivers/mmc/host/dw_mmc.c | 48 --
include/linux/mmc/card.h | 2 ++
3 files changed, 44 insertions(
a
data transfer again if we got DRTO and EBE interrupt.
After this patch, all mmc_test cases can pass on RK3288-Pink2 board.
Signed-off-by: Addy Ke
---
drivers/mmc/host/dw_mmc.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc
This patch focuses on clock setting for RK3288 mmc controller.
In RK3288 mmc controller, CLKDIV register can only be set 0 or 1,
and if DDR 8bit mode, CLKDIV register must be set 1.
Reported-by Doug Anderson
Suggested-by: Jaehoon Chung
Suggested-by: Doug Anderson
Signed-off-by: Addy Ke
Add public list
On 2014/9/17 23:17, Doug Anderson wrote:
> Addy,
>
> On Tue, Sep 16, 2014 at 6:30 PM, addy...@rock-chips.com
> wrote:
>> hi, all
>
> Any reason why you didn't add some public lists? It seems like this
> is a perfect discussion for linux-i2
estion about division formula.
Signed-off-by: Addy Ke
---
drivers/i2c/busses/i2c-rk3x.c | 79 +++
1 file changed, 72 insertions(+), 7 deletions(-)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index 93cfc83..49d67b7 100644
--- a/d
On 2014/9/24 12:10, Doug Anderson wrote:
> Addy,
>
> On Tue, Sep 23, 2014 at 6:55 PM, Addy Ke wrote:
>> As show in I2C specification:
>> - Standard-mode:
>> the minimum HIGH period of the scl clock is 4.0us
>> the minimum LOW period of the scl clock
Hi, Doug
On 2014/9/25 1:13, Doug Anderson wrote:
> Addy,
>
> On Wed, Sep 24, 2014 at 1:23 AM, addy ke wrote:
>>
>>
>> On 2014/9/24 12:10, Doug Anderson wrote:
>>> Addy,
>>>
>>> On Tue, Sep 23, 2014 at 6:55 PM, Addy Ke wrote:
>>>&
In my test on RK3288-pinky board, if spi is enabled, it will begin to
read data from slave regardless of whether the DMA is ready. So we
need prepare DMA before spi is enable.
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 15 +++
1 file changed, 7 insertions(+), 8
Hi, Doug
On 2014/9/26 5:52, Doug Anderson wrote:
> Addy,
>
> On Wed, Sep 24, 2014 at 9:36 PM, Doug Anderson wrote:
>> Addy,
>>
>> On Wed, Sep 24, 2014 at 6:56 PM, addy ke wrote:
>>> In my measurement,all paramter but "Data hold time" are match the
On 2014/9/26 10:08, Doug Anderson wrote:
> Addy,
>
> On Thu, Sep 25, 2014 at 6:40 PM, addy ke wrote:
>> Hi, Doug
>>
>> On 2014/9/26 5:52, Doug Anderson wrote:
>>> Addy,
>>>
>>> On Wed, Sep 24, 2014 at 9:36 PM, Doug Anderson
>>&
From: Addy
As show in I2C specification:
- Standard-mode: the minimum HIGH period of the scl clock is 4.0us
the minimum LOW period of the scl clock is 4.7us
- Fast-mode: the minimum HIGH period of the scl clock is 0.6us
the minimum LOW period of the scl clock is
Hi Doug
On 2014/9/29 12:39, Doug Anderson wrote:
> Addy,
>
> On Sat, Sep 27, 2014 at 12:11 AM, Addy Ke wrote:
>> From: Addy
>>
>> As show in I2C specification:
>> - Standard-mode: the minimum HIGH period of the scl clock is 4.0us
>> the
Signed-off-by: addy ke
---
changes since v1:
- fix binding document according to comments from Mark Rutland
- fix address according to comments from Mark Brown
- combine all properties into "Required Properties" suggested by Heiko Stübner
- remove "Board Specific Portion"
>tmode << CR0_XFM_OFFSET);
cr0 |= (rs->type << CR0_FRF_OFFSET);
For more information, see RK3288 chip manual.
- Wait for idle: Must ensure that the FIFO data has been sent out
before the next transfer.
Signed-off-by: addy ke
---
changes since v1:
- more specific about t
This patch focuses on clock setting for RK3288 mmc controller.
In RK3288 mmc controller, CLKDIV register can only be set 0 or 1,
and if DDR 8bit mode, CLKDIV register must be set 1.
Signed-off-by: Addy Ke
---
changes since v1:
- dw_mci_rk3288_setup_clock: do not call clk_get_rate(), just use
From: Addy Ke
These patches based on:
- git: kernel/git/broonie/spi.git
- branch: topic/rockchip
- commit: c15369087ae5c7db7f3e3604822eac6ab87429bd
Addy Ke (4):
spi/rockchip: cleanup some coding issues and uncessary output
spi/rockchip: call wait_for_idle() for the transfer to complete
From: Addy Ke
Suggested-by: Mark Brown
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 24 +++-
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 8c24708..09c690c 100644
--- a/drivers/spi
From: Addy Ke
Suggested-by: Mark Brown
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 41 +++--
1 file changed, 23 insertions(+), 18 deletions(-)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 72fb287..8c24708 100644
From: Addy Ke
Suggested-by: Jonas Gorski
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 09c690c..a8866c9 100644
--- a/drivers/spi/spi-rockchip.c
+++ b
From: Addy Ke
Suggested-by: Mark Brown
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index a8866c9..cb8fd6f 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi
This patch focuses on clock setting for RK3288 mmc controller.
In RK3288 mmc controller, CLKDIV register can only be set 0 or 1,
and if DDR 8bit mode, CLKDIV register must be set 1.
Signed-off-by: addy ke
---
.../devicetree/bindings/mmc/rockchip-dw-mshc.txt | 4 +-
drivers/mmc/host/dw_mmc
> On Tue, Jul 01, 2014 at 09:03:59AM +0800, addy ke wrote:
>> In order to facilitate understanding, rockchip SPI controller IP design
>> looks similar in its registers to designware. But IC implementation
>> is different from designware, So we need a dedicated driver for Ro
> Hi, Addy,
>
> On 07/05/2014 09:59 PM, addy ke wrote:
>> This patch focuses on clock setting for RK3288 mmc controller.
>>
>> In RK3288 mmc controller, CLKDIV register can only be set 0 or 1,
>> and if DDR 8bit mode, CLKDIV register must be se
:0]bit[3:0]
For more information, see RK3288 chip manual.
- Wait for idle: Must ensure that the FIFO data has been sent out
before the next transfer.
Signed-off-by: Addy Ke
---
changes since v1:
- more specific about the differences according to comments from Mark Brown
- not to cast
Signed-off-by: addy ke
---
.../devicetree/bindings/spi/spi-rockchip.txt | 51 ++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-rockchip.txt
diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt
b
Patch 1 add rockchip spi documentation
Patch 2 add driver for Rockchip RK3XXX SoCs integrated SPI.
Tested on rk3288 sdk board with polling mode and DMA mode.
addy ke (2):
documentation: add rockchip spi documentation
spi: add driver for Rockchip RK3xxx SoCs integrated SPI
.../devicetree
SoCs integrated SPI.
Signed-off-by: addy ke
---
drivers/spi/Kconfig| 11 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-rockchip.c | 894 +
3 files changed, 906 insertions(+)
create mode 100644 drivers/spi/spi-rockchip.c
diff --git a
In rk3x SOC, the I2C controller can receive/transmit up to 32 bytes data
in one transaction, so the size of data to be write/read to/from
TXDATAx/RXDATAx must be less than or equal 32 bytes at a time.
Test on pinky board, elan receive 158 bytes data.
Signed-off-by: Addy Ke
---
drivers/i2c
In rk3x SOC, the I2C controller can receive/transmit up to 32 bytes data
in one chunk, so the size of data to be write/read to/from TXDATAx/RXDATAx
must be less than or equal 32 bytes at a time.
Tested on rk3288-pinky board, elan receive 158 bytes data.
Acked-by: Max Schwarz
Signed-off-by: Addy
In rk3x SOC, the I2C controller can receive/transmit up to 32 bytes data
in one chunk, so the size of data to be write/read to/from TXDATAx/RXDATAx
must be less than or equal 32 bytes at a time.
Tested on rk3288-pinky board, elan receive 158 bytes data.
Acked-by: Max Schwarz
Signed-off-by: Addy
-by: Addy Ke
Acked-by: Max Schwarz
---
Changes in v2:
- Use cleaner syntax as suggested by Sergei.
- Update commit message as suggested by Wolfram.
Changes in v3:
- fix typo: maste --> master and double spaces after 'len'
drivers/i2c/busses/i2c-rk3x.c | 4
Changes in v4:
- re
> Addy,
>
> On Fri, Aug 22, 2014 at 11:00 AM, Addy Ke wrote:
>> In rk3x SOC, the I2C controller can receive/transmit up to 32 bytes data
>> in one chunk, so the size of data to be write/read to/from TXDATAx/RXDATAx
>> must be less than or equal 32 bytes at a time.
&
)
It will be updated to the latest version of chip manual.
Signed-off-by: Addy Ke
---
changes since v1:
- make it more cleaner, suggested by Doug Anderson
drivers/i2c/busses/i2c-rk3x.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b
This patch requires that <https://patchwork.kernel.org/patch/4701721/>
land in order to compile.
Signed-off-by: Addy Ke
---
Changes in v2:
- repost patch to match what's in Heiko's "wip/v3.18-next/dts" tree
for the other dwmmc controllers
- add "cd" and &q
To support HS200 and UHS-1, we need add a big hunk of code,
as shown in the following patches. So a separate file for
rockchip SOCs is suitable.
Signed-off-by: Addy Ke
---
Changes in v2:
- Kconfig: depend on ARCH_ROCKCHIP, suggested by Bartlomiej Zolnierkiewicz
- Kconfig: depend on OF, suggested
This patch requires that <https://patchwork.kernel.org/patch/4701721/>
land in order to compile.
Signed-off-by: Addy Ke
---
Changes in v2:
- repost patch to match what's in Heiko's "wip/v3.18-next/dts" tree
for the other dwmmc controllers
- add "cd" and &q
This patch requires that <https://patchwork.kernel.org/patch/4701721/>
land in order to compile.
Reviewed-by: Doug Anderson
Signed-off-by: Addy Ke
---
Changes in v2:
- repost patch to match what's in Heiko's "wip/v3.18-next/dts" tree
for the other dwmmc controllers
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index cb8fd6f..4ef3fd3 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -679,7 +679,7
)
It will be updated to the latest version of chip manual.
Signed-off-by: Addy Ke
---
drivers/i2c/busses/i2c-rk3x.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index e637c32..76b6604 100644
--- a/drivers/i2c
> Addy,
>
> On Thu, Sep 4, 2014 at 7:32 PM, Addy Ke wrote:
>> I2C_CLKDIV register descripted in the previous version of
>> RK3x chip manual is incorrect. Plus 1 is required.
>>
>> The correct formula:
>> - T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
>&g
If slave holds scl, I2C_IPD[7] will be set 1 by controller
for debugging. Driver must ignore it.
[5.752391] rk3x-i2c ff16.i2c: unexpected irq in WRITE: 0x80
[5.939027] rk3x-i2c ff16.i2c: timeout, ipd: 0x80, state: 4
Signed-off-by: Addy Ke
---
drivers/i2c/busses/i2c-rk3x.c | 2
erson
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 72fb287..1e3bcfa 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -511,8 +
> Addy,
>
> On Wed, Aug 13, 2014 at 6:57 PM, Addy wrote:
>
>> I think maybe it is suitable as follows:
>> mmc0 = &sdmmc
>> mmc1 = &sdio0
>> mmc2 = &sdio1
>> mmc3 = &emmc
>
> Right, except the only ones that have landed in Heiko
Signed-off-by: Addy Ke
---
arch/arm/boot/dts/rk3288.dtsi | 76 +++
1 file changed, 76 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 7a9173d..a440869 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm
To support HS200 and UHS-1, we need add a big hunk of code,
as shown in the following patches. So a separate file for
rockchip SOCs is suitable.
Signed-off-by: Addy Ke
---
drivers/mmc/host/Kconfig | 9 +++
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/dw_mmc-pltfm.c
actual measured high_ns is about 3900ns, which is less than 4000ns
(the minimum high_ns in I2C spec).
Signed-off-by: Addy Ke
---
drivers/i2c/busses/i2c-rk3x.c | 58 +++
1 file changed, 37 insertions(+), 21 deletions(-)
diff --git a/drivers/i2c/busses/i2c
This patch add a quirk: DW_MCI_QUIRK_SDIO_INT_24BIT.
The bit of sdio interrupt is 16 in designware implementation, but
is 24 in RK3288. To support RK3288 mmc controller, we need add
a quirk for it.
Signed-off-by: Addy Ke
---
drivers/mmc/host/dw_mmc.c | 32
Hi, Doug,
On 2014/10/30 12:49, Doug Anderson wrote:
> Addy,
>
> On Wed, Oct 29, 2014 at 9:41 PM, Doug Anderson wrote:
>> You can avoid a lot of "if" tests if you just add a new "sdio->id"
>
> Whoops, I mean "slot->sdio_id"
>
To us
The bit of sdio interrupt is 16 in designware implementation,
but it is 24 in RK3288. This patch add sdio_id0 for the number
of slot0 in the SDIO interrupt registers, which can be set in
platform DT table, such as:
- rockchip,sdio-interrupt-slot0 = <8>;
Signed-off-by: Addy Ke
---
drive
Hi, Jaehoon
On 2014/10/30 19:02, Jaehoon Chung wrote:
> Hi, Addy.
>
> This patch is conflicted..Could you rebase on latest Ulf's tree?
I have not found ulf's tree in git.kernel.org.
I can't 'git clone git://git.kernel.org/pub/scm/linux/kernel/git/ulf/xxx.git'.
S
On 2014/10/30 19:17, Jaehoon Chung wrote:
> On 10/30/2014 08:11 PM, Ulf Hansson wrote:
>> On 30 October 2014 11:50, Addy Ke wrote:
>>> The bit of sdio interrupt is 16 in designware implementation,
>>> but it is 24 in RK3288. This patch add sdio_id0 for the numb
The bit of sdio interrupt is 16 in designware implementation,
but it is 24 in RK3288. This patch add sdio_id0 for the number
of slot0 in the SDIO interrupt registers, which can be set in
platform DT table, such as:
- rockchip,sdio-interrupt-slot0 = <8>;
Signed-off-by: Addy Ke
---
Changes
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
Signed-off-by: Addy Ke
---
Changes in v2:
- remove Fast-mode plus and HS-mode
- use new formulas suggested by Doug
Changes in V3:
- use new formulas (sep 30) suggested by Doug
Changes in V4:
- fix some wrong style
- WARN_ONCE if min_low_div
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
Signed-off-by: Addy Ke
---
Changes in v2:
- remove Fast-mode plus and HS-mode
- use new formulas suggested by Doug
Changes in V3:
- use new formulas (sep 30) suggested by Doug
Changes in V4:
- fix some wrong style
- WARN_ONCE if min_low_div
Patch 1: fix bug that case spi can't go as fast as slave request
Patch 2: fix bug that cause spi transfer timed out in DMA duplex mode
Tested on rk3288-pinky-version2 board.
Addy Ke (2):
spi/rockchip: fix bug that case spi can't go as fast as slave request
spi/rockchip: fix bug
Because the minimum divisor in rk3x's spi controller is 2,
if spi_clk is less than 2 * sclk_out, we can't get the right divisor.
So we must set spi_clk again to match slave request.
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 12
1 file changed, 12 insertion
In rx mode, dma must be prepared before spi is enabled.
But in tx and tr mode, spi must be enabled first.
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 34 +++---
1 file changed, 23 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/spi-rockchip.c b
hi, Mark
On 2014/10/15 21:04, Mark Brown wrote:
> On Wed, Oct 15, 2014 at 07:25:49PM +0800, Addy Ke wrote:
>
>> +if (WARN_ON(rs->speed > MAX_SCLK_OUT))
>> +rs->speed = MAX_SCLK_OUT;
>> +
>> +/* the minimum divsor is 2 */
&
_current_transfer(rs->master);
+ }
spin_unlock_irqrestore(&rs->lock, flags);
}
Sorry for my mistake, I have not put these changes to this patch.
Do I need send patch v2 or a new patch to fix this issure?
On 2014/10/15 21:05, Mark Brown wrote:
> On Wed, Oct 15, 2014 at 07:26:18PM +0800, Addy Ke wrote:
&
measured i2c SCL waveforms in fast-mode by oscilloscope
on rk3288-pinky board. the LOW period of the scl clock is 1.3us.
It is so critical that we must adjust LOW division to increase
the LOW period of the scl clock.
Thanks Doug for the suggestion about division formulas.
Signed-off-by: Addy Ke
On 2014/10/31 18:43, Heiko Stübner wrote:
> Am Freitag, 31. Oktober 2014, 11:50:09 schrieb Addy Ke:
>> The bit of sdio interrupt is 16 in designware implementation,
>> but it is 24 in RK3288. This patch add sdio_id0 for the number
>> of slot0 in the SDIO interrupt registers
The bit of sdio interrupt is 16 in designware implementation,
but it is 24 on Rockchip SoCs.This patch add sdio_id0 for the
number of slot0 in the SDIO interrupt registers.
Signed-off-by: Addy Ke
---
Changes in v2:
- rebase on http://git.linaro.org/git/people/ulf.hansson/mmc.git, next branch
Hi, Jaehoo
On 2014/11/3 16:59, Jaehoon Chung wrote:
> Hi, Addy.
>
> On 11/03/2014 10:20 AM, Addy Ke wrote:
>> The bit of sdio interrupt is 16 in designware implementation,
>> but it is 24 on Rockchip SoCs.This patch add sdio_id0 for the
>> number of slot0 in t
The bit of sdio interrupt is 16 in designware implementation,
but it is 24 on Rockchip SoCs.This patch add sdio_id0 for the
number of slot0 in the SDIO interrupt registers.
Signed-off-by: Addy Ke
---
Changes in v2:
- rebase on http://git.linaro.org/git/people/ulf.hansson/mmc.git, next branch
Hi Jaehoon
On 2014/11/19 09:22, Jaehoon Chung Wrote:
> Hi, Addy.
>
> On 11/18/2014 09:32 AM, Addy wrote:
>>
>> On 2014年11月14日 21:18, Jaehoon Chung wrote:
>>> Hi, Addy.
>>>
>>> Did you use the DW_MCI_QUIRK_IDMAC_DTO?
>>> I'm not sure
Hi, Jaehoon
On 2014/11/19 13:56, addy ke wrote:
> Hi Jaehoon
>
> On 2014/11/19 09:22, Jaehoon Chung Wrote:
>> Hi, Addy.
>>
>> On 11/18/2014 09:32 AM, Addy wrote:
>>>
>>> On 2014年11月14日 21:18, Jaehoon Chung wrote:
>>>> Hi, Addy.
>>&g
On 2014/11/13 02:04, Doug Anderson wrote:
> Ulf,
>
> On Tue, Nov 11, 2014 at 12:52 AM, Ulf Hansson wrote:
>> On 11 November 2014 05:02, Addy Ke wrote:
>>> SD2.0 cards need vqmmc and vmmc to be the same.
>>
>> No, that's not correct.
>>
>
From: Addy
This patch add a new quirk to notify the driver to teminate
current transfer and report a data timeout to the core,
if data over interrupt does NOT come within the given time.
dw_mmc call mmc_request_done func to finish transfer depends on
data over interrupt. If data over interrupt
Hi,
On 2014/11/27 06:46, Doug Anderson wrote:
> Hi,
>
> On Tue, Nov 25, 2014 at 12:10 AM, Addy Ke wrote:
>> This patch add a new quirk to add a s/w timer to notify the driver
>> to terminate current transfer and report a data timeout to the core,
>> if DTO interru
)
Signed-off-by: Addy Ke
---
drivers/mmc/host/dw_mmc.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index b4c3044..a8b70b5 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1163,8
that host should get DRTO and DTO interrupt.
But we really don't get any data-related interrupt in RK3X SoCs.
And driver can't get data transfer state, it can do nothing but wait for.
Signed-off-by: Addy Ke
---
- fix some typo.
- remove extra timeout value (250ms).
- remove dw_mci_dt
for signals from the device tree.
This allows us to more accurately calculate timings. see:
https://chromium-review.googlesource.com/#/c/232774/
Signed-off-by: Addy Ke
---
Changes in v2:
- merged the patch that Doug submitted to chromium
Documentation/devicetree/bindings/i2c/i2c-rk3x.txt | 10
ollow up change when we find the root cause.
Signed-off-by: Addy Ke
---
Changes in v2:
- fix some typo.
- remove extra timeout value (250ms).
- remove dw_mci_dto_start_monitor func.
- use "broken-dto" for new quirk and change Subject for it.
Changes in v3:
- Remove dts for brok
team
was based on this freequency point.
Signed-off-by: Addy Ke
---
arch/arm/boot/dts/rk3288.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index acb6a2f..9c35a1d 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arc
On 2014/10/16 17:34, Mark Brown wrote:
> On Thu, Oct 16, 2014 at 05:16:02PM +0800, addy ke wrote:
>> On 2014/10/15 21:04, Mark Brown wrote:
>>> On Wed, Oct 15, 2014 at 07:25:49PM +0800, Addy Ke wrote:
>
>>>> + if (WARN_ON(rs->speed > MAX_SCLK_OUT))
&
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 153269b..87bc16f 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -418,8 +418,10
Tested-by: Doug Anderson
Signed-off-by: Addy Ke
---
Changes in v2:
- remove Fast-mode plus and HS-mode
- use new formulas suggested by Doug
Changes in V3:
- use new formulas (sep 30) suggested by Doug
Changes in V3:
- fix some wrong style
- WARN_ONCE if min_low_div > max_low_div
drivers/
Addy Ke (2):
mmc: dw_mmc: fix bug that cause 'Timeout sending command'
mmc: dw_mmc: Don't start command while data busy
drivers/mmc/host/dw_mmc.c | 35 +++
1 file changed, 35 insertions(+)
--
Changes in v2:
- add new patch to handle data
we will get 'Timeout sending command', and then system will
be blocked. To avoid this, we need reset mmc controller.
Signed-off-by: Addy Ke
---
drivers/mmc/host/dw_mmc.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc.c b/driver
We should wait for data busy here in non-volt-switch state.
This may happend when sdio sends CMD53.
Signed-off-by: Addy Ke
---
drivers/mmc/host/dw_mmc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index b0b57e3..b40080d 100644
On 2015/2/9 15:04, Jaehoon Chung wrote:
> On 02/09/2015 03:56 PM, Addy wrote:
>>
>>
>> On 2015.02.09 12:51, Ulf Hansson wrote:
>>> On 5 February 2015 at 12:13, Addy Ke wrote:
>>>> Because of some uncertain factors, such as worse card or worse hard
Signed-off-by: Addy Ke
---
Documentation/devicetree/bindings/mmc/mmc.txt | 11 +++
drivers/mmc/core/host.c | 2 ++
2 files changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt
b/Documentation/devicetree/bindings/mmc/mmc.txt
index
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