kernel.org/lkml/20190405035446.31886-1-georgi.dja...@linaro.org/
Bjorn Andersson (1):
interconnect: qcom: Add QCS404 interconnect provider driver
Georgi Djakov (4):
dt-bindings: interconnect: Add Qualcomm QCS404 DT bindings
soc: qcom: smd-rpm: Create RPM interconnect proxy child device
int
ed
by the RPM.
Signed-off-by: Georgi Djakov
---
v4:
- Return error if platform_device_register_data() fails
- Remove platform_set_drvdata() on the child device.
v3:
- New patch.
drivers/soc/qcom/smd-rpm.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/dr
Andersson
Signed-off-by: Georgi Djakov
---
v4:
- Select INTERCONNECT_QCOM_SMD_RPM from this driver.
- Move the DT header to the dt-bindings patch.
- Move this patch later in the series.
v3:
- Convert the #defines into enum. (Bjorn)
- Move the rpm-smd part into a separate interconnect proxy driver.
v2
On some Qualcomm SoCs, there is a remote processor, which controls some of
the Network-On-Chip interconnect resources. Other CPUs express their needs
by communicating with this processor. Add a driver to handle communication
with this remote processor.
Signed-off-by: Georgi Djakov
---
v4
The Qualcomm QCS404 platform has several buses that could be controlled
and tuned according to the bandwidth demand.
Reviewed-by: Bjorn Andersson
Signed-off-by: Georgi Djakov
---
v4:
- Add the DT header into this patch.
- Pick Bjorn's r-b.
v3:
- Add a reg property and move the interco
Add the DT nodes for the network-on-chip interconnect buses found
on qcs404-based platforms.
Reviewed-by: Bjorn Andersson
Signed-off-by: Georgi Djakov
---
v4:
- Insert the NoC DT nodes after rng@ to keep the nodes sorted by address.
- Pick Bjorn's r-b.
v3:
- Update according to th
On 5/8/19 23:42, Rob Clark wrote:
> From: Georgi Djakov
>
Let's put some text in the commit message:
The interconnect API provides an interface for consumer drivers to express
their bandwidth needs in the SoC. This data is aggregated and the on-chip
interconnect hardware is config
...@linaro.org/
Bjorn Andersson (1):
interconnect: qcom: Add QCS404 interconnect provider driver
Georgi Djakov (3):
dt-bindings: interconnect: Add Qualcomm QCS404 DT bindings
arm64: dts: qcs404: Add interconnect provider DT nodes
dt-bindings: interconnect: qcs404: Introduce qcom,qos DT property
The Qualcomm QCS404 platform has several buses that could be controlled
and tuned according to the bandwidth demand.
Signed-off-by: Georgi Djakov
---
v2:
- No changes.
.../bindings/interconnect/qcom,qcs404.txt | 45 +++
1 file changed, 45 insertions(+)
create mode 100644
ot;bypass" and "regulator". Depending on
the mode, there are a few additional knobs that could be configured.
Introduce the qcom,qos property, so that we describe this relation in DT and
allow the interconnect provider drivers can make use of it.
Signed-off-by: Georgi Djakov
---
v2:
- New
: Georgi Djakov
---
v2:
- Use the clk_bulk API. (Bjorn)
- Move the port IDs into the provider file. (Bjorn)
- Use ARRAY_SIZE in the macro to automagically count the num_links. (Bjorn)
- Improve code readability. (Bjorn)
drivers/interconnect/qcom/Kconfig | 8 +
drivers/interconnect
Add the DT nodes for the network-on-chip interconnect buses found
on qcs404-based platforms.
Signed-off-by: Georgi Djakov
---
v2:
- No changes.
arch/arm64/boot/dts/qcom/qcs404.dtsi | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404
Add nodes for the network-on-chip interconnect buses present on
MSM8916-based platforms.
Signed-off-by: Georgi Djakov
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 28 +++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64
bering
the bandwidth values and handle this in the framework instead.
With this patch the users can call icc_disable() and icc_enable() to lower
their bandwidth request to zero and then restore it back to it's previous
value.
Suggested-by: Evan Green
Suggested-by: Bjorn Andersson
Signed
On 5/4/20 11:57, Akash Asthana wrote:
> Hi Georgi,
>
> On 4/28/2020 2:46 PM, Georgi Djakov wrote:
>> There is a repeated pattern in multiple drivers where they want to switch
>> the bandwidth between zero and some other value. This is happening often
>> in the suspend/
.
opp-avg-kBps is an optional property that can be used in Bandwidth OPP
tables.
Signed-off-by: Saravana Kannan
Reviewed-by: Sibi Sankar
Reviewed-by: Rob Herring
Signed-off-by: Georgi Djakov
---
v8:
* Picked reviewed-by tags.
* Changes on wording.
Documentation/devicetree/bindings/opp/opp.txt
.com
[7] https://lore.kernel.org/r/20190726231558.175130-1-sarava...@google.com
[8] https://lore.kernel.org/r/20190807223111.230846-1-sarava...@google.com
[9] https://lore.kernel.org/r/20191207002424.201796-1-sarava...@google.com
Georgi Djakov (6):
interconnect: Add of_icc_get_by_index() he
: Georgi Djakov
---
v8:
* Keep the existing behavior: goto free_opp only if !is_genpd
* Picked reviewed-by tags.
drivers/opp/core.c | 15 +--
drivers/opp/of.c | 45 +++--
drivers/opp/opp.h | 1 +
3 files changed, 41 insertions(+), 20 deletions
Currently when we check for the available resources, we assume that there
is only one interconnect path, but in fact it could be more than one. Do
some validation to determine the number of paths and verify if each one
of them is available.
Signed-off-by: Georgi Djakov
---
v8:
* New patch
From: Sibi Sankar
Add interconnect-tags bindings to enable passing of optional
tag information to the interconnect framework.
Signed-off-by: Sibi Sankar
Signed-off-by: Georgi Djakov
---
v8:
* New patch, picked from here:
https://lore.kernel.org/r/20200504202243.5476-10-si...@codeaurora.org
In addition to clocks and regulators, some devices can scale the bandwidth
of their on-chip interconnect - for example between CPU and DDR memory. Add
support for that, so that platforms which support it can make use of it.
Reviewed-by: Matthias Kaehlcke
Signed-off-by: Georgi Djakov
---
v8
Sibi Sankar
Signed-off-by: Georgi Djakov
---
v8:
* Picked reviewed-by tags.
drivers/opp/of.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/opp/of.c b/drivers/opp/of.c
index d139ad8c8f4f..3a64f2aa0f86 100644
--- a/drivers/opp/of.c
+++ b/driver
If the OPP bandwidth values are populated, we want to switch also the
interconnect bandwidth in addition to frequency and voltage.
Reviewed-by: Matthias Kaehlcke
Reviewed-by: Sibi Sankar
Signed-off-by: Georgi Djakov
---
v8:
* Picked reviewed-by tags.
drivers/opp/core.c | 13 -
1
From: Sibi Sankar
Add support for setting tags on icc paths associated with
the opp_table.
Signed-off-by: Sibi Sankar
Signed-off-by: Georgi Djakov
---
v8:
* New patch, picked from here:
https://lore.kernel.org/r/20200504202243.5476-11-si...@codeaurora.org
drivers/opp/of.c | 24
The OPP bindings now support bandwidth values, so add support to parse it
from device tree and store it into the new dev_pm_opp_icc_bw struct, which
is part of the dev_pm_opp.
Signed-off-by: Georgi Djakov
---
v8:
* Drop bandwidth requests and free memory in _opp_table_kref_release.
* Take into
This is the same as the traditional of_icc_get() function, but the
difference is that it takes index as an argument, instead of name.
Reviewed-by: Matthias Kaehlcke
Reviewed-by: Sibi Sankar
Signed-off-by: Georgi Djakov
---
v8:
* Dropped unneeded initializations.
* Picked reviewed-by tags
leaning up
Then the USB devices are not functional anymore. Let's disable the PM of
the controller for now, as this will at least keep USB devices working
even after suspend and resume.
Signed-off-by: Georgi Djakov
---
drivers/pci/controller/dwc/pcie-qcom.c | 8
1 file change
Enable the driver for the real time clock found in the PMICs on various
Qualcomm platforms.
Signed-off-by: Georgi Djakov
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 883e8bace3ed
Hi Bjorn,
On 06/23/2017 08:45 PM, Bjorn Andersson wrote:
> On Fri 23 Jun 09:15 PDT 2017, Georgi Djakov wrote:
>
>> +static int msm8916_register_clk(struct device *dev, void __iomem *base)
>> +{
> [..]
>> +regmap = devm_regmap_init_mmio(dev, base, &a53cc_reg
On 06/27/2017 12:48 PM, Riku Voipio wrote:
> On 26 June 2017 at 22:40, Rob Herring wrote:
>> On Fri, Jun 23, 2017 at 07:15:31PM +0300, Georgi Djakov wrote:
>>> The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs,
>>> a primary (A53) CPU PLL and a second
Hi Stephen,
On 06/27/2017 01:47 AM, Stephen Boyd wrote:
> On 06/23, Georgi Djakov wrote:
>> diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
>> b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
>> index 9924c6d7f05d..da363c6580da 100644
>> --- a/drivers/mailbox/qcom-
Add driver for the Qualcomm interconnect controllers found in
msm8916 based platforms. This patch contains only a small part
of the topology to make reviewing easier.
Signed-off-by: Georgi Djakov
---
drivers/interconnect/Kconfig | 5 +
drivers/interconnect/Makefile
The interconnect API is not yet using DT bindings for expressing
the relations between the API consumers and providers. This is
posted a separate patch as it needs further discussions on how
to represent this with DT.
Signed-off-by: Georgi Djakov
---
.../bindings/interconnect/interconnect.txt
t ports as arguments).
* Removed public declarations of some structs.
* Now passing prev/next nodes to the vendor driver.
* Properly remove requests on _put().
* Added refcounting.
* Updated documentation.
* Changed struct interconnect_path to use array instead of linked list.
Georgi Djakov (3):
topology node according to the requested data flow path, physical links and
constraints. The topology could be complicated and multi-tiered and is SoC
specific.
Signed-off-by: Georgi Djakov
---
Documentation/interconnect/interconnect.rst | 71 ++
drivers/Kconfig | 2
just return this rate.
Reported-by: Archit Taneja
Fixes: 00f64b58874e ("clk: qcom: Add support for SMD-RPM Clocks")
Signed-off-by: Georgi Djakov
---
drivers/clk/qcom/clk-smd-rpm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk
On 07/14/2017 12:56 AM, Stephen Boyd wrote:
> On 07/13, Georgi Djakov wrote:
>> As there is no way to actually query the hardware for the current clock
>> rate, now racalc_rate() just returns the last rate that was previously
>> set. But if the rate was not set yet, we ret
Hi Vincent,
On 06/28/2017 08:45 PM, Vincent Guittot wrote:
> Hi Georgi,
>
> On 27 June 2017 at 19:49, Georgi Djakov wrote:
>
> [snip]
>
>> +
>> +static int interconnect_aggregate(struct interconnect_node *node,
>> +
Hi Rob,
On 06/30/2017 12:32 AM, Rob Herring wrote:
> On Tue, Jun 27, 2017 at 08:49:03PM +0300, Georgi Djakov wrote:
>> The interconnect API is not yet using DT bindings for expressing
>> the relations between the API consumers and providers. This is
>> posted a separate patc
need to remove recalc_rate ops and then the core framework will handle
this automagically. The round_rate() is unused, so remove it as well.
Reported-by: Archit Taneja
Fixes: 00f64b58874e ("clk: qcom: Add support for SMD-RPM Clocks")
Signed-off-by: Georgi Djakov
---
drivers/clk/qcom/clk
ing shared memory based communication
to request regulators are failing to boot and mount rootfs.
Fix this by explicitly enabling HWSPINLOCK in defconfig.
Signed-off-by: Georgi Djakov
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defcon
ng prev/next nodes to the vendor driver.
* Properly remove requests on _put().
* Added refcounting.
* Updated documentation.
* Changed struct interconnect_path to use array instead of linked list.
Georgi Djakov (2):
interconnect: Add generic on-chip interconnect API
interconnect: Add Qualco
Add driver for the Qualcomm interconnect buses found in msm8916 based
platforms. This patch contains only a partial topology to make reviewing
easier.
Signed-off-by: Georgi Djakov
---
drivers/interconnect/Kconfig | 5 +
drivers/interconnect/Makefile
according to the requested data flow path, physical links and
constraints. The topology could be complicated and multi-tiered and is SoC
specific.
Signed-off-by: Georgi Djakov
---
Documentation/interconnect/interconnect.rst | 93 +++
drivers/Kconfig | 2
Add a device tree node for the A53 PLL, which exists on msm8916
platforms.
Signed-off-by: Georgi Djakov
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index
There are clock controller registers in the APCS block, which purpose
is to control the main CPU mux and divider. Add the clock properties as
part of the APCS device-tree node.
Signed-off-by: Georgi Djakov
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff
The APCS block was exposed until now as a syscon, but now we have a
proper driver for this block. Add the compatible string of the new
driver to probe and register the mailbox functionality.
Signed-off-by: Georgi Djakov
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 7 ---
1 file changed, 4
Add a CPU OPP table to allow CPU frequency scaling on msm8916 platforms.
Signed-off-by: Georgi Djakov
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom
On 22.12.17 г. 2:49, Stephen Boyd wrote:
> On 12/05, Georgi Djakov wrote:
>> This patchset adds support for the A53 CPU clock on MSM8916 platforms
>> and allows scaling of the CPU frequency on msm8916 based platforms.
>
> Ok. I will apply just the clk ones? Patches 3,4, an
On 12/05/2017 08:01 AM, Bjorn Andersson wrote:
> On Fri 01 Dec 09:02 PST 2017, Georgi Djakov wrote:
> [..]
>> diff --git a/drivers/clk/qcom/apcs-msm8916.c
>> b/drivers/clk/qcom/apcs-msm8916.c
>> new file mode 100644
>> index ..f71039ff2347
>> ---
pplied.
* Add gpll0_vote rate propagation patch.
* Update/rebase patches to the current clk-next.
Georgi Djakov (6):
mailbox: qcom: Convert APCS IPC driver to use regmap
mailbox: qcom: Create APCS child device for clock controller
clk: qcom: Add A53 PLL support
clk: qcom: Add regmap mux-div clock
range of frequencies above 1GHz.
Signed-off-by: Georgi Djakov
Acked-by: Bjorn Andersson
---
.../devicetree/bindings/clock/qcom,a53pll.txt | 22 +
drivers/clk/qcom/Kconfig | 10 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom
Update the binding documentation for APCS to mention that the APCS
hardware block also expose a clock controller functionality.
The APCS clock controller is a mux and half-integer divider. It has the
main CPU PLL as an input and provides the clock for the application CPU.
Signed-off-by: Georgi
Add support for hardware that can switch both parent clock and divider
at the same time. This avoids generating intermediate frequencies from
either the old parent clock and new divider or new parent clock and
old divider combinations.
Signed-off-by: Georgi Djakov
---
drivers/clk/qcom/Makefile
the same time.
This is required for enabling CPU frequency scaling on MSM8916-based
platforms.
Signed-off-by: Georgi Djakov
---
drivers/clk/qcom/Kconfig| 11 +++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/apcs-msm8916.c | 149
3
as parent.
Signed-off-by: Georgi Djakov
Acked-by: Bjorn Andersson
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index ab344bc6fa63..57bde0dfd12f
This hardware block provides more functionalities that just IPC. Convert
it to regmap to allow other child platform devices to use the same regmap.
Signed-off-by: Georgi Djakov
Acked-by: Bjorn Andersson
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 24 +++-
1 file changed
Hi Amit,
On 12/08/2017 08:38 PM, Amit Kucheria wrote:
> On Fri, Sep 8, 2017 at 10:48 PM, Georgi Djakov
> wrote:
>> This patch introduce a new API to get requirements and configure the
>> interconnect buses across the entire chipset to fit with the current demand.
>&g
On 08/24/2017 01:55 AM, Stephen Boyd wrote:
> On 08/18, Georgi Djakov wrote:
>> The clock bimc_gpu_clk_src is incorrectly set to use the shared rcg2
>> ops, which are for RCGs with child branches controlled by different
>> CPUs.
>>
>> The result of the incorrect
The RCGs ops for shared branches are not used now, so remove it.
Signed-off-by: Georgi Djakov
---
drivers/clk/qcom/clk-rcg.h | 3 --
drivers/clk/qcom/clk-rcg2.c | 79 -
2 files changed, 82 deletions(-)
diff --git a/drivers/clk/qcom/clk-rcg.h b
according to the requested data flow path, physical links and
constraints. The topology could be complicated and multi-tiered and is SoC
specific.
Signed-off-by: Georgi Djakov
---
Documentation/interconnect/interconnect.rst | 93 +++
drivers/Kconfig | 2
ents).
* Removed public declarations of some structs.
* Now passing prev/next nodes to the vendor driver.
* Properly remove requests on _put().
* Added refcounting.
* Updated documentation.
* Changed struct interconnect_path to use array instead of linked list.
Georgi Djakov (3):
interconnec
Add basic tracepoints in interconnect_set() so we can trace the
performance and the operations which configure the hardware.
Signed-off-by: Georgi Djakov
Cc: Steven Rostedt
Cc: Ingo Molnar
---
drivers/interconnect/interconnect.c | 7 ++
include/trace/events/interconnect.h | 45
Add driver for the Qualcomm interconnect buses found in msm8916 based
platforms. This patch contains only a partial topology to make reviewing
easier.
Signed-off-by: Georgi Djakov
---
drivers/interconnect/Kconfig | 5 +
drivers/interconnect/Makefile
On 8.09.17 г. 21:13, Steven Rostedt wrote:
> On Fri, 8 Sep 2017 20:18:29 +0300
> Georgi Djakov wrote:
>
>> diff --git a/include/trace/events/interconnect.h
>> b/include/trace/events/interconnect.h
>> new file mode 100644
>> index ..c4a72163873c
2 ops.
Fixes: a2e8272f3f89 ("clk: qcom: Add MSM8916 gpu clocks")
Signed-off-by: Georgi Djakov
---
drivers/clk/qcom/gcc-msm8916.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 2cfe7000fc60..3410ee68d4
Add support for hardware that can switch both parent clock and divider
at the same time. This avoids generating intermediate frequencies from
either the old parent clock and new divider or new parent clock and
old divider combinations.
Signed-off-by: Georgi Djakov
---
drivers/clk/qcom/Makefile
the same time.
This is required for enabling CPU frequency scaling on MSM8916-based
platforms.
Signed-off-by: Georgi Djakov
---
.../bindings/mailbox/qcom,apcs-kpss-global.txt | 5 +
drivers/mailbox/qcom-apcs-ipc-mailbox.c| 122 +
2 files changed, 127
.
Changes since v1 (https://lkml.org/lkml/2015/6/12/193)
* Drop SR2 PLL patch, as it is already applied.
* Add gpll0_vote rate propagation patch.
* Update/rebase patches to the current clk-next.
Georgi Djakov (3):
clk: qcom: Add A53 PLL support
clk: qcom: Add regmap mux-div clocks support
range of frequencies above 1GHz.
Signed-off-by: Georgi Djakov
---
.../devicetree/bindings/clock/qcom,a53pll.txt | 22 +
drivers/clk/qcom/Kconfig | 9 +++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/a53-pll.c
w takes (src and dst ports as arguments).
* Removed public declarations of some structs.
* Now passing prev/next nodes to the vendor driver.
* Properly remove requests on _put().
* Added refcounting.
* Updated documentation.
* Changed struct interconnect_path to use array instead of linked list.
Georgi
The interconnect API is not yet using DT bindings for expressing
the relations between the API consumers and providers. This is
posted a separate patch as it needs further discussions on how
to represent this with DT.
Signed-off-by: Georgi Djakov
---
.../bindings/interconnect/interconnect.txt
Add driver for the Qualcomm interconnect controllers found in
msm8916 based platforms.
Signed-off-by: Georgi Djakov
---
drivers/interconnect/Kconfig | 5 +
drivers/interconnect/Makefile| 1 +
drivers/interconnect/qcom/Kconfig| 12
topology node according to the requested data flow path, physical links and
constraints. The topology could be complicated and multi-tiered and is SoC
specific.
Signed-off-by: Georgi Djakov
---
Documentation/interconnect/interconnect.txt | 65 ++
drivers/Kconfig | 2
On 05/15/2017 07:01 PM, Geert Uytterhoeven wrote:
> Hi Georgi,
>
> On Mon, May 15, 2017 at 5:35 PM, Georgi Djakov
> wrote:
>> --- /dev/null
>> +++ b/drivers/interconnect/qcom/interconnect_msm8916.c
>
>> +struct qcom_interconnect_node {
>>
Add driver for the Qualcomm interconnect controllers found in
msm8916 based platforms.
Signed-off-by: Georgi Djakov
---
drivers/interconnect/Kconfig | 5 +
drivers/interconnect/Makefile| 1 +
drivers/interconnect/qcom/Kconfig| 12
The interconnect API is not yet using DT bindings for expressing
the relations between the API consumers and providers. This is
posted a separate patch as it needs further discussions on how
to represent this with DT.
Signed-off-by: Georgi Djakov
---
.../bindings/interconnect/interconnect.txt
ed refcounting.
* Updated documentation.
* Changed struct interconnect_path to use array instead of linked list.
Georgi Djakov (3):
interconnect: Add generic interconnect controller API
interconnect: Add Qualcomm msm8916 interconnect provider driver
dt-binding: Interconnect device-tree bin
topology node according to the requested data flow path, physical links and
constraints. The topology could be complicated and multi-tiered and is SoC
specific.
Signed-off-by: Georgi Djakov
---
Documentation/interconnect/interconnect.txt | 65 +
drivers/Kconfig | 2
On 06/13/2017 04:42 PM, Greg KH wrote:
> On Mon, Jun 12, 2017 at 05:13:57PM +0300, Georgi Djakov wrote:
>> This patch introduce a new API to get the requirement and configure the
>> interconnect buses across the entire chipset to fit with the current demand.
>>
>>
Add support for hardware that can switch both parent clock and divider
at the same time. This avoids generating intermediate frequencies from
either the old parent clock and new divider or new parent clock and
old divider combinations.
Signed-off-by: Georgi Djakov
---
drivers/clk/qcom/Makefile
the same time.
This is required for enabling CPU frequency scaling on MSM8916-based
platforms.
Signed-off-by: Georgi Djakov
---
drivers/clk/qcom/Kconfig| 11 +++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/apcs-msm8916.c | 172
3
Add device-tree binding documentation for the Qualcom APCS clock
controller. This clock controller is a mux and half-integer divider
and provides the clock for the application CPU.
Signed-off-by: Georgi Djakov
---
.../devicetree/bindings/clock/qcom,apcs.txt| 27 ++
1
Move the structure shared by the APCS IPC device and its subdevices
into a separate header file.
Signed-off-by: Georgi Djakov
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 11 +--
include/linux/mailbox/qcom-apcs.h | 34 +
2 files changed, 35
Drop gpll0_vote patch.
* Switch to the new clk_hw_* APIs.
* Rebase to the current clk-next.
Changes since v1 (https://lkml.org/lkml/2015/6/12/193)
* Drop SR2 PLL patch, as it is already applied.
* Add gpll0_vote rate propagation patch.
* Update/rebase patches to the current clk-next.
G
range of frequencies above 1GHz.
Signed-off-by: Georgi Djakov
---
.../devicetree/bindings/clock/qcom,a53pll.txt | 22 +
drivers/clk/qcom/Kconfig | 10 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/a53-pll.c
Register the child platform devices to probe their drivers.
Signed-off-by: Georgi Djakov
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index ab344bc6fa63
This hardware block provides more functionalities that just IPC. Convert
it to regmap to allow other child platform devices to use the same regmap.
Signed-off-by: Georgi Djakov
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 24 +++-
1 file changed, 19 insertions(+), 5
can do better and return that rate instead of a bogus one.
Reported-by: Archit Taneja
Signed-off-by: Georgi Djakov
---
drivers/clk/qcom/clk-smd-rpm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index
Add support for hardware that can switch both parent clock and divider
at the same time. This avoids generating intermediate frequencies from
either the old parent clock and new divider or new parent clock and
old divider combinations.
Signed-off-by: Georgi Djakov
---
drivers/clk/qcom/Makefile
the same time.
This is required for enabling CPU frequency scaling on MSM8916-based
platforms.
Signed-off-by: Georgi Djakov
---
drivers/clk/qcom/Kconfig| 11 +++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/apcs-msm8916.c | 149
3
This hardware block provides more functionalities that just IPC. Convert
it to regmap to allow other child platform devices to use the same regmap.
Signed-off-by: Georgi Djakov
Acked-by: Bjorn Andersson
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 24 +++-
1 file changed
Update the binding documentation for APCS to mention that the APCS
hardware block also expose a clock controller functionality.
The APCS clock controller is a mux and half-integer divider. It has the
main CPU PLL as an input and provides the clock for the application CPU.
Signed-off-by: Georgi
range of frequencies above 1GHz.
Signed-off-by: Georgi Djakov
Acked-by: Rob Herring
---
.../devicetree/bindings/clock/qcom,a53pll.txt | 22 +
drivers/clk/qcom/Kconfig | 10 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/a53
as parent.
Signed-off-by: Georgi Djakov
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index ab344bc6fa63..57bde0dfd12f 100644
--- a/drivers/mailbox
clk_hw_* APIs.
* Rebase to the current clk-next.
Changes since v1 (https://lkml.org/lkml/2015/6/12/193)
* Drop SR2 PLL patch, as it is already applied.
* Add gpll0_vote rate propagation patch.
* Update/rebase patches to the current clk-next.
Georgi Djakov (6):
mailbox: qcom: Convert APCS IPC d
Hi Amit,
On 12/06/2017 07:51 AM, Amit Kucheria wrote:
> On Tue, Dec 5, 2017 at 9:16 PM, Georgi Djakov
> wrote:
>> This patchset adds support for the A53 CPU clock on MSM8916 platforms
>> and allows scaling of the CPU frequency on msm8916 based platforms.
>
> Though
On 12/06/2017 11:08 PM, Rob Herring wrote:
> On Tue, Dec 05, 2017 at 05:46:55PM +0200, Georgi Djakov wrote:
>> This patchset adds support for the A53 CPU clock on MSM8916 platforms
>> and allows scaling of the CPU frequency on msm8916 based platforms.
>>
>> Changes since
Hi,
On 09/08/2017 08:18 PM, Georgi Djakov wrote:
> This patch introduce a new API to get requirements and configure the
> interconnect buses across the entire chipset to fit with the current demand.
>
> The API is using a consumer/provider-based model, where the providers are
> t
CPU frequency scaling on platforms like
MSM8916.
Signed-off-by: Georgi Djakov
---
.../devicetree/bindings/clock/qcom,a53cc.txt | 22 +++
drivers/clk/qcom/Kconfig | 8 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/a53cc.c
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