Since GCC 8.0 -fsanitize=signed-integer-overflow doesn't work with -fwrapv.
-fwrapv makes signed overflows defines and GCC essentially disables
ubsan checks. On GCC < 8.0 -fwrapv doesn't have influence on
-fsanitize=signed-integer-overflow setting, so it kinda works
but generates false-positves and
On Wed, Feb 03, 2021 at 11:31:28AM -0500, Theodore Ts'o wrote:
> On Wed, Feb 03, 2021 at 03:55:06AM -0700, Andreas Dilger wrote:
> >
> > It looks like this change will break the dirdata feature, which is similarly
> > storing a data field beyond the end of the dirent. However, that feature
> > al
Hello My Dearest
Please I appeal to you to exercise a little patience and read through
my mail carefully, I am contacting you personally for investment
assistance and a long term business relationship in your Country.
I am Mrs. Sophia Robin a citizen of the united state of America , I
work at H
On Mon, Feb 08, 2021 at 05:08:06PM +0300, Serge Semin wrote:
> Baikal-T1 SoC is equipped with two DW GMAC v3.73a-based 1GBE ethernet
> interfaces synthesized with: RGMII PHY interface, AXI-DMA and APB3 CSR,
> 16KB Tx/Rx FIFOs and PBL up to half of that, PTP, PMT, TCP/IP CoE, up to 4
> outstanding A
On Tue, 09 Feb 2021 15:16:45 -0800
nnet wrote:
> I've two of these and I've just swapped them (and re-pasted the heat sinks).
>
> The second one ran under load for awhile and now has frozen as well.
>
> Under a moderate load `wget -O /dev/null ` @X00Mbits they are fine.
>
> Under a 1 min speed
Hi,
On Tue, Feb 9, 2021 at 8:09 AM Bjorn Andersson
wrote:
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
> b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
> index 216a74f0057c..2f44785d1af0 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm84
On Tue, Feb 9, 2021 at 12:33 PM Roman Gushchin wrote:
>
> On Tue, Feb 09, 2021 at 09:46:37AM -0800, Yang Shi wrote:
> > Since memcg_shrinker_map_size just can be changed under holding
> > shrinker_rwsem
> > exclusively, the read side can be protected by holding read lock, so it
> > sounds
> > su
On Sat, Jan 16, 2021 at 2:03 AM Ryan Chen wrote:
> >
> > Sorry it did not make it into the merge window. The patch is still in
> > patchwork.
> > I could just pick it up directly for v5.12, or wait for a combined pull
> > request
> > with other work.
>
> Hello Arnd,
> Thanks your update.
>
> >Jo
On Tue, 09 Feb 2021 03:16:45 +0800, Tianling Shen wrote:
> Add devicetree binding documentation for the FriendlyARM NanoPi R4S.
>
> Signed-off-by: Tianling Shen
> ---
> Documentation/devicetree/bindings/arm/rockchip.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring
s/configation/configuration/
Signed-off-by: Bhaskar Chowdhury
---
drivers/net/wireless/broadcom/brcm80211/brcmsmac/d11.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmsmac/d11.h
b/drivers/net/wireless/broadcom/brcm80211/brcmsma
On Tue, Feb 9, 2021 at 12:43 PM Roman Gushchin wrote:
>
> On Tue, Feb 09, 2021 at 09:46:38AM -0800, Yang Shi wrote:
> > Both memcg_shrinker_map_size and shrinker_nr_max is maintained, but
> > actually the
> > map size can be calculated via shrinker_nr_max, so it seems unnecessary to
> > keep bot
On Tue, Feb 9, 2021 at 12:50 PM Roman Gushchin wrote:
>
> On Tue, Feb 09, 2021 at 09:46:39AM -0800, Yang Shi wrote:
> > The following patch is going to add nr_deferred into shrinker_map, the
> > change will
> > make shrinker_map not only include map anymore, so rename it to
> > "memcg_shrinker_i
On Tue 09 Feb 17:25 CST 2021, Doug Anderson wrote:
> Hi,
>
> On Tue, Feb 9, 2021 at 8:09 AM Bjorn Andersson
> wrote:
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
> > b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
> > index 216a74f0057c..2f44785d1af0 100644
> > --- a/arch/arm64/
Hello:
This patch was applied to netdev/net.git (refs/heads/master):
On Tue, 9 Feb 2021 09:52:19 +0100 you wrote:
> In vsock_shutdown() we touched some socket fields without holding the
> socket lock, such as 'state' and 'sk_flags'.
>
> Also, after the introduction of multi-transport, we are ac
On 1/29/21 1:04 PM, Yang Shi wrote:
>> @@ -1527,7 +1527,7 @@ retry:
>> nr_succeeded += nr_subpages;
> It seems the above line is missed. The THP accounting change was
> merged in v5.9 before I submitted this patch.
Thanks for reporting that. Ying found and
On 2/9/21 3:29 PM, Bhaskar Chowdhury wrote:
>
> s/configation/configuration/
>
> Signed-off-by: Bhaskar Chowdhury
Acked-by: Randy Dunlap
Thanks.
> ---
> drivers/net/wireless/broadcom/brcm80211/brcmsmac/d11.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/n
Hi Bjorn,
Thank you! This looks great!
[...]
> commit e8e9aababe60 ("PCI: Apply CONFIG_PCI_DEBUG to entire drivers/pci
> hierarchy")
> Author: Junhao He
> Date: Thu Feb 4 19:30:15 2021 +0800
>
> PCI: Apply CONFIG_PCI_DEBUG to entire drivers/pci hierarchy
>
> CONFIG_PCI_DEBUG=y
On 2/2/21 3:42 AM, Oscar Salvador wrote:
>> +static int __meminit migrate_on_reclaim_callback(struct notifier_block
>> *self,
>> + unsigned long action, void
>> *arg)
>> +{
>> +switch (action) {
>> +case MEM_GOING_OFFLINE:
>> +/*
>>
The only usage of radeon_ttm_vm_ops is to assign its address to the
vm_ops field in the vm_area_struct struct. Make it const to allow the
compiler to put it in read-only memory
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/radeon/radeon_ttm.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
The only usage of nouveau_ttm_vm_ops is to assign its address to the
vm_ops field in the vm_area_struct struct. Make it const to allow the
compiler to put it in read-only memory
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/nouveau/nouveau_ttm.c | 2 +-
1 file changed, 1 insertion(+), 1 de
Constify a few static vm_operations_struct that are never modified. Their
only usage is to assign their address to the vm_ops field in the
vm_area_struct, which is a pointer to const vm_operations_struct. Make them
const to allow the compiler to put them in read-only memory.
With this series appli
The only usage of amdgpu_ttm_vm_ops is to assign its address to the
vm_ops field in the vm_area_struct struct. Make it const to allow the
compiler to put it in read-only memory.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
1 file changed, 1 insertion(+), 1
Am Dienstag, 9. Februar 2021, 23:25:40 CET schrieb Arnd Bergmann:
> On Mon, Jan 18, 2021 at 4:52 PM Johan Jonker wrote:
> >
> > Recently introduced async probe on mmc devices can shuffle block IDs.
> > Pin them to fixed values to ease booting in environments where UUIDs are
> > not practical. Use
Hi folk,
We have released exfatprogs 1.1.0 version. In this release, exfatlabel
has been added to print or re-write volume label and volume serial value.
Also, A new dump.exfat util has been added to display statistics from
a given device(Requested by Mike Fleetwood(GParted Developer)).
Any feedb
On Tue, Feb 09, 2021 at 11:46:40AM -0800, Andrew Morton wrote:
> On Tue, 9 Feb 2021 15:21:28 +0900 Naoya Horiguchi
> wrote:
>
> > Currently hwpoison code checks PageAnon() for thp and refuses to handle
> > errors on non-anonymous thps (just for historical reason). We now
> > support non-anonym
With the introduction of gen9_bc, where Intel combines Cometlake CPUs with
a Tigerpoint PCH, we'll need to introduce new DDC pin mappings for this
platform in order to make all of the display connectors work. So, let's do
that.
Changes since v4:
* Split this into it's own patch - vsyrjala
Cc: Mat
Most a6xx targets have security issues that were fixed with new versions
of the microcode(s). Make sure that we are booting with a safe version of
the microcode for the target and print a message and error if not.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 67 +
-20210209 (attached as .config)
compiler: mipsel-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
#
https://git.kernel.org/pub/scm/linux/kernel/git
Thanks Jakub. Overlooked new warnings as I was using C=2 flag.
Will fix it in the next version.
From: Jakub Kicinski
Sent: Monday, February 8, 2021 11:10 PM
To: Geethasowjanya Akula
Cc: net...@vger.kernel.org; linux-kernel@vger.kernel.org;
linux-cry...@v
As expected, HDMI controller clock should always match pixel clock. In
the past, changing HDMI controller rate would seemingly worsen
situation. However, that was the result of other bugs which are now
fixed.
Fix that by removing set_rate quirk and always set clock rate.
Fixes: 40bb9d3147b2 ("drm
Over the year I got plenty of reports of troubles with H6 HDMI signal.
Sometimes monitor flickers, sometimes there was no image at all and
sometimes it didn't play well with AVR.
It turns out there are multiple issues. Patch 1 fixes clock issue,
which didn't adjust parent rate, even if it is allow
Channel 1 has polarity bits for vsync and hsync signals but driver never
sets them. It turns out that with pre-HDMI2 controllers seemingly there
is no issue if polarity is not set. However, with HDMI2 controllers
(H6) there often comes to de-synchronization due to phase shift. This
causes flickerin
allmodconfig
powerpc allyesconfig
powerpc allnoconfig
x86_64 randconfig-a006-20210209
x86_64 randconfig-a001-20210209
x86_64 randconfig-a005-20210209
x86_64 randconfig-a004-20210209
x86_64
randconfig-a006-20210209
x86_64 randconfig-a001-20210209
x86_64 randconfig-a005-20210209
x86_64 randconfig-a004-20210209
x86_64 randconfig-a002-20210209
x86_64 randconfig-a003-20210209
i386 randconfig-a001
fig
x86_64 randconfig-a006-20210209
x86_64 randconfig-a001-20210209
x86_64 randconfig-a005-20210209
x86_64 randconfig-a004-20210209
x86_64 randconfig-a002-20210209
x86_64 randconfig-a003-20210209
i386 randconfig-a00
allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a006-20210209
x86_64 randconfig-a001-20210209
allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a006-20210209
x86_64 randconfig-a001-20210209
fig
x86_64 randconfig-a006-20210209
x86_64 randconfig-a001-20210209
x86_64 randconfig-a005-20210209
x86_64 randconfig-a004-20210209
x86_64 randconfig-a002-20210209
x86_64 randconfig-a003-20210209
i386 randconfig-a00
allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a006-20210209
x86_64 randconfig-a001-20210209
x86_64 randconfig-a005-20210209
x86_64 randconfig-a004
allmodconfig
powerpc allnoconfig
x86_64 randconfig-a006-20210209
x86_64 randconfig-a001-20210209
x86_64 randconfig-a005-20210209
x86_64 randconfig-a004-20210209
x86_64 randconfig-a002-20210209
x86_64
# Changes since v1 [1]
* Squash together several other patches (Ben)
* Make register locator only search the DVSEC size. Bug fix. (Ben)
* Get rid of anonymous structs in send UAPI (Ben)
* Rename "MB" to "MBOX" in defines (Ben)
* Dynamically allocate enable_cmds bitmask (Ben)
* As
From: Dan Williams
Create the /sys/bus/cxl hierarchy to enumerate:
* Memory Devices (per-endpoint control devices)
* Memory Address Space Devices (platform address ranges with
interleaving, performance, and persistence attributes)
* Memory Regions (active provisioned memory from an address s
Provide enough functionality to utilize the mailbox of a memory device.
The mailbox is used to interact with the firmware running on the memory
device. The flow is proven with one implemented command, "identify".
Because the class code has already told the driver this is a memory
device and the ide
From: Dan Williams
The CXL.mem protocol allows a device to act as a provider of "System
RAM" and/or "Persistent Memory" that is fully coherent as if the memory
was attached to the typical CPU memory controller.
With the CXL-2.0 specification a PCI endpoint can implement a "Type-3"
device interfa
Add a straightforward IOCTL that provides a mechanism for userspace to
query the supported memory device commands. CXL commands as they appear
to userspace are described as part of the UAPI kerneldoc. The command
list returned via this IOCTL will contain the full set of commands that
the driver sup
allnoconfig
x86_64 randconfig-a006-20210209
x86_64 randconfig-a001-20210209
x86_64 randconfig-a005-20210209
x86_64 randconfig-a004-20210209
x86_64 randconfig-a002-20210209
x86_64 randconfig-a003
sparcallyesconfig
mips allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allnoconfig
x86_64 randconfig-a006-20210209
x86_64
allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allnoconfig
x86_64 randconfig-a006-20210209
x86_64 randconfig-a001-20210209
x86_64 randconfig-a005-20210209
x86_64
allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a006-20210209
x86_64 randconfig-a001-20210209
x86_64 randconfig-a005
The CXL memory device send interface will have a number of supported
commands. The raw command is not such a command. Raw commands allow
userspace to send a specified opcode to the underlying hardware and
bypass all driver checks on the command. This is useful for a couple of
usecases, mainly:
1. U
On Tue, 9 Feb 2021 at 19:06, Vlastimil Babka wrote:
> On 2/9/21 4:13 PM, Marco Elver wrote:
> > We cannot rely on CONFIG_DEBUG_KERNEL to decide if we're running a
> > "debug kernel" where we can safely show potentially sensitive
> > information in the kernel log.
> >
> > Therefore, add the option
CXL devices identified by the memory-device class code must implement
the Device Command Interface (described in 8.2.9 of the CXL 2.0 spec).
While the driver already maintains a list of commands it supports, there
is still a need to be able to distinguish between commands that the
driver knows abou
Add initial set of formal commands beyond basic identify and command
enumeration.
Of special note is the Get Log Command which is only specified to return
2 log types, CEL and VENDOR_DEBUG. Given that VENDOR_DEBUG is already a
large catch all for vendor specific information there is no known reaso
Cc: Dan Williams
Cc: Vishal Verma
Cc: Ira Weiny
Cc: Alison Schofield
Signed-off-by: Ben Widawsky
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6eff4f720c72..93c8694a8f04 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -,6 +4
I am getting some compilation error on when using CONFIG_X86_32 kernel
configuration
arch/x86/entry/vdso/vdso32/../vclock_gettime.c:29:1:
error: ‘-mindirect-branch’ and ‘-fcf-protection’ are not compatible
add -fcf-protection=none when CONFIG_RETPOLINE=y
Signed-off-by: Tong Zhang
---
arch/x86
On 2/9/21 2:59 PM, Josh Poimboeuf wrote:
> On Mon, Feb 08, 2021 at 01:39:03PM -0800, Randy Dunlap wrote:
>> On 2/8/21 1:21 PM, Josh Poimboeuf wrote:
>>> On Mon, Feb 08, 2021 at 11:30:59AM -0800, Randy Dunlap wrote:
On 2/8/21 4:52 AM, Stephen Rothwell wrote:
> Hi all,
>
> Changes si
On Tue, Feb 09, 2021 at 03:33:56PM -0800, Yang Shi wrote:
> On Tue, Feb 9, 2021 at 12:50 PM Roman Gushchin wrote:
> >
> > On Tue, Feb 09, 2021 at 09:46:39AM -0800, Yang Shi wrote:
> > > The following patch is going to add nr_deferred into shrinker_map, the
> > > change will
> > > make shrinker_ma
On Wed, Feb 10, 2021 at 02:23:48AM +0300, Andrey Ryabinin wrote:
> Since GCC 8.0 -fsanitize=signed-integer-overflow doesn't work with -fwrapv.
> -fwrapv makes signed overflows defines and GCC essentially disables
> ubsan checks. On GCC < 8.0 -fwrapv doesn't have influence on
> -fsanitize=signed-int
On Wed, Feb 10, 2021 at 02:17:57AM +0300, Andrey Rybainin wrote:
> Subject: ubsan: Require GCC-8+ or Clang to use UBSAN
>
> Just like how we require GCC-8.2 for KASAN due to compiler bugs, require
> a sane version of GCC for UBSAN.
>
> Specifically, before GCC-8 UBSAN
On Tue, Feb 09, 2021 at 09:46:40AM -0800, Yang Shi wrote:
> The shrinker_info is dereferenced in a couple of places via
> rcu_dereference_protected
> with different calling conventions, for example, using mem_cgroup_nodeinfo
> helper
> or dereferencing memcg->nodeinfo[nid]->shrinker_info. And th
On Fri, Feb 05, 2021 at 12:25:22PM -0600, Timur Tabi wrote:
> I can extend make-printk-non-secret to %pK if everyone agrees.
Let's just leave those alone. There is already a toggle for that in
/proc.
--
Kees Cook
On 2/8/2021 7:37 PM, Jason Wang wrote:
On 2021/2/6 下午8:29, Si-Wei Liu wrote:
While virtq is stopped, get_vq_state() is supposed to
be called to get sync'ed with the latest internal
avail_index from device. The saved avail_index is used
to restate the virtq once device is started. Co
On 2/9/21 5:25 PM, Guenter Roeck wrote:
On Tue, Feb 09, 2021 at 04:46:02PM -0500, Waiman Long wrote:
On 2/9/21 3:39 PM, Guenter Roeck wrote:
On Tue, Feb 02, 2021 at 10:57:12AM -0800, Ben Gardon wrote:
rwlocks do not currently have any facility to detect contention
like spinlocks do. In order t
On Tue, 9 Feb 2021, Song Bao Hua (Barry Song) wrote:
> > On Tue, 9 Feb 2021, Song Bao Hua (Barry Song) wrote:
> >
> > > > On Sun, 7 Feb 2021, Xiaofei Tan wrote:
> > > >
> > > > > Replace spin_lock_irqsave with spin_lock in hard IRQ of SCSI
> > > > > drivers. There are no function changes, but ma
> Right at the beginning - we implemented PP function into the Kernel
> driver like the SDMA operation (This is the RX/TX DMA engine).
> We do plan to port more and more PP functions as Kernel drivers
> along the way.
It will be interesting to see how well you manage to handle the 'split
brain' p
-20210209 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project
c9439ca36342fb6013187d0a69aef92736951476)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin
> -Original Message-
> From: Finn Thain [mailto:fth...@telegraphics.com.au]
> Sent: Wednesday, February 10, 2021 1:29 PM
> To: Song Bao Hua (Barry Song)
> Cc: tanxiaofei ; j...@linux.ibm.com;
> martin.peter...@oracle.com; linux-s...@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux
Amazon NVMe controllers do not support 64-bit DMA addresses; they are
limited to 48-bit DMA addresses. Let's add a quirk to ensure that we
make use of 48-bit DMA addresses to avoid misbehavior.
This affects all Amazon NVMe controllers that expose EBS volumes
(0x0061, 0x0065, 0x8061) and local ins
On Tue, Feb 09, 2021 at 09:46:41AM -0800, Yang Shi wrote:
> Currently registered shrinker is indicated by non-NULL shrinker->nr_deferred.
> This approach is fine with nr_deferred at the shrinker level, but the
> following
> patches will move MEMCG_AWARE shrinkers' nr_deferred to memcg level, so th
ath10k_debug_fw_stats_request() is called ath10k_sta_statistics()
without holding conf_mutex. ath10k_debug_fw_stats_request() simply
returns when CONFIG_ATH10K_DEBUGFS is disabled.
When CONFIG_ATH10K_DEBUGFS is enabled, ath10k_debug_fw_stats_request()
code path isn't protected. This assert is trig
I have been seeing lockdep asserts for a couple of months and finally
found time to debug and fix the problems. The dmesg looks clean with
these fixes.
Enabling LOCKDEP and ATH10K_DEBUGFS triggers the lockdep assert and
RCU warns.
The first two patches in this series are fixes to lockdep assert a
On 2/9/21 7:27 PM, Waiman Long wrote:
On 2/9/21 5:25 PM, Guenter Roeck wrote:
On Tue, Feb 09, 2021 at 04:46:02PM -0500, Waiman Long wrote:
On 2/9/21 3:39 PM, Guenter Roeck wrote:
On Tue, Feb 02, 2021 at 10:57:12AM -0800, Ben Gardon wrote:
rwlocks do not currently have any facility to detect c
Add tests that specify a valid range, but one that is outside the
width of the bitmap for which it is to be applied to. These should
trigger an -ERANGE response from the code.
Cc: Yury Norov
Cc: Rasmus Villemoes
Cc: Andy Shevchenko
Signed-off-by: Paul Gortmaker
---
lib/test_bitmap.c | 2 ++
ieee80211_find_sta_by_ifaddr() must be called under the RCU lock and
the resulting pointer is only valid under RCU lock as well.
Fix ath10k_wmi_tlv_parse_peer_stats_info() to hold RCU lock before it
calls ieee80211_find_sta_by_ifaddr() and release it when the resulting
pointer is no longer needed.
Based on the comment block in this function and the FIXME for this, peer
being present for the offchannel tx is unlikely. Peer is deleted once tx
is complete. Change peer present msg to a warn to detect this condition.
Signed-off-by: Shuah Khan
---
drivers/net/wireless/ath/ath10k/mac.c | 5 ++---
ath10k_drain_tx() must not be called with conf_mutex held as workers can
use that also. Add check to detect conf_mutex held calls.
Signed-off-by: Shuah Khan
---
drivers/net/wireless/ath/ath10k/mac.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/wireless/ath/ath10k/mac.c
b/driv
ath10k_mac_get_rate_flags_ht() floods dmesg with the following messages,
when it fails to find a match for mcs=7 and rate=1440.
supported_ht_mcs_rate_nss2:
{7, {1300, 2700, 1444, 3000} }
ath10k_pci :02:00.0: invalid ht params rate 1440 100kbps nss 2 mcs 7
dev_warn_ratelimited() isn't helpin
This block of tests was meant to find/flag incorrect use of the ":"
and "/" separators (syntax errors) and invalid (zero) group len.
However they were specified with an 8 bit width and 32 bit operations,
so they really contained two errors (EINVAL and ERANGE).
Promote them to 32 bit so it is clea
There are inputs to bitmap_parselist() that would probably never
be entered manually by a person, but might result from some kind of
automated input generator. Things like ranges of length 1, or group
lengths longer than nbits, overlaps, or offsets of zero.
Adding these tests serve two purposes:
On Tue, 9 Feb 2021 02:51:31 +
Jianlin Lv wrote:
>
>
> > -Original Message-
> > From: Masami Hiramatsu
> > Sent: Monday, February 8, 2021 8:33 PM
> > To: Jianlin Lv
> > Cc: pet...@infradead.org; mi...@redhat.com; a...@kernel.org; Mark
> > Rutland ; alexander.shish...@linux.intel.co
With the core bitmap support now accepting "N" as a placeholder for
the end of the bitmap, "all" can be represented as "0-N" and has the
advantage of not being specific to RCU (or any other subsystem).
So deprecate the use of "all" by removing documentation references
to it. The support itself ne
Most a6xx targets have security issues that were fixed with new versions
of the microcode(s). Make sure that we are booting with a safe version of
the microcode for the target and print a message and error if not.
v2: Add more informative error messages and fix typos
Signed-off-by: Jordan Crouse
A region is a standalone entity to some degree, but it needs to
be paired with a bitmap width in order to set context and determine
if the region even fits into the width of the bitmap.
This will reduce parameter passing and enable using nbits as part
of future dynamic region parameter parsing.
C
From: Thomas Gleixner
The per CPU hardirq_stack_ptr contains the pointer to the irq stack in the
form that it is ready to be assigned to [ER]SP so that the first push ends
up on the top entry of the stack.
But the stack switching on 64 bit has the following rules:
1) Store the current stack
From: Thomas Gleixner
The recursion protection for hard interrupt stacks is an unsigned int per
CPU variable initialized to -1 named __irq_count.
The irq stack switching is only done when the variable is -1, which creates
worse code than just checking for 0. When the stack switching happens it
From: Thomas Gleixner
Convert device interrupts to inline stack switching by replacing the
existing macro implementation with the new inline version. Tweak the
function signature of the actual handler function to have the vector
argument as u32. That allows the inline macro to avoid extra interme
From: Thomas Gleixner
Use the new inline stack switching and remove the old ASM indirect call
implementation.
Signed-off-by: Thomas Gleixner
Reviewed-by: Kees Cook
---
arch/x86/entry/entry_64.S| 39 -
arch/x86/include/asm/irq_stack.h | 52 -
From: Thomas Gleixner
The effort to make the ASM entry code slim and unified moved the irq stack
switching out of the low level ASM code so that the whole return from
interrupt work and state handling can be done in C and the ASM code just
handles the low level details of entry and exit.
This en
This is the second version of this series. V1 is available here:
https://lore.kernel.org/r/20210204204903.350275...@linutronix.de
The recent effort to make the ASM entry code slim and unified moved
the irq stack switching out of the low level ASM code so that the
whole return from interrupt wor
From: Thomas Gleixner
Embracing a callout into instrumentation_begin() / instrumentation_begin()
does not really make sense. Make the latter instrumentation_end().
Fixes: 2f6474e4636b ("x86/entry: Switch XEN/PV hypercall entry to IDTENTRY")
Signed-off-by: Thomas Gleixner
Reviewed-by: Kees Cook
From: Thomas Gleixner
Now that all invocations of irq_exit_rcu() happen on the irq stack, turn on
CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK which causes the core code to invoke
__do_softirq() directly without going through do_softirq_own_stack().
That means do_softirq_own_stack() is only invoked from ta
Hello,
syzbot found the following issue on:
HEAD commit:dd86e7fa Merge tag 'pci-v5.11-fixes-2' of git://git.kernel..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=13e43f90d0
kernel config: https://syzkaller.appspot.com/x/.config?x=e83e68d0a6aba5f6
das
Quoting tudor.amba...@microchip.com (2021-02-08 01:49:45)
> Hi, Michael, Stephen,
>
> Do you plan to take this patch for v5.12?
> If fw_devlink will remain set to ON for v5.12, some of our boards will
> no longer boot without this patch.
Is fw_devlink defaulted to on for v5.12?
From: Thomas Gleixner
sysvec_spurious_apic_interrupt() calls into the handling body of
__spurious_interrupt() which is not obvious as that function is declared
inside the DEFINE_IDTENTRY_IRQ(spurious_interrupt) macro.
As __spurious_interrupt() is currently always inlined this ends up with two
co
From: Thomas Gleixner
To inline the stack switching and to prepare for enabling
CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK provide a macro template for system
vectors and device interrupts and convert the system vectors over to it.
Signed-off-by: Thomas Gleixner
Reviewed-by: Kees Cook
---
V2: Adopt to
From: Thomas Gleixner
To avoid yet another macro implementation reuse the existing
run_sysvec_on_irqstack_cond() and move the set_irq_regs() handling into the
called function. Makes the code even simpler.
Signed-off-by: Thomas Gleixner
Reviewed-by: Kees Cook
---
arch/x86/entry/common.c | 1
To prepare for inlining do_softirq_own_stack() replace
__ARCH_HAS_DO_SOFTIRQ with a Kconfig switch and select it in the affected
architectures.
This allows in the next step to move the function prototype and the inline
stub into a seperate asm-generic header file which is required to avoid
include
To avoid include recursion hell move the do_softirq_own_stack() related
content into a generic asm header and include it from all places in arch/
which need the prototype.
This allows architectures to provide an inline implementation of
do_softirq_own_stack() without introducing a lot of #ifdeffer
From: Thomas Gleixner
There is no reason to have this as a seperate function for a single caller.
Signed-off-by: Thomas Gleixner
Reviewed-by: Kees Cook
---
V2: Adopt to the new header file.
---
arch/x86/include/asm/irq_stack.h |3 +--
arch/x86/include/asm/softirq_stack.h | 11 ++
On Tue, Feb 9, 2021 at 4:54 PM Stephen Boyd wrote:
>
> Quoting tudor.amba...@microchip.com (2021-02-08 01:49:45)
> > Hi, Michael, Stephen,
> >
> > Do you plan to take this patch for v5.12?
> > If fw_devlink will remain set to ON for v5.12, some of our boards will
> > no longer boot without this pa
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