From: Daire McNamara
Add device tree bindings for the Microchip PolarFire system
clock controller
Signed-off-by: Daire McNamara
---
.../bindings/clock/microchip,mpfs.yaml| 73 +++
1 file changed, 73 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clo
On Thu, Jan 07, 2021 at 07:32:07PM +0800, 李捷 wrote:
> >From 0fbcd7e386898d829d3000d094358a91e626ee4a Mon Sep 17 00:00:00 2001
> From: Jie Li
> Date: Mon, 7 Dec 2020 08:05:07 +0800
> Subject: [PATCH] uio: uio_pci_generic: don't fail probe if pdev->irq equals to
> IRQ_NOTCONNECTED
Why is this in t
A: http://en.wikipedia.org/wiki/Top_post
Q: Were do I find info about this thing called top-posting?
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing in e-mail?
A: No.
Q: Should I includ
Hi Atish,
On 12/4/20 8:58 AM, Atish Patra wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Add Microchip PolarFire kconfig option which selects SoC specific
> and common drivers that is required for this SoC.
>
> Signed-off-by: Atish Patra
On 2021-01-07 20:05, Daniel Borkmann wrote:
>
> On 1/7/21 1:39 AM, Dongseok Yi wrote:
> > skbs in fraglist could be shared by a BPF filter loaded at TC. It
> > triggers skb_ensure_writable -> pskb_expand_head ->
> > skb_clone_fraglist -> skb_get on each skb in the fraglist.
> >
> > While tcpdump,
On Thu, Jan 7, 2021 at 7:18 PM Michal Hocko wrote:
>
> On Thu 07-01-21 16:53:13, Muchun Song wrote:
> > On Thu, Jan 7, 2021 at 4:41 PM Michal Hocko wrote:
> > >
> > > On Thu 07-01-21 13:39:38, Muchun Song wrote:
> > > > On Thu, Jan 7, 2021 at 12:56 AM Michal Hocko wrote:
> > > > >
> > > > > On W
On Thu, 7 Jan 2021 10:13:43 +0100
Hans Verkuil wrote:
> On 08/12/2020 16:55, Adrian Ratiu wrote:
> > Some configurations built by the ktest bot produce the following
> > warn, so mark the struct as __maybe_unused to avoid unnecessary
> > ML spam.
> >
> >>> drivers/staging/media/rkvdec/rkvdec.c
Section 3.11 was incorrectly called 3.9, fix it.
Signed-off-by: Viresh Kumar
---
Documentation/kbuild/makefiles.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/kbuild/makefiles.rst
b/Documentation/kbuild/makefiles.rst
index d36768cf1250..9f6a11881951 100644
From: lijinlin
For enhancing diagnosis capability when scsi device reset，we direct print
these logs which are infrequently printed, and add disk name to logs.
logs as follow:
[ 550.268049] sd 3:0:0:0: [sdc] Sending device reset
[ 550.268053] sd 3:0:0:0: [sdc] Sending target reset
[ 550.268055
Hi Atish,
On 12/4/20 8:58 AM, Atish Patra wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Add initial DTS for Microchip ICICLE board having only
> essential devices (clocks, sdhci, ethernet, serial, etc).
> The device tree is based on the
On Thu 07-01-21 19:24:59, Muchun Song wrote:
> On Thu, Jan 7, 2021 at 7:16 PM Michal Hocko wrote:
> >
> > On Thu 07-01-21 10:52:21, Muchun Song wrote:
> > > On Thu, Jan 7, 2021 at 12:13 AM Michal Hocko wrote:
> > > >
> > > > On Wed 06-01-21 16:47:34, Muchun Song wrote:
> > > > > If the refcount i
On 2021/1/7 4:22, Jaegeuk Kim wrote:
On 12/09, Jaegeuk Kim wrote:
On 12/10, Chao Yu wrote:
Hi Daeho, Jaegeuk
I found one missing place in this patch which should adapt
"compress vs verity race bugfix"
Could you please check and apply below diff?
Applied.
Hi Chao,
Could you please rebase
On Sat, Dec 19, 2020 at 01:23:17PM +0800, Sang Yan wrote:
> Introducing a feature of CPU PARK in order to save time
> of cpus down and up during kexec, which may cost 250ms of
> per cpu's down and 30ms of up.
Where is that 250ms spent? Is that mostly in FW, or in the kernel
preparing/monitoring th
Hi Arnd,
On Wed, 6 Jan 2021, Arnd Bergmann wrote:
> On Tue, Jan 5, 2021 at 8:07 PM Arnd Bergmann wrote:
> > Change it to use the normal probe order of starting with a specific
> > device in a driver, turning the sof-acpi-dev.c driver into a library.
>
> There were a couple of build failures int
This series hunts the problems discovered after manual enabling of
ARCH_WANT_LD_ORPHAN_WARN. Notably:
- adds the missing PAGE_ALIGNED_DATA() section affecting VDSO
placement (marked for stable);
- properly stops .eh_frame section generation.
Compile and runtime tested on MIPS32R2 CPS board wi
MIPS uses its own declaration of rwdata, and thus it should be kept
in sync with the asm-generic one. Currently PAGE_ALIGNED_DATA() is
missing from the linker script, which emits the following ld
warnings:
mips-alpine-linux-musl-ld: warning: orphan section
`.data..page_aligned' from `arch/mips/ker
Hi Jassi Brar
Thank you very much for your reply.
Look at the function sprd_mbox_outbox_isr .
Chan is !NULL.
chan->cl is NULL when the client driver not loaded, the controller
driver don't know the client driver loaded successfully, so, I do not
use mbox_free_channel.
Here,How do you know chan
Discard GNU attributes (MIPS FP type, GNU Hash etc.) at link time
as kernel doesn't use it at all.
Solves a dozen of the following ld warnings (one per every file):
mips-alpine-linux-musl-ld: warning: orphan section `.gnu.attributes'
from `arch/mips/kernel/head.o' being placed in section
`.gnu.att
Commit 866b6a89c6d1 ("MIPS: Add DWARF unwinding to assembly") added
-fno-asynchronous-unwind-tables to KBUILD_CFLAGS to prevent compiler
from emitting .eh_frame symbols.
However, as MIPS heavily uses CFI, that's not enough. Use the
approach taken for x86 (as it also uses CFI) and explicitly put CFI
Now, after that all the sections are explicitly described and
declared in vmlinux.lds.S, we can enable ld orphan warnings to
prevent from missing any new sections in future.
Signed-off-by: Alexander Lobakin
Reviewed-by: Kees Cook
---
arch/mips/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff
LLVM stack generates GOT table when building the kernel:
ld.lld: warning: :(.got) is being placed in '.got'
According to the debug assertions, it's not zero-sized and thus
can't be handled the same way as .rel.dyn (like it's done for x86).
Use the ARM/ARM64 path here and place it at the end of .t
Catch any symbols placed in .rel.dyn and check for these sections
to be zero-sized at link time.
Eliminates following ld warning:
mips-alpine-linux-musl-ld: warning: orphan section `.rel.dyn'
from `init/main.o' being placed in section `.rel.dyn'
Adopted from x86/kernel/vmlinux.lds.S.
Suggested-b
When building kernel with LD_DEAD_CODE_DATA_ELIMINATION, LLVM stack
generates separate sections for compound literals, just like in case
with enabled LTO [0]:
ld.lld: warning: drivers/built-in.a(mtd/nand/spi/gigadevice.o):
(.data..compoundliteral.14) is being placed in
'.data..compoundliteral.14'
From: Kees Cook
Date: Wed, 6 Jan 2021 15:26:18 -0800
> On Wed, Jan 06, 2021 at 10:36:38PM +, Alexander Lobakin wrote:
>> From: Kees Cook
>> Date: Wed, 6 Jan 2021 14:07:07 -0800
>>
>>> On Wed, Jan 06, 2021 at 08:08:19PM +, Alexander Lobakin wrote:
Discard GNU attributes at link time
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月7日 週四 上午11:12寫道：
>
> Add DDP support for MT8167 SoC.
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 48
> ++
> 1 file changed, 48 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk
From: SeongJae Park
NOTE: This RFC has a dependancy on DAMON (Data Access MONitor)
patchset[1], which is not merged in the mainline yet. The aim of this
is to show how DAMON would be evolved once it is merged in and get some
comments early. So, if you have some interest in this, please consider
On Sun, Dec 27, 2020 at 12:20:34AM +0100, Jiri Olsa wrote:
> hi,
> adding support to enable/disable specific events via control
> file via following commands:
>
> # echo 'enable sched:sched_process_fork' > control
> # echo 'disabled sched:sched_process_fork' > control
>
> v4 changes:
>
On Thu, Jan 07, 2021 at 11:39:14AM +, Partha Nayak wrote:
> Hi Greg / Linux community
>
> I was going through the patch details:
> https://www.spinics.net/lists/stable/msg436529.html .
>
> In our case the superblock for EXT4 is configured to trigger a kernel panic .
> But inspite of that th
Add support for w25q512jvq. This is of the same series chip with
w25q256jv, which is already supported, but with size doubled and
different JEDEC ID.
Tested on Intel whitley platform with dd from/to the flash for
read/write respectly, and flash_erase for erasing the flash.
Signed-off-by: Shuhao M
On Thu, Jan 07, 2021 at 03:52:12PM +0800, Wen Yang wrote:
> The dentries such as /proc//ns/ have the DCACHE_OP_DELETE flag, they
> should be deleted when the process exits.
>
> Suppose the following race appears：
>
> release_task dput
> -> proc_flush_task
>
Move elliptic curves definition to 'include/crypto/ecc_curve_defs.h',
so all can use it,
Signed-off-by: Meng Yu
Reviewed-by: Zaibo Xu
---
crypto/ecc.c| 1 -
crypto/ecc.h| 37 +
crypto/ecc_curve_defs.h | 57
1. Move elliptic curve parameter definitions out to "include/crypto";
2. Add some new elliptic curve parameters definitions, and reorder
ECC 'Curves IDs';
3. Add ECDH and CURVE25519 algorithms support for Kunpeng 930.
v5->v6:
- patch #1: add a new patch (the first patch), which is the "depend o
Algorithm type is brought in to get hardware HPRE queue
to support different algorithms.
Signed-off-by: Meng Yu
Reviewed-by: Zaibo Xu
---
drivers/crypto/hisilicon/hpre/hpre.h| 10 +-
drivers/crypto/hisilicon/hpre/hpre_crypto.c | 12 ++--
drivers/crypto/hisilicon/hpre/hpr
From: Hui Tang
HPRE of Kunpeng 930 is updated on cluster numbers and configurations
of Kunpeng 920 HPRE, so we try to update this driver to make it running
okay on both chips.
Signed-off-by: Hui Tang
Signed-off-by: Meng Yu
Reviewed-by: Zaibo Xu
---
drivers/crypto/hisilicon/hpre/hpre.h |
1. Add some new 'ECDH' curve parameter definitions to
'include/crypto/ecc_curve_defs.h', and reorder ECC 'Curves IDs'
in 'include/crypto/ecdh.h';
2. Enable 'ECDH' algorithm in Kunpeng 930.
Signed-off-by: Meng Yu
Reviewed-by: Zaibo Xu
---
crypto/ecc.c| 4 +
Add #interconnect-cells on main &noc so that it will probe the interconnect
provider.
Signed-off-by: Martin Kepplinger
Acked-by: Georgi Djakov
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
b/arch/arm6
1. Add 'CURVE25519' curve parameter definition to
'include/crypto/ecc_curve_defs.h';
2. Enable 'CURVE25519' algorithm in Kunpeng 930.
Signed-off-by: Meng Yu
Reviewed-by: Zaibo Xu
Reported-by: kernel test robot
---
drivers/crypto/hisilicon/Kconfig| 1 +
drivers/crypto/hisilicon
From: Leonard Crestez
Add initial support for dynamic frequency scaling of the main NOC
on imx8mq.
Make DDRC the parent of the NOC (using passive governor) so that the
main NOC is automatically scaled together with DDRC by default.
Support for proactive scaling via interconnect will come on top
Add optional interconnect properties for the dram path requests.
Signed-off-by: Martin Kepplinger
---
Documentation/devicetree/bindings/display/mxsfb.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mxsfb.txt
b/Documentation/devicetree/bind
A new generation of accelerator Kunpeng930 has appeared, and the
corresponding driver needs to be updated to support some new
algorithms of Kunpeng930. To be compatible with Kunpeng920, we
add parameter 'struct hisi_qm *qm' to sec_algs_(un)register to
identify the chip's version.
Signed-off-by: Me
Add interconnect ports for lcdif to set bus capabilities.
Signed-off-by: Martin Kepplinger
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 89e7de2e7f7
revision history:
v4: (thanks Shawn, Georgi and Greg)
* reorder to have dt-bindings doc before code addition
* add newline between dt nodes
* removed "interconnect: imx8mq: Use icc_sync_state" from the patchset
since it's part of gregkh/char-misc.git
* Add acks
v3: (thanks Krysztof and Geor
Enable INTERCONNECT_IMX8MQ in order to make interconnect more widely
available.
Signed-off-by: Martin Kepplinger
Acked-by: Georgi Djakov
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 3ca9d
On Thu, 7 Jan 2021 at 12:26, Valentin Schneider
wrote:
>
> On 07/01/21 11:33, Vincent Guittot wrote:
> > Active balance is triggered for a number of voluntary cases like misfit
> > or pinned tasks cases but also after that a number of load balance
> > attempts failed to migrate a task. There is no
Hello folks,
My comments are below.
On Wed, Jan 06, 2021 at 01:44:28PM +0200, Andy Shevchenko wrote:
> On Wednesday, January 6, 2021, Bartosz Golaszewski <
> bgolaszew...@baylibre.com> wrote:
>
> > On Mon, Dec 7, 2020 at 2:10 PM luojiaxing wrote:
> > >
> > >
> > > On 2020/12/7 2:50, Marc Zyngier
The ROHM PMIC regulator drivers only need the regmap pointer from
the parent device. Regmap can be obtained via dev_get_regmap()
so do not require parent to populate driver data for that.
Signed-off-by: Matti Vaittinen
---
Sorry for not including this in previous cleanup patch I sent yesterday.
This patchset is to improve tlb flushing performance in iommu_map/unmap
for MediaTek IOMMU.
For iommu_map, currently MediaTek IOMMU use IO_PGTABLE_QUIRK_TLBI_ON_MAP
to do tlb_flush for each a memory chunk. this is so unnecessary. we could
improve it by tlb flushing one time at the end of iommu_map
Remove IO_PGTABLE_QUIRK_TLBI_ON_MAP to avoid tlb sync for each a small
chunk memory, Use the new iotlb_sync_map to tlb_sync once for whole the
iova range of iommu_map.
Signed-off-by: Yong Wu
Reviewed-by: Robin Murphy
---
drivers/iommu/mtk_iommu.c | 10 +-
1 file changed, 9 insertions(+)
iotlb_sync_map allow IOMMU drivers tlb sync after completing the whole
mapping. This patch adds iova and size as the parameters in it. then the
IOMMU driver could flush tlb with the whole range once after iova mapping
to improve performance.
Signed-off-by: Yong Wu
Reviewed-by: Robin Murphy
---
This patch allows io_pgtable_tlb ops could be null since the IOMMU drivers
may use the tlb ops from iommu framework.
Signed-off-by: Yong Wu
---
include/linux/io-pgtable.h | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgt
> This series hunts the problems discovered after manual enabling of
> ARCH_WANT_LD_ORPHAN_WARN. Notably:
> - adds the missing PAGE_ALIGNED_DATA() section affecting VDSO
>placement (marked for stable);
> - properly stops .eh_frame section generation.
>
> Compile and runtime tested on MIPS32R
Until now, we have already used the tlb operations from iommu framework,
then the tlb operations for v7s can be removed.
Correspondingly, Switch the paramenter "cookie" to the internal structure.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 27 ---
1 file chang
Currently gather->end is "unsigned long" which may be overflow in
arch32 in the corner case: 0xfff0 + 0x10(iova + size).
Although it doesn't affect the size(end - start), it affects the checking
"gather->end < end"
This patch changes this "end" to the real end address
(end = start + size -
In current iommu_unmap, this code is:
iommu_iotlb_gather_init(&iotlb_gather);
ret = __iommu_unmap(domain, iova, size, &iotlb_gather);
iommu_iotlb_sync(domain, &iotlb_gather);
We could gather the whole iova range in __iommu_unmap, and then do tlb
synchronization in the iomm
In the end of __iommu_map, It alway call iotlb_sync_map.
This patch moves iotlb_sync_map out from __iommu_map since it is
unnecessary to call this for each sg segment especially iotlb_sync_map
is flush tlb all currently. Add a little helper _iommu_map for this.
Signed-off-by: Yong Wu
Reviewed-by
On 06.01.21 07:11, Anshuman Khandual wrote:
> Hi Sudershan,
>
> This patch (and the cover letter) does not copy LAKML even though the
> entire change here is arm64 specific. Please do copy all applicable
> mailing lists for a given patch.
>
> On 1/6/21 6:58 AM, Sudarshan Rajagopalan wrote:
>> Cur
On Thu, 2021-01-07 at 12:41 +0100, Boris Brezillon wrote:
> On Thu, 7 Jan 2021 10:13:43 +0100
> Hans Verkuil wrote:
>
> > On 08/12/2020 16:55, Adrian Ratiu wrote:
> > > Some configurations built by the ktest bot produce the following
> > > warn, so mark the struct as __maybe_unused to avoid unnec
In hugetlb_sysfs_add_hstate(), we would do kobject_put() on hstate_kobjs
when failed to create sysfs group but forget to set hstate_kobjs to NULL.
Then in hugetlb_register_node() error path, we may free it again via
hugetlb_unregister_node().
Fixes: a3437870160c ("hugetlb: new sysfs interface")
Si
MIPS uses its own declaration of rwdata, and thus it should be kept
in sync with the asm-generic one. Currently PAGE_ALIGNED_DATA() is
missing from the linker script, which emits the following ld
warnings:
mips-alpine-linux-musl-ld: warning: orphan section
`.data..page_aligned' from `arch/mips/ker
This series hunts the problems discovered after manual enabling of
ARCH_WANT_LD_ORPHAN_WARN. Notably:
- adds the missing PAGE_ALIGNED_DATA() section affecting VDSO
placement (marked for stable);
- properly stops .eh_frame section generation.
Compile and runtime tested on MIPS32R2 CPS board wi
Commit 866b6a89c6d1 ("MIPS: Add DWARF unwinding to assembly") added
-fno-asynchronous-unwind-tables to KBUILD_CFLAGS to prevent compiler
from emitting .eh_frame symbols.
However, as MIPS heavily uses CFI, that's not enough. Use the
approach taken for x86 (as it also uses CFI) and explicitly put CFI
The huge page size is encoded for VM_FAULT_HWPOISON errors only. So if we
return VM_FAULT_HWPOISON, huge page size would just be ignored.
Fixes: aa50d3a7aa81 ("Encode huge page size for VM_FAULT_HWPOISON errors")
Signed-off-by: Miaohe Lin
Cc:
---
mm/hugetlb.c | 2 +-
1 file changed, 1 insertion
Discard GNU attributes (MIPS FP type, GNU Hash etc.) at link time
as kernel doesn't use it at all.
Solves a dozen of the following ld warnings (one per every file):
mips-alpine-linux-musl-ld: warning: orphan section `.gnu.attributes'
from `arch/mips/kernel/head.o' being placed in section
`.gnu.att
In VM_MAP_PUT_PAGES case, we should put pages and free array in vfree. But
we missed to set area->nr_pages in vmap(). So we would failed to put pages
in __vunmap() because area->nr_pages = 0.
Fixes: b944afc9d64d ("mm: add a VM_MAP_PUT_PAGES flag for vmap")
Signed-off-by: Shijie Luo
Signed-off-by:
Hi Sean,
On 2021/1/6 5:11, Sean Christopherson wrote:
On Mon, Jan 04, 2021, Like Xu wrote:
If IA32_PERF_CAPABILITIES.PEBS_BASELINE [bit 14] is set, the
IA32_PEBS_ENABLE MSR exists and all architecturally enumerated fixed
and general purpose counters have corresponding bits in IA32_PEBS_ENABLE
t
We are about to introduce support for sysreg access to ETMv4.4+
component. Since there are generic routines that access the
registers (e.g, CS_LOCK/UNLOCK , claim/disclaim operations, timeout)
and in order to preserve the logic of these operations at a
single place we introduce an abstraction layer
From: Colin Ian King
Currently the error return paths don't kfree lmac and lmac->name
leading to some memory leaks. Fix this by adding two error return
paths that kfree these objects
Addresses-Coverity: ("Resource leak")
Fixes: 1463f382f58d ("octeontx2-af: Add support for CGX link management")
Prepare the TPIU driver to make use of the CoreSight device access
abstraction layer. The driver touches the device even before the
coresight device is registered. Thus we could be accessing the
devices without a csdev. As we are about to use the abstraction
layer for accessing the device, pass in
TRCSSPCICR is present only if all of the following are true:
TRCIDR4.NUMSSCC > n.
TRCIDR4.NUMPC > 0b .
TRCSSCSR.PC == 0b1
Add a helper function to check all the conditions.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since
When the ETM is affected by Qualcomm errata, modifying the
TRCPDCR could cause the system hang. Even though this is
taken care of during enable/disable ETM, the ETM state
save/restore could still access the TRCPDCR. Make sure
we skip the access during the save/restore.
Found by code inspection.
F
On Thu 07-01-21 19:38:00, Muchun Song wrote:
> On Thu, Jan 7, 2021 at 7:18 PM Michal Hocko wrote:
> >
> > On Thu 07-01-21 16:53:13, Muchun Song wrote:
> > > On Thu, Jan 7, 2021 at 4:41 PM Michal Hocko wrote:
> > > >
> > > > On Thu 07-01-21 13:39:38, Muchun Song wrote:
> > > > > On Thu, Jan 7, 202
CoreSight ETMv4.4 obsoletes memory mapped access to ETM and
mandates the system instructions for registers.
This also implies that they may not be on the amba bus.
Right now all the CoreSight components are accessed via memory
map. Also, we have some common routines in coresight generic
code driver
We rely on the ETM architecture version to decide whether
Secure EL2 is available on the CPU for excluding the level
for address comparators and viewinst main control register.
We must instead use the TRCDIDR3.EXLEVEL_S field to detect
the supported levels.
Reviewed-by: Mathieu Poirier
Signed-off
Convert the generic CLAIM tag management APIs to use the
device access layer abstraction.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since V3:
- Removed WARN_ON(!csdev) check. (Mathieu)
- Fixed indentation (Mathieu)
---
drivers/hwtracing/coresight
etm4_get_access_type() calculates the exception level bits
for use in address comparator registers. This is also used
by the TRCVICTLR register by shifting to the required position.
This patch cleans up the logic to make etm4_get_access_type()
calcualte a generic mask which can be used by all user
We are about to rely on TRCDEVARCH for detecting the ETM
and its architecture version, falling back to TRCIDR1 if
the former is not implemented (in older broken implementations).
Also, we use the architecture version information to
make some decisions. Streamline the architecture version
handling
Add support for devices with system instruction access only.
They don't have a memory mapped interface and thus are not
AMBA devices. System register access is not permitted to
TRCPDCR and thus skip access to them.
Cc: Mike Leach
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes s
We have been using TRCIDR1 for detecting the ETM version. This
is in preparation for the future IP support.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c | 46 +--
1 file changed, 23 insertions(+),
CoreSight ETM with system register access may not have a
memory mapped i/o access. Refactor the ETM specific probing
into a common routine to allow reusing the code for such ETMs.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since v4:
- Refactor the "
ETM v4.4 onwards adds support for system instruction access
to the ETM. Detect the support on an ETM and switch to using the
mode when available.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c | 39 +
As we are about to add support for system register based devices,
we don't get an AMBA pid. So, the detection code could check
the system registers running on the CPU to check for the architecture
specific features. Thus we move the arch feature detection to
run on the CPU. We cannot always read th
From: Jonathan Zhou
Add definitions for the Arm v8.4 SelfHosted trace extensions registers.
Acked-by: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Jonathan Zhou
[ split the register definitions to separate patch
rename some of the symbols ]
Signed-off-by: Suzuki K Poulose
---
arch/arm64
In preparation to detect the support for system instruction
support, move the detection of the device access to the target
CPU.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since v3
- Name constructs etm4_xx instead of etm_** (Mathieu)
---
.../coresi
As per the specification any update to the TRCPRGCTLR must be synchronized
by a context synchronization event (in our case an explicist ISB) before
the TRCSTATR is checked.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm
Align start and end on page boundaries before calling
invalidate_inode_pages2_range.
This might allow us to miss a collision if the write and the discard were done
to the same page and do overlap but it is still better than returning -EBUSY
if those writes didn't overlap.
Signed-off-by: Maxim Lev
Expose the TRCDEVARCH register via the sysfs for component
detection. Given that the TRCIDR1 may not completely identify
the ETM component and instead need to use TRCDEVARCH, expose
this via sysfs for tools to use it for identification.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by:
On Sun, Dec 20, 2020 at 03:39:22PM +, guo...@kernel.org wrote:
> +#define cmpxchg(ptr, o, n) \
> +({ \
> + __typeof__(*(ptr)) __ret; \
> + __smp_release_fence();
Document the bindings for ETMs with system register accesses.
Cc: devicet...@vger.kernel.org
Cc: Mathieu Poirier
Cc: Mike Leach
Acked-by: Rob Herring
Signed-off-by: Suzuki K Poulose
---
Documentation/devicetree/bindings/arm/coresight.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(
From: Jonathan Zhou
v8.4 tracing extensions added support for trace filtering controlled
by TRFCR_ELx. This must be programmed to allow tracing at EL1/EL2 and
EL0. The timestamp used is the virtual time. Also enable CONTEXIDR_EL2
tracing if we are running the kernel at EL2.
Cc: Catalin Marinas
Define the fields of the DEVARCH register for identifying
a component as an ETMv4.x unit. Going forward, we use the
DEVARCH register for the component identification, rather
than the TRCIDR3.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresigh
Convert the generic routines to use the new access abstraction layer
gradually, starting with coresigth_timeout.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since v4:
- Remove stacking of parameters in coresight.h
Changes since v3:
- Fix style : sta
Convert all register accesses from etm4x driver to use a wrapper
to allow switching the access at runtime with little overhead.
co-developed by sed tool ;-), mostly equivalent to :
s/readl\(_relaxed\)\?(drvdata->base + \(.*\))/etm4x_\1_read32(csdev, \2)
s/writel\(_relaxed\)\?(\(.*\), drvdata->bas
ETM architecture defines the system instructions for accessing
via register accesses. Add basic support for accessing a given
register via system instructions.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since v3:
- Removed stacking of parameters and
As we are about define a switch..case table for individual register
access by offset for implementing the system instruction support,
document the possible set of registers for each group to make
it easier to correlate.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
As we are about to add support for sysreg access to ETM4.4+ components,
make sure that we read the registers only on the host CPU.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-sysfs.c | 23 ---
1 file chan
The Software lock is not implemented for system instructions
based accesses. So, skip the lock register access in such
cases.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c | 40 ---
1 file changed,
On Thu, 2021-01-07 at 14:40 +0200, Maxim Levitsky wrote:
> Align start and end on page boundaries before calling
> invalidate_inode_pages2_range.
>
> This might allow us to miss a collision if the write and the discard were done
> to the same page and do overlap but it is still better than returni
On Thu, Jan 07, 2021 at 11:18:41AM +, Russell King - ARM Linux admin wrote:
> On Wed, Jan 06, 2021 at 10:32:23PM +, Russell King - ARM Linux admin
> wrote:
> > On Wed, Jan 06, 2021 at 05:20:34PM +, Will Deacon wrote:
> > > With that, I see the following after ten seconds or so:
> > >
On Sun, Dec 20, 2020 at 03:39:23PM +, guo...@kernel.org wrote:
> From: Guo Ren
>
> There are two implementation of spinlock in arch/csky:
> - simple one (NR_CPU = 1,2)
> - tick's one (NR_CPU = 3,4)
> Remove the simple one.
>
> There is already smp_mb in spinlock, so remove the definition o
On Wed, Jan 06, 2021 at 08:49:32PM +, Dexuan Cui wrote:
> > From: Michael Kelley
> > Sent: Wednesday, January 6, 2021 9:38 AM
> > From: Dexuan Cui
> > Sent: Tuesday, December 22, 2020 4:12 PM
> > >
> > > When a Linux VM runs on Hyper-V, if the host toolstack doesn't support
> > > hibernation
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