tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git rcu/test
branch HEAD: 88054dca0f5708bee190e093dce64dc3cb025793 ACPI: processor: Fix
missing need_resched() check after rcu_idle_enter()
Error/Warning ids grouped by kconfigs:
gcc_recent_errors
`-- nds32-randcon
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git
dev.2020.12.21a
branch HEAD: ceb57fe529baff777d89a46bff3580926b3186ef torture: Break affinity
of kthreads last running on outgoing CPU
elapsed time: 724m
configs tested: 138
configs skipped: 2
The following c
Symbol 'btf_vmlinux' was not declared in the header file and does not
add extern, so no other file uses it. It's better to add static to it.
Signed-off-by: YANG LI
Reported-by: Abaci
---
kernel/bpf/verifier.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/bpf/verifi
Hi,
* Pavel Machek [201220 22:48]:
> Hi!
>
> > Sorry about the late reply on this.
>
> I'm afraid I'll need some more answers in near future, but for now:
>
> Tony, do you remember / can you figure out what gsmtty GPS is on? I
> never used it on that interface, and I can't seem to figure it ou
Hi Leo,
On Wed, 23 Dec 2020 14:39:03 +0800
Leo Yan wrote:
> This patch is to enable SDT on Arm64.
>
> Since Arm64 SDT marker in ELF file is different from other archs,
> especially for using stack pointer (sp) to retrieve data for local
> variables, patch 01 is used to fixup the arguments for t
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 58cf05f597b03a8212d9ecf2c79ee046d3ee8ad9
commit: 2ac6795fcc085e8d03649f1bbd0d70aaff612cad clocksource/drivers: Add CLINT
timer driver
date: 4 months ago
config: riscv-randconfig-s031-20201221 (attached as
On Wed, 23 Dec 2020 17:17:27 -0600
Tom Zanussi wrote:
> Hi Masami,
>
> On Tue, 2020-12-22 at 21:42 +0900, Masami Hiramatsu wrote:
> > Hi Tom,
> >
> > On Mon, 21 Dec 2020 15:44:28 -0600
> > Tom Zanussi wrote:
> >
> >
> > > @@ -656,7 +651,6 @@ static struct synth_field
> > > *parse_synth_field
Hi Lee,
> From: Lee Jones, Sent: Thursday, December 24, 2020 4:34 PM
> > Hi Lee,
> >
> > > From: Lee Jones, Sent: Thursday, December 24, 2020 12:39 AM
> > > On Wed, 23 Dec 2020, Yoshihiro Shimoda wrote:
> > > > From: Khiem Nguyen
> > > > + switch (ret) {
> > > > + case BD9571MWV_PROD
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 58cf05f597b03a8212d9ecf2c79ee046d3ee8ad9
commit: 20f2ffe504728612d7b0c34e4f8280e34251e704 drm/amdgpu: fold
CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)
date: 7 weeks ago
config: powerpc-randconf
On Thu, Dec 24, 2020 at 04:11:17PM +0800, kernel test robot wrote:
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> master
> head: 58cf05f597b03a8212d9ecf2c79ee046d3ee8ad9
> commit: 2ac6795fcc085e8d03649f1bbd0d70aaff612cad clocksource/drivers: Add
> CLINT timer dri
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 58cf05f597b03a8212d9ecf2c79ee046d3ee8ad9
commit: 2ac6795fcc085e8d03649f1bbd0d70aaff612cad clocksource/drivers: Add CLINT
timer driver
date: 4 months ago
config: riscv-randconfig-s031-20201221 (attached as
On Mon, 2020-12-21 at 12:23 -0700, Rob Herring wrote:
> On Wed, Dec 16, 2020 at 05:30:10PM +0800, Chunfeng Yun wrote:
> > Convert mediatek,mtk-xhci.txt to YAML schema mediatek,mtk-xhci.yaml
> >
> > Signed-off-by: Chunfeng Yun
> > ---
> > v4: update it according to Rob's suggestion
> > 1. modify
Subject: Teo En Ming's Guide to Configuring Asterisk/FreePBX with Cisco
7960 IP Phones
Author: Mr. Turritopsis Dohrnii Teo En Ming (TARGETED INDIVIDUAL)
Country: Singapore
Date: 24 December 2020 Thursday Singapore Time
Type of Publication: Plain Text
Document version: 20201224.01
==
Add the callback functions of drm_driver structure member functions
load and unload, no need to call load in the hibmc_pci_probe function
and unload in the hibmc_pci_remove function.
v2:
remove the hibmc_unload called from hibmc_pic_remove.
Signed-off-by: Tian Tao
---
drivers/gpu/drm/hisilicon/
On Thu, 24 Dec 2020, Yoshihiro Shimoda wrote:
> Document other similar specification chip BD9574MWF.
>
> Signed-off-by: Yoshihiro Shimoda
> ---
> Documentation/devicetree/bindings/mfd/bd9571mwv.txt | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
For my own reference (apply this as-
Hello!
On 24.12.2020 10:04, Yoshihiro Shimoda wrote:
Use dev_regmap_add_irq_chip() to simplify the code.
devm_?
Signed-off-by: Yoshihiro Shimoda
Acked-for-MFD-by: Lee Jones
Reviewed-by: Matti Vaittinen
Reviewed-by: Geert Uytterhoeven
---
drivers/mfd/bd9571mwv.c | 27 ++-
On Thu, 24 Dec 2020, Yoshihiro Shimoda wrote:
> From: Khiem Nguyen
>
> Since the driver supports BD9571MWV PMIC only, this patch makes
> the functions and data structure become more generic so that
> it can support other PMIC variants as well. Also remove printing
> part name which Lee Jones sug
How do I account for the Linux kernel development team？
Hi Ard,
On Wed, Dec 23, 2020 at 11:43:45PM +0100, Ard Biesheuvel wrote:
> I hope this report is not holding up the PR for efi/core?
I was just looking at that yesterday...
But nah, lemme send it.
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
Hi Linus,
please pull the EFI updates for v5.11. They got delayed due to a last
minute ia64 build issue which got fixed in the meantime:
https://lkml.kernel.org/r/87o8iwdtbj@nanos.tec.linutronix.de
and now the lot is all clear.
Thx.
---
The following changes since commit 3650b228f83adda7e
On Thu, 24 Dec 2020 at 09:55, Borislav Petkov wrote:
>
> Hi Ard,
>
> On Wed, Dec 23, 2020 at 11:43:45PM +0100, Ard Biesheuvel wrote:
> > I hope this report is not holding up the PR for efi/core?
>
> I was just looking at that yesterday...
>
> But nah, lemme send it.
>
Cheers,
On Wed, 23 Dec 2020 at 13:07, Jagan Teki wrote:
>
> On Wed, Dec 23, 2020 at 5:29 PM Krzysztof Kozlowski wrote:
> >
> > On Wed, Dec 23, 2020 at 04:33:41PM +0530, Jagan Teki wrote:
> > > Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
> > > board.
> > >
> > > Genaral features:
> >
Hi,
Le Tue 22 Dec 20, 09:17, Jernej Škrabec a écrit :
> Dne petek, 18. december 2020 ob 20:50:33 CET je Paul Kocialkowski napisal(a):
> > This adds a device-tree definition for the CSI0 MCLK pin,
> > which can be used for feeding MIPI CSI-2 sensors.
> >
> > Signed-off-by: Paul Kocialkowski
>
>
Hi,
Le Tue 22 Dec 20, 09:21, Jernej Škrabec a écrit :
> Dne petek, 18. december 2020 ob 21:54:35 CET je Paul Kocialkowski napisal(a):
> > Introduce bindings description for the V3s PWM, which is
> > register-compatible with the A20 PWM.
> >
> > Signed-off-by: Paul Kocialkowski
>
> This is meant
On Wed, Dec 23, 2020 at 10:44 PM Matthew Wilcox wrote:
>
> On Wed, Dec 23, 2020 at 08:21:41PM +, Sargun Dhillon wrote:
> > On Wed, Dec 23, 2020 at 08:07:46PM +, Matthew Wilcox wrote:
> > > On Wed, Dec 23, 2020 at 07:29:41PM +, Sargun Dhillon wrote:
> > > > On Wed, Dec 23, 2020 at 06:50
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 58cf05f597b03a8212d9ecf2c79ee046d3ee8ad9
commit: 2ac6795fcc085e8d03649f1bbd0d70aaff612cad clocksource/drivers: Add CLINT
timer driver
date: 4 months ago
config: riscv-randconfig-s031-20201221 (attached as
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 58cf05f597b03a8212d9ecf2c79ee046d3ee8ad9
commit: 2ac6795fcc085e8d03649f1bbd0d70aaff612cad clocksource/drivers: Add CLINT
timer driver
date: 4 months ago
config: riscv-randconfig-s031-20201221 (attached as
>
> From: Bean Huo
>
> sprintf and snprintf may cause output defect in sysfs content, it is
> better to use new added sysfs_emit function which knows the size of the
> temporary buffer.
>
> Suggested-by: Greg Kroah-Hartman
> Signed-off-by: Bean Huo
Reviewed-by: Avri Altman
On 2020/12/24 15:52, Greg Kroah-Hartman wrote:
On Thu, Dec 24, 2020 at 09:11:53AM +0800, Chao Yu wrote:
Hi Greg,
Thanks a lot for helping to resend and merge the patch. :)
Not a problem, glad to help out. In the future, all you need to do is
give us the git commit id that needs to be backpor
On Wed, 2020-12-23 at 16:33 +0100, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 5.10.3 release.
> There are 40 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied,
> please
> let me know.
>
>
On Wed, Dec 23, 2020 at 01:42:43PM +, Timon Baetz wrote:
> Add maxim,max8997-battery and maxim,max8997-muic optional nodes.
>
> Signed-off-by: Timon Baetz
I already acked this, why did you skip my tag?
Best regards,
Krzysztof
> ---
> .../bindings/regulator/max8997-regulator.txt |
On Wed, Dec 23, 2020 at 9:01 AM Xie He wrote:
>
> I don't think this patch is suitable for stable branches. This patch is
> part of a patch series that changes the lapb module from "establishing the
> L2 connection only when needed by L3", to "establishing the L2 connection
> automatically wheneve
On Wed, Dec 23, 2020 at 01:43:05PM +, Timon Baetz wrote:
> Register for extcon notification and set charging current depending on
> the detected cable type. Current values are taken from vendor kernel,
> where most charger types end up setting 650mA [0].
>
> Also enable and disable the CHARGER
Hello,
syzbot found the following issue on:
HEAD commit:467f8165 Merge tag 'close-range-cloexec-unshare-v5.11' of ..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=12b7fccb50
kernel config: https://syzkaller.appspot.com/x/.config?x=37c889fb8b2761af
das
On Fri, Dec 4, 2020 at 2:38 PM Johan Hovold wrote:
>
> Hi Himadri,
>
> and sorry about the late feedback on this one. I'm still trying to dig
> myself out of some backlog.
>
> On Wed, Nov 04, 2020 at 12:16:48PM +0530, Himadri Pandya wrote:
> > There are many usages of usb_control_msg() that can us
We have encountered the following problems several times:
1、A raid slot or hardware problem causes block device loss.
2、Continue to issue IO requests to the problematic block device.
3、The system possibly crash after a few hours.
dmesg log as below:
[15205901.268313] blk_partition_rema
On Thu, Dec 24, 2020 at 2:48 PM Krzysztof Kozlowski wrote:
>
> On Wed, 23 Dec 2020 at 13:07, Jagan Teki wrote:
> >
> > On Wed, Dec 23, 2020 at 5:29 PM Krzysztof Kozlowski wrote:
> > >
> > > On Wed, Dec 23, 2020 at 04:33:41PM +0530, Jagan Teki wrote:
> > > > Engicam C.TOUCH 2.0 is an EDIMM compli
On Thu, Dec 24, 2020 at 11:32:55AM +0200, Amir Goldstein wrote:
> On Wed, Dec 23, 2020 at 10:44 PM Matthew Wilcox wrote:
> >
> > On Wed, Dec 23, 2020 at 08:21:41PM +, Sargun Dhillon wrote:
> > > On Wed, Dec 23, 2020 at 08:07:46PM +, Matthew Wilcox wrote:
> > > > On Wed, Dec 23, 2020 at 07:
On Tue, Dec 22, 2020 at 07:47:45PM +0800, Chao Yu wrote:
> On 2020/12/18 19:53, Satya Tangirala wrote:
> > On Fri, Dec 18, 2020 at 05:02:23PM +0800, Chao Yu wrote:
> > > But, what's the plan about supporting software encryption for metadata?
> > > Current
> > > f2fs write flow will handle all oper
> On Wed, 23 Dec 2020 20:38:33 +0800 Dinghao Liu wrote:
> > The error handling paths in enic_alloc_vnic_resources()
> > have called enic_free_vnic_resources() before returning.
> > So we may not need to call it again on failure at caller
> > side.
> >
> > Signed-off-by: Dinghao Liu
>
> But it's
On 12/09/2020 12:17 PM, Song Liu wrote:
Hi Matthew,
On Dec 8, 2020, at 7:46 PM, Matthew Ruffell
wrote:
Hello,
I recently backported the following patches into the Ubuntu stable kernels:
md: add md_submit_discard_bio() for submitting discard bio
md/raid10: extend r10bio devs to raid disks
On Thu, 24 Dec 2020 at 11:08, Jagan Teki wrote:
>
> On Thu, Dec 24, 2020 at 2:48 PM Krzysztof Kozlowski wrote:
> >
> > On Wed, 23 Dec 2020 at 13:07, Jagan Teki wrote:
> > >
> > > On Wed, Dec 23, 2020 at 5:29 PM Krzysztof Kozlowski
> > > wrote:
> > > >
> > > > On Wed, Dec 23, 2020 at 04:33:41PM
From: Quanyang Wang
In function _allocate_opp_table, opp_dev is allocated and referenced
by opp_table via _add_opp_dev. But in the case that the subsequent calls
return -EPROBE_DEFER, it will jump to err label and opp_table will be
freed. Then opp_dev becomes an unreferenced object to cause memor
Hi,
Just to clarify things:
> > Do you see any substantial benefit of having fWriteBoosterBufferFlushEn
> > disabled?
>
> 1. The definition of fWriteBoosterBufferFlushEn is that host allows
> device to do flush in anytime after fWriteBoosterBufferFlushEn is set as
> on. This is not what we want.
From: Leonid Ravich
to remove locking from nvmet_fc_find_target_queue
which called per IO.
Signed-off-by: Leonid Ravich
---
drivers/nvme/target/fc.c | 54
1 file changed, 32 insertions(+), 22 deletions(-)
diff --git a/drivers/nvme/target/fc.c b
From: Leonid Ravich
to remove locking from nvmet_fc_find_target_queue
which called per IO.
Signed-off-by: Leonid Ravich
---
drivers/nvme/target/fc.c | 54
1 file changed, 32 insertions(+), 22 deletions(-)
diff --git a/drivers/nvme/target/fc.c b
Roja Rani Yarubandi (3):
dt-bindings: power: Introduce 'assigned-performance-states' property
arm64: dts: sc7180: Add assigned-performance-states for i2c
i2c: i2c-qcom-geni: Add support for 'assigned-performance-states'
.../bindings/power/power-domain.yaml | 49 +++
For devices which have 'assigned-performance-states' specified in DT,
set the specified performance state during probe and drop it on remove.
Also drop/set as part of runtime suspend/resume callbacks.
Signed-off-by: Roja Rani Yarubandi
---
drivers/i2c/busses/i2c-qcom-geni.c | 49
While most devices within power-domains which support performance states,
scale the performance state dynamically, some devices might want to
set a static/default performance state while the device is active.
These devices typically would also run off a fixed clock and not support
dynamically scali
Hello, Mandeep, Guenter et al.
I came across the out-of-tree patch [1] that apparently is still alive
after 10 years of residing in the Chromium OS tree, and I have a couple
of questions if you don't mind spending your time answering them.
1. is this knob really necessary given there's an explici
qup-i2c devices on sc7180 are clocked with a fixed clock (19.2 MHz).
Though qup-i2c does not support DVFS, it still needs to vote for a
performance state on 'CX' to satisfy the 19.2 MHz clock frequency
requirement.
Use 'assigned-performance-states' to pass this information from
device tree, and al
There is a deadlock in bm_register_write:
First, in the beggining of the function, a lock is taken on the
binfmt_misc root inode with inode_lock(d_inode(root))
Then, if the user used the MISC_FMT_OPEN_FILE flag, the function will
call open_exec on the user-provided interpreter.
open_exec will call
Invoke wiz_init() before configuring anything else in Sierra/Torrent
(invoked as part of of_platform_device_create()). wiz_init() resets the
SERDES device and any configuration done in the probe() of
Sierra/Torrent will be lost. In order to prevent SERDES configuration
from getting reset, invoke wi
Add binding for the PLLs within SERDES.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/phy-cadence-sierra.yaml | 89 ++-
1 file changed, 86 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
b/Documentation/
Cadence Sierra PHY driver registers PHY using devm_phy_create()
for all sub-nodes of Sierra device tree node. However Sierra device
tree node can have sub-nodes for the various clocks in addtion to the
PHY. Use devm_phy_create() only for nodes with name "phy" (or "link"
for old device tree) which r
"serdes" node (child node of WIZ) can have sub-nodes for representing links
or it can have sub-nodes for representing the various clocks within the
serdes. Instead of trying to read "reg" from every child node used for
assigning "lane_phy_type", read only if the child node's name is "phy"
or "link"
No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 36
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/dri
Add DT nodes for clocks within Sierra SERDES.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 128 --
1 file changed, 120 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
b/arch/arm64/boot/dts/ti/k3-j
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk and refrcv. Model PLL_CMNLC and PLL_CMNLC1 as
clocks so that it's possible to select one of these two inputs from
device tree.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-caden
Patch series adds support in Sierra driver to use external clock.
v1 of the patch series can be found @ [1]
v2 of the patch series can be found @ [2]
Changes from v2:
1) Add depends on COMMON_CLK in Sierra
2) Add modelling PLL_CMNLC and PLL_CMNLC1 as clocks into a separate
patch
3) Disable clocks
Commit 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
de-asserts PHY_RESET even before the configurations are loaded in
phy_init(). However PHY_RESET should be de-asserted only after
all the configurations has been initialized, instead of de-asserting
in probe. Fix it here.
Fixes: 44d30
Sierra has two reference recievers REFRCV and REFRCV1. REFRCV is used to
drive reference clock cmn_refclk_m/p to PLL_CMNLC1 and REFRCV1 is used to
drive reference clock cmn_refclk1_m/p to PLL_CMNLC. Model these
reference receivers as clocks in order for PLL_CMNLC and PLL_CMNLC1 to
be able to seamle
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them.
This will enable REFRCV/1 in case the pll_cmnlc/1 takes input
from REFRCV/1 respectively.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 55 insertions(
No functional change. Since the reset controls obtained in
Sierra is exclusively used by the Sierra device, use
exclusive reset control request API calls.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Rename the external refclk inputs to the SERDES from
dummy_cmn_refclk/dummy_cmn_refclk1 to cmn_refclk/cmn_refclk1
respectively. Also move the external refclk DT nodes outside the
cbass_main DT node. Since in j721e common processor board, only the
cmn_refclk1 is connected to 100MHz clock, fix the cl
No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra
Use external clock for all the SERDES used by PCIe controller. This will
make the same clock used by the local SERDES as well as the clock
provided to the PCIe connector.
Signed-off-by: Kishon Vijay Abraham I
---
.../dts/ti/k3-j721e-common-proc-board.dts | 45 +++
1 file chan
Commit 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board:
Configure the PCIe instances") and
commit 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed
support for USB0") added PHY DT nodes with node name as "link"
However nodes with #phy-cells should be named 'phy' as discussed i
Since gpiolib requires having separate irqchips for each gpiochip, we
need to add some we definetly need a separate one for F port, and we
could combine gpiochip A and B into one - but this will break namespace
and logick.
So despite 3 irqchips is a bit beefy we need a separate irqchip for each
in
On Wed, Dec 23, 2020 at 02:23:15PM -0800, Tim Harvey wrote:
> Add bindings for the Gateworks Venice Development kit boards with
> IMX8MM System on Module.
>
> Signed-off-by: Tim Harvey
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --g
As ->to_irq is redefined in gpiochip_add_irqchip, having it defined in
driver is useless, so let's drop it.
Also i think it is worth to give a gentle warning in
gpiochip_add_irqchip, to prevent people relying on to_irq.
For example
WARN_ON_ONCE(gc->to_irq,
"to_irq is redefined in gpiochip_add_ir
I was lucky enough to became an owner of some splendid piece's of
antiques called ts7250 based on the top of Cirrus Logic EP9302.
I don't know what fate expects this hardware (it's not EOL it's just Not
recommended for new designs) but i wanted to share fixes in ep93xx gpio area.
It seems ep93xx
On Wed, 23 Dec 2020 15:32:07 +, Lee Jones wrote:
> On Wed, 23 Dec 2020, Timon Baetz wrote:
>
> > Add of_compatible ("maxim,max8997-muic") to the mfd_cell to have a
> > of_node set in the extcon driver.
> >
> > Add of_compatible ("maxim,max8997-battery") to the mfd_cell to configure
> > the cha
Adds bitrate control for all coding layers for h264
same as hevc.
Signed-off-by: Dikshita Agarwal
---
.../userspace-api/media/v4l/ext-ctrls-codec.rst | 20
drivers/media/v4l2-core/v4l2-ctrls.c | 7 +++
include/uapi/linux/v4l2-controls.h
- Adds min/max qp controls for B frame for h264.
- Adds min/max qp controls for I/P/B frames for hevc similar to h264.
- Update valid range of min/max qp for hevc to accommodate 10 bit.
Signed-off-by: Dikshita Agarwal
---
.../userspace-api/media/v4l/ext-ctrls-codec.rst| 52 ++
Add support for frame type specific min and max qp controls
for encoder.
This is a preparation patch to support v6.
Signed-off-by: Dikshita Agarwal
---
drivers/media/platform/qcom/venus/core.h | 18
drivers/media/platform/qcom/venus/venc.c | 21 +++--
drivers/media/platform/qc
On Wed, 2020-12-23 at 17:15 +0900, Tomasz Figa wrote:
> Hi Yong,
>
> On Wed, Dec 09, 2020 at 04:00:39PM +0800, Yong Wu wrote:
> > In the latest SoC, there are several HW IP require a sepecial iova
> > range, mainly CCU and VPU has this requirement. Take CCU as a example,
> > CCU require its iova l
This series adds frame specific min/max qp controls for hevc and layer
wise bitrate control for h264.
Chnages since v2:
- Rebased the changes on latest media tree
- Added driver side implementation for new controls.
Dikshita Agarwal (3):
media: v4l2-ctrl: Add frame-specific min/max qp control
On Wed, 2020-12-23 at 08:51 +, Christoph Hellwig wrote:
> On Wed, Dec 16, 2020 at 06:36:01PM +0800, Yong Wu wrote:
> > In the end of __iommu_map, It alway call iotlb_sync_map.
> > This patch moves iotlb_sync_map out from __iommu_map since it is
> > unnecessary to call this for each sg segment e
Port F irq's should be statically mapped to EP93XX_GPIO_F_IRQ_BASE.
So we need to specify girq->first otherwise:
"If device tree is used, then first_irq will be 0 and
irqs get mapped dynamically on the fly"
And that's not the thing we want.
Signed-off-by: Nikita Shubin
---
drivers/gpio/gpio-e
ALARM_EN status is retained in PMIC register after device shutdown
if poweron_alarm is enabled. Read it to make sure the driver has
consistent value with the register status.
Signed-off-by: Guixiong Wei
---
drivers/rtc/rtc-pm8xxx.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/dri
I realized I didn't update fscrypt_mergeable_bio() to take metadata
encryption into account, so bios will be more fragmented than required.
I'll fix it in v3.
On Wed, 2020-12-23 at 17:18 +0900, Tomasz Figa wrote:
> On Wed, Dec 09, 2020 at 04:00:41PM +0800, Yong Wu wrote:
> > This patch adds decriptions for mt8192 IOMMU and SMI.
> >
> > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
> > table format. The M4U-SMI HW diagram is a
On Wed, Dec 23, 2020 at 02:23:16PM -0800, Tim Harvey wrote:
> The Gateworks Venice GW71xx-0x/GW72xx-0x/GW73xx-0x are development
> kits comprised of a GW700x SoM and a Baseboard.
>
> The GW700x SoM contains:
> - IMX8MM SoC
It's i.MX 8M Mini.
https://www.nxp.com/products/processors-and-microcontr
Add bindings for AM64 SERDES Wrapper.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
b/Documentation/devic
cmn_refclk_ lines in Torrent SERDES is used for connecting external
reference clock. cmn_refclk_ can also be configured to output the
reference clock. In order to drive the refclk out from the SERDES
(Cadence Torrent), PHY_EN_REFCLK should be set in SERDES_RST of WIZ.
Model PHY_EN_REFCLK as a clock
Add binding for refclk driver used to route the refclk out of the
SERDES.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/phy-cadence-torrent.yaml | 17 +
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yam
The frequency of the txmclk between PCIe and SERDES has
changed to 250MHz from 500MHz. Configure full rate divider
for AM64 accordingly.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 43 +++---
1 file changed, 40 insertions(+), 3 deletions
Add DT binding for phy_en_refclk used to route the refclk out of the
SERDES.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 13 +
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yam
cmn_refclk_ lines in Torrent SERDES is used for connecting external
reference clock. cmn_refclk_ can also be configured to output the
reference clock. Model this derived reference clock as a "clock" so that
platforms like AM642 EVM can enable it.
This is used by PCIe to use the same refclk both in
AM64 has a single lane SERDES which can be configured to be used
with either PCIe or USB. Define the possilbe values for the SERDES
function in AM64 SoC here.
Signed-off-by: Kishon Vijay Abraham I
---
include/dt-bindings/mux/ti-serdes.h | 4
1 file changed, 4 insertions(+)
diff --git a/inc
AM64 uses the same SERDES as in J7200, however AM642 EVM doesn't
have a clock generator (unlike J7200 base board). Here the clock from
the SERDES has to be routed to the PCIE connector. This series adds
support to drive reference clock output from SERDES and also adds
SERDES (torrent) and SERDES wr
On Wed, 25 Nov 2020, Sumera Priyadarsini wrote:
> The command "make coccicheck C=1 CHECK=scripts/coccicheck" results in the
> error:
> ./scripts/coccicheck: line 65: -1: shift count out of range
>
> This happens because every time the C variable is specified,
> the shell arguments need
AM64 uses the same PCIe controller as in J7200, however AM642 EVM
doesn't have a clock generator (unlike J7200 base board). Here
the clock from the SERDES has to be routed to the PCIE connector.
This series provides an option for the pci-j721e.c driver to
drive reference clock output to the connect
Add binding to represent refclk to the PCIe connector.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/pci/ti,j721e-pci-host.yaml | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
b/
Add endpoint mode dt-bindings for TI's AM64 SoC. This is the same IP
used in J7200, however AM64 is a non-coherent architecture.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff
Add host mode dt-bindings for TI's AM64 SoC. This is the same IP used in
J7200, however AM64 is a non-coherent architecture.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --g
Add support to provide refclk to PCIe connector.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pci-j721e.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c
b/drivers/pci/controller/cadence/pci-j721e.c
in
On Thu, 2020-12-24 at 11:03 +, Avri Altman wrote:
> > > Do you see any substantial benefit of having
> > > fWriteBoosterBufferFlushEn
> > > disabled?
> >
> > 1. The definition of fWriteBoosterBufferFlushEn is that host allows
> > device to do flush in anytime after fWriteBoosterBufferFlushEn i
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index fd6ae5464dea..e7eb2c9f37af 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/a
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