Hi Rafael,
On Mon, Dec 14, 2020 at 09:23:47PM +0100, Rafael J. Wysocki wrote:
> Hi,
>
> This series addresses some enumeration ordering issues by using information
> from _DEP to defer the enumeration of devices that are likely to depend on
> operation region (OpRegion) handlers supplied by the d
Add "jz4780_core1_disable()" for disable the second core of JZ4780,
prepare for later commits.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v1->v2:
Add Paul Cercueil's Reviewed-by.
v2->v3:
No change.
drivers/clk/ingenic/jz4780-cgu.c | 21
X1000 and X1830 have two MAC related clocks, one is MACPHY, which is
controlled by MACCDR register, the other is MAC, which is controlled
by the MAC bit in the CLKGR register (with CLK_AHB2 as the parent).
The original driver mistakenly mixed the two clocks together.
Signed-off-by: 周琰杰 (Zhou Yanji
From: zhuling
bpf/seccomp: modify hardcode 2 to SECCOMP_MODE_FILTER
while the hardcode 2 has been define in seccomp_bpf.c, we should use
the definitions(SECCOMP_MODE_FILTER) instead of hardcode 2.
Signed-off-by: zhuling
---
samples/bpf/tracex5_user.c | 2 +-
samples/seccomp/dropper.c
This is a major cleanup of the paravirt infrastructure aiming at
eliminating all custom code patching via paravirt patching.
This is achieved by using ALTERNATIVE instead, leading to the ability
to give objtool access to the patched in instructions.
In order to remove most of the 32-bit special h
SWAPGS is used only for interrupts coming from user mode or for
returning to user mode. So there is no reason to use the PARAVIRT
framework, as it can easily be replaced by an ALTERNATIVE depending
on X86_FEATURE_XENPV.
There are several instances using the PV-aware SWAPGS macro in paths
which are
Xen PV guests don't use IST. For double fault interrupts switch to
the same model as NMI.
Correct a typo in a comment while copying it.
Signed-off-by: Juergen Gross
Acked-by: Peter Zijlstra (Intel)
Reviewed-by: Thomas Gleixner
---
V2:
- fix typo (Andy Lutomirski)
---
arch/x86/include/asm/idte
Xen PV guests don't use IST. For machine check interrupts switch to
the same model as debug interrupts.
Signed-off-by: Juergen Gross
Acked-by: Peter Zijlstra (Intel)
Reviewed-by: Thomas Gleixner
---
arch/x86/include/asm/idtentry.h | 3 +++
arch/x86/xen/enlighten_pv.c | 16 +++-
Instead of using paravirt patching for custom code sequences add
support for using ALTERNATIVE handling combined with paravirt call
patching.
Signed-off-by: Juergen Gross
---
V3:
- drop PVOP_ALT_VCALL() macro
---
arch/x86/include/asm/paravirt_types.h | 49 +++
1 file
Instead of only supporting to modify instructions when a specific
feature is set, support doing so for the case a feature is not set.
As today a feature is specified using a 16 bit quantity and the highest
feature number in use is around 600, using a negated feature number for
specifying the inver
The central pvops call macros PVOP_CALL() and PVOP_VCALL() are
looking very similar now.
The main differences are using PVOP_VCALL_ARGS or PVOP_CALL_ARGS, which
are identical, and the return value handling.
So drop PVOP_VCALL_ARGS and instead of PVOP_VCALL() just use
(void)PVOP_CA
There is no need any longer to have different paravirt patch functions
for native and Xen. Eliminate native_patch() and rename
paravirt_patch_default() to paravirt_patch().
Signed-off-by: Juergen Gross
---
V3:
- remove paravirt_patch_insns() (kernel test robot)
---
arch/x86/include/asm/paravirt_
From: Peter Zijlstra
Alternatives pose an interesting problem for unwinders because from
the unwinders PoV we're just executing instructions, it has no idea
the text is modified, nor any way of retrieving what with.
Therefore the stance has been that alternatives must not change stack
state, as
For being able to switch paravirt patching from special cased custom
code sequences to ALTERNATIVE handling some X86_FEATURE_* are needed
as new features. This enables to have the standard indirect pv call
as the default code and to patch that with the non-Xen custom code
sequence via ALTERNATIVE p
USERGS_SYSRET64 is used to return from a syscall via sysret, but
a Xen PV guest will nevertheless use the iret hypercall, as there
is no sysret PV hypercall defined.
So instead of testing all the prerequisites for doing a sysret and
then mangling the stack for Xen PV again for doing an iret just u
The time pvops functions are the only ones left which might be
used in 32-bit mode and which return a 64-bit value.
Switch them to use the static_call() mechanism instead of pvops, as
this allows quite some simplification of the pvops implementation.
Due to include hell this requires to split out
"popf" is a rather expensive operation, so don't use it for restoring
irq flags. Instead test whether interrupts are enabled in the flags
parameter and enable interrupts via "sti" in that case.
This results in the restore_fl paravirt op to be no longer needed.
Suggested-by: Andy Lutomirski
Signe
Instead of using paravirt patching for custom code sequences use
ALTERNATIVE for the functions with custom code replacements.
Instead of patching an ud2 instruction for unpopulated vector entries
into the caller site, use a simple function just calling BUG() as a
replacement.
Signed-off-by: Juerg
PVOP_VCALL4() is only used for Xen PV, while PVOP_CALL4() isn't used
at all. Keep PVOP_CALL4() for 64 bits due to symmetry reasons.
This allows to remove the 32-bit definitions of those macros leading
to a substantial simplification of the paravirt macros, as those were
the only ones needing non-e
The iret paravirt op is rather special as it is using a jmp instead
of a call instruction. Switch it to ALTERNATIVE.
Signed-off-by: Juergen Gross
---
V3:
- use ALTERNATIVE_TERNARY
---
arch/x86/include/asm/paravirt.h | 6 +++---
arch/x86/include/asm/paravirt_types.h | 5 +
arch/x86/ke
On Thu, 17 Dec 2020 17:15:47 +0100,
Robin Gong wrote:
>
> Since mmap for userspace is based on page alignment, add page alignment
> for iram alloc from pool, otherwise, some good data located in the same
> page of dmab->area maybe touched wrongly by userspace like pulseaudio.
>
> Signed-off-by: R
On Wed, 2020-12-16 at 08:53 +, Lee Jones wrote:
> On Fri, 04 Dec 2020, Matti Vaittinen wrote:
>
> > Add BD71827 driver header. For a record - Header is originally
> > based on work authored by Cong Pham although not much of original
> > work is left now.
> >
> > Signed-off-by: Matti Vaittine
On Thu, Dec 17, 2020 at 3:28 AM Stephen Rothwell wrote:
>
> Hi all,
>
> On Mon, 14 Dec 2020 20:21:07 +1100 Stephen Rothwell
> wrote:
> >
> > Today's linux-next merge of the akpm-current tree got a conflict in:
> >
> > lib/Makefile
> >
> > between commit:
> >
> > 527701eda5f1 ("lib: Add a gen
> -Original Message-
> From: Jakub Kicinski
> Sent: Thursday, December 17, 2020 2:42 AM
> To: Stefan Chulski
> Cc: net...@vger.kernel.org; thomas.petazz...@bootlin.com;
> da...@davemloft.net; Nadav Haklai ; Yan Markman
> ; linux-kernel@vger.kernel.org;
> li...@armlinux.org.uk; m...@semi
From: Stefan Chulski
During GoP port 2 Networking Complex Control mode of operation configurations,
also GoP port 3 mode of operation was wrongly set.
Patch removes these configurations.
GENCONF_CTRL0_PORTX naming also fixed.
Fixes: f84bf386f395 ("net: mvpp2: initialize the GoP")
Signed-off-by:
From: Stefan Chulski
Force link UP can be enabled by bootloader during tftpboot
and breaks NFS support.
Force link UP disabled during port init procedure.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 14 +-
1 file changed, 13 insertions(+), 1
On Wed, 16 Dec 2020 19:29:09 +0100,
Amadej Kastelic wrote:
>
> On Wed, Dec 16, 2020 at 04:38:07PM +0100, Takashi Iwai wrote:
> > On Tue, 15 Dec 2020 19:09:05 +0100,
> > Amadej Kastelic wrote:
> > >
> > > Message-Id:
> > >
> > > Add VID to support native DSD reproduction on FiiO devices.
> > >
On 12/17/20 5:15 PM, Robin Gong wrote:
Since mmap for userspace is based on page alignment, add page alignment
for iram alloc from pool, otherwise, some good data located in the same
page of dmab->area maybe touched wrongly by userspace like pulseaudio.
I wonder, do we also have to align size to
Quoting Dmitry Osipenko (2020-11-15 12:34:32)
> Add "hardware enable" column to the clk summary in order to show actual
> hardware enable-state of all clocks. The possible states are "Y/N/?",
> where question mark means that state is unknown, i.e. clock isn't a
> mux and clk-driver doesn't support
This series implements Runtime PM support for the Tegra ChipIdea USB driver.
It also squashes the older ehci-tegra driver into the ChipIdea driver, hence
the RPM is supported by both UDC and host controllers, secondly this opens
opportunity for implementing OTG support in the future.
Patchset was
The OF core adds an alias based on the OF device ID table, which is enough
to have the driver autoloaded. The legacy MODULE_ALIAS macro was relevant
to a pre-OF board files which manually created platform devices, this is
irrelevant to the modern ARM kernels since devices are created by the OF
core
The ehci-tegra driver was superseded by the generic ChipIdea USB driver,
update the tegra's defconfig accordingly.
Signed-off-by: Dmitry Osipenko
---
arch/arm/configs/tegra_defconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm
The PHY hardware needs the delay of 2ms after power up, otherwise initial
interrupt may be lost if USB controller is accessed before PHY is settled
down. Previously this issue was masked by implicit delays, but now it pops
up after squashing the older ehci-tegra driver into the ChipIdea driver.
Te
On Thu, Dec 17, 2020 at 10:28 AM Calvin Johnson
wrote:
> On Tue, Dec 15, 2020 at 07:28:10PM +0200, Andy Shevchenko wrote:
> > On Tue, Dec 15, 2020 at 6:44 PM Calvin Johnson
> > wrote:
...
> > > + if (sscanf(cp, "ethernet-phy-id%4x.%4x", &upper, &lower) == 2) {
> >*phy_id = ((uppe
Support programming of waking up from a low power mode by implementing the
generic set_wakeup() callback of the USB PHY API.
Tested-by: Matt Merhar
Tested-by: Nicolas Chauvet
Tested-by: Peter Geis
Tested-by: Ion Agorria
Signed-off-by: Dmitry Osipenko
---
drivers/usb/phy/phy-tegra-usb.c | 9
Rename all occurrences in the code from "udc" to "usb" and change the
Kconfig entry in order to show that this driver supports USB modes other
than device-only mode. The follow up patch will add host-mode support and
it will be cleaner to perform the renaming separately, i.e. in this patch.
Tested
From: Peter Geis
Add USB host mode to the Tegra HDRC driver. This allows us to benefit from
support provided by the generic ChipIdea driver instead of duplicating the
effort in a separate ehci-tegra driver.
Tested-by: Matt Merhar
Tested-by: Nicolas Chauvet
Tested-by: Ion Agorria
Signed-off-by
The ChipIdea driver now provides USB2 host mode support for NVIDIA Tegra
SoCs. The ehci-tegra driver is obsolete now, remove it and redirect the
older Kconfig entry to the CI driver.
Tested-by: Matt Merhar
Tested-by: Nicolas Chauvet
Tested-by: Peter Geis
Tested-by: Ion Agorria
Signed-off-by: D
Hi Alex,
On 12/2/20 7:34 AM, Alexandre Courbot wrote:
> DRC events can happen virtually at anytime, including when we are
> starting a seek. Should this happen, we must make sure to return to the
> DRC state, otherwise the firmware will expect buffers of the new
> resolution whereas userspace wil
Tegra PHY driver now supports waking up controller from a low power mode.
Enable runtime PM in order to put controller into the LPM during idle.
Tested-by: Matt Merhar
Tested-by: Nicolas Chauvet
Tested-by: Peter Geis
Tested-by: Ion Agorria
Signed-off-by: Dmitry Osipenko
---
drivers/usb/chipi
Quoting Zheng Yongjun (2020-12-16 05:05:34)
> The parameter of kfree function is NULL, so kfree code is useless, delete it.
Not always though. Sometimes it is non-NULL and this code avoids a goto.
>
> Signed-off-by: Zheng Yongjun
> ---
> drivers/clk/ti/fapll.c | 1 -
> 1 file changed, 1 deleti
On 16/12/20 10:16 pm, Bean Huo wrote:
> On Wed, 2020-12-16 at 20:51 +0200, Adrian Hunter wrote:
>> ufshcd_variant_hba_exit(hba);
>> ufshcd_setup_vreg(hba, false);
>> ufshcd_suspend_clkscaling(hba);
>> @@ -9436,6 +9441,20 @@ int ufshcd_init(struct ufs_
Quoting Alexandru Ardelean (2020-12-02 23:40:36)
> Up until the these limits were global/hard-coded, since they are typically
> limits of the fabric.
>
> However, since this is an FPGA generated clock, this may run on setups
> where one clock is on a fabric, and another one synthesized on another
Quoting Alexandru Ardelean (2020-10-13 07:34:20)
> This change converts the old binding for the AXI clkgen driver to a yaml
> format.
>
> As maintainers, added:
> - Lars-Peter Clausen - as original author of driver &
>binding
> - Michael Hennerich - as supporter of
>Analog Devices driv
Quoting Alexandru Ardelean (2020-12-02 23:40:37)
> The change is mostly cosmetic. No functional changes.
> Since the driver now uses of_device_get_match_data() to obtain some driver
> specific info, there is no need to define the OF table before the probe
> function.
>
> Signed-off-by: Alexandru A
Hi Stephen,
Thanks for the review.
On Thu, Dec 17, 2020 at 10:09 AM Stephen Boyd wrote:
>
> Quoting Sergio Paracuellos (2020-11-22 01:55:53)
> > The documentation for this SOC only talks about two
> > registers regarding to the clocks:
> > * SYSC_REG_CPLL_CLKCFG0 - provides some information abou
Le 17/12/2020 à 07:11, Alexei Starovoitov a écrit :
On Wed, Dec 16, 2020 at 10:07:37AM +, Christophe Leroy wrote:
Implement Extended Berkeley Packet Filter on Powerpc 32
Test result with test_bpf module:
test_bpf: Summary: 378 PASSED, 0 FAILED, [354/366 JIT'ed]
nice!
Registe
On Thu, 17 Dec 2020 10:43:45 +0100,
Lars-Peter Clausen wrote:
>
> On 12/17/20 5:15 PM, Robin Gong wrote:
> > Since mmap for userspace is based on page alignment, add page alignment
> > for iram alloc from pool, otherwise, some good data located in the same
> > page of dmab->area maybe touched wron
On Thu 17-12-20 00:49:35, Al Viro wrote:
> [Christoph added to Cc...]
> On Wed, Dec 16, 2020 at 06:31:47PM -0500, Vivek Goyal wrote:
> > Current implementation of __sync_filesystem() ignores the return code
> > from ->sync_fs(). I am not sure why that's the case. There must have
> > been some histo
On Mon, Dec 14, 2020 at 9:41 PM Uwe Kleine-König
wrote:
> Technically there are still some maintainers' ack missing but I'd really
> like to get this series applied. As I don't want to make people angry
> I'm asking once more for your Acks.
Acked-by: Linus Walleij
Sorry for taking so long, it
Hi Stephen,
Thanks for the review!
On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd wrote:
>
> Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> > Adds device tree binding documentation for clocks in the
> > MT7621 SOC.
> >
> > Signed-off-by: Sergio Paracuellos
> > ---
> > .../bindings/clock/medi
On Wed, Dec 16, 2020 at 5:16 PM Paul E. McKenney wrote:
>
> On Wed, Dec 16, 2020 at 10:52:06AM +0100, Daniel Vetter wrote:
> > On Wed, Dec 16, 2020 at 2:14 AM syzbot
> > wrote:
> > >
> > > Hello,
> > >
> > > syzbot found the following issue on:
> > >
> > > HEAD commit:94801e5c Merge tag 'pinc
Hi deee Ho Lee,
On Wed, 2020-12-02 at 15:32 +0200, Matti Vaittinen wrote:
> Hello Lee,
>
> On Wed, 2020-12-02 at 12:57 +, Lee Jones wrote:
> > On Fri, 27 Nov 2020, Vaittinen, Matti wrote:
> >
> > > Hello Lee,
> > >
> > > On Fri, 2020-11-27 at 08:32 +, Lee Jones wrote:
> > > > On Mon, 23
Hi Andy,
On Thu, 17 Dec 2020 11:40:51 +0200 Andy Shevchenko
wrote:
>
> Yeah, and it's slightly different. Perhaps RISC-V tree can handle this
> by moving Makefile entry somewhere else in the file.
Or just let Linus take care of it ...
--
Cheers,
Stephen Rothwell
pgprUxnfVtQtO.pgp
Descriptio
On Thu, Dec 17, 2020 at 9:40 AM Jiaying Liang wrote:
>
>
> On 12/15/20 7:23 AM, Alex Deucher wrote:
> > On Mon, Dec 14, 2020 at 7:24 PM Jiaying Liang
> > wrote:
> >> On 12/11/20 11:39 AM, Daniel Vetter wrote:
> >>> Hi all
> >>>
> >>> On Fri, Dec 11, 2020 at 8:03 PM Alex Deucher
> >>> wrote:
>
On 16.12.20 21:42, Liam R. Howlett wrote:
>
> Thank you for looking at this. I appreciate the scrutiny.
>
> * David Hildenbrand [201216 09:58]:
>> On 15.12.20 16:54, Liam R. Howlett wrote:
>>> do_mmap() will unlock the necessary VMAs. There is also a bug in the
>>> loop which will evaluate as
Hi,
This series adds some DRM bridge drivers support for i.MX8qm/qxp SoCs.
The bridges may chain one by one to form display pipes to support
LVDS displays. The relevant display controller is DPU embedded in
i.MX8qm/qxp SoCs.
The DPU KMS driver can be found at:
https://www.spinics.net/lists/arm-
This patch adds RGB666_1X30_CPADLO, RGB888_1X30_CPADLO, RGB666_1X36_CPADLO
and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp pixel combiner.
The RGB pixels with padding low per component are transmitted on a 30-bit
input bus(10-bit per component) from a display controller or a 36-bit
output bu
This patch allows LVDS PHYs to be configured through
the generic functions and through a custom structure
added to the generic union.
The parameters added here are based on common LVDS PHY
implementation practices. The set of parameters
should cover all potential users.
Cc: Kishon Vijay Abraham
This patch adds bindings for i.MX8qm/qxp pixel combiner.
Signed-off-by: Liu Ying
---
.../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 160 +
1 file changed, 160 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.
This patch adds a drm bridge driver for i.MX8qm/qxp pixel combiner.
The pixel combiner takes two output streams from a single display
controller and manipulates the two streams to support a number
of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured
as either one screen, two scre
This patch adds documentations for RGB666_1X30_CPADLO, RGB888_1X30_CPADLO,
RGB666_1X36_CPADLO and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp
pixel combiner. The RGB pixels with padding low per component are
transmitted on a 30-bit input bus(10-bit per component) from a display
controller o
This patch adds bindings for i.MX8qxp pixel link to DPI(PXL2DPI).
Signed-off-by: Liu Ying
---
.../display/bridge/fsl,imx8qxp-pxl2dpi.yaml| 134 +
1 file changed, 134 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dp
This patch adds a drm bridge driver for i.MX8qxp pixel link to display
pixel interface(PXL2DPI). The PXL2DPI interfaces the pixel link 36-bit
data output and the DSI controller’s MIPI-DPI 24-bit data input, and
inputs of LVDS Display Bridge(LDB) module used in LVDS mode, to remap
the pixel color c
This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link.
The pixel link forms a standard asynchronous linkage between
pixel sources(display controller or camera module) and pixel
consumers(imaging or displays). It consists of two distinct
functions, a pixel transfer function and a c
This patch adds a helper to support LDB drm bridge drivers for
i.MX SoCs. Helper functions exported from this driver should
implement common logics for all LDB modules embedded in i.MX SoCs.
Signed-off-by: Liu Ying
---
drivers/gpu/drm/bridge/imx/Kconfig | 8 +
drivers/gpu/drm/bridge/
This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).
Signed-off-by: Liu Ying
---
.../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 185 +
1 file changed, 185 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.y
This patch adds a drm bridge driver for i.MX8qxp LVDS display bridge(LDB).
The LDB has two channels. Each of them supports up to 24bpp parallel
input color format and can map the input to VESA or JEIDA standards.
The two channels cannot be used simultaneously, that is to say, the user
should pick
This patch adds bindings for i.MX8qm/qxp display pixel link.
Signed-off-by: Liu Ying
---
.../display/bridge/fsl,imx8qxp-pixel-link.yaml | 128 +
1 file changed, 128 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.
Add myself as the maintainer of DRM bridge drivers for i.MX SoCs.
Signed-off-by: Liu Ying
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7b073c4..4b4e40e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5846,6 +5846,16 @@ F: Do
This patch adds a drm bridge driver for i.MX8qm LVDS display bridge(LDB).
The LDB has two channels. Each of them supports up to 30bpp parallel
input color format and can map the input to VESA or JEIDA standards.
The two channels can be used simultaneously, either in dual mode or
split mode. In du
Hello,
syzbot found the following issue on:
HEAD commit:accefff5 Merge tag 'arm-soc-omap-genpd-5.11' of git://git...
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=14567b7f50
kernel config: https://syzkaller.appspot.com/x/.config?x=1e6efc730c219bd4
das
On Thu, Dec 17, 2020 at 11:07 AM Stephen Boyd wrote:
>
> Quoting Sergio Paracuellos (2020-12-17 02:01:39)
> >
> > On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd wrote:
> > >
> > > Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/
Not sure why this wasn't picked up in the samsung PR. Can you resend?
> diff --git a/drivers/clk/samsung/clk-exynos7.c
> b/drivers/clk/samsung/clk-exynos7.c
> index c1ff715e960c..1048d83f097b 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -538,7 +5
On 09/12/2020 at 14:03, Claudiu Beznea wrote:
Hi,
This series adds support for SAMA7G5 Ethernet interfaces: one 10/100Mbps
and one 1Gbps interfaces.
Along with it I also included a fix to disable clocks for SiFive FU540-C000
on failure path of fu540_c000_clk_init().
Thank you,
Claudiu Beznea
On Thu, 17 Dec 2020 10:55:42 +0100,
Takashi Iwai wrote:
>
> On Thu, 17 Dec 2020 10:43:45 +0100,
> Lars-Peter Clausen wrote:
> >
> > On 12/17/20 5:15 PM, Robin Gong wrote:
> > > Since mmap for userspace is based on page alignment, add page alignment
> > > for iram alloc from pool, otherwise, some
On Thu, 2020-12-17 at 16:54 +0800, Fox Chen wrote:
> On Thu, Dec 17, 2020 at 12:46 PM Ian Kent wrote:
> > On Tue, 2020-12-15 at 20:59 +0800, Ian Kent wrote:
> > > On Tue, 2020-12-15 at 16:33 +0800, Fox Chen wrote:
> > > > On Mon, Dec 14, 2020 at 9:30 PM Ian Kent
> > > > wrote:
> > > > > On Mon, 2
Hello Chang,
On Wed, 16 Dec 2020 at 18:47, Chang S. Bae wrote:
>
> Key Locker (KL) is Intel's new security feature that protects the AES key
> at the time of data transformation. New AES SIMD instructions -- as a
> successor of Intel's AES-NI -- are provided to encode an AES key and
> reference i
Hi Mathieu
For google reference design(mt8183+it6505), the maximum 95000kHz is depends on
mt8183 requirement.
-Original Message-
From: Mathieu Tournier [mailto:mathieutourn...@gmail.com]
Sent: Thursday, December 17, 2020 2:47 AM
To: Allen Chen (陳柏宇)
Cc: Jau-Chih Tseng (曾昭智); Kenneth Hun
On Thu, Dec 17, 2020 at 6:42 AM Vijayanand Jitta wrote:
>
> On 12/16/2020 7:04 PM, Alexander Potapenko wrote:
> >>> To reiterate, I think you don't need a tunable stack_hash_order
> >>> parameter if the only use case is to disable the stack depot.
> >>> Maybe it is enough to just add a boolean fla
On Thu, Dec 17, 2020 at 11:12 AM Stephen Boyd wrote:
>
> Quoting Sergio Paracuellos (2020-12-17 01:54:18)
> >
> > On Thu, Dec 17, 2020 at 10:09 AM Stephen Boyd wrote:
> > >
> > > Quoting Sergio Paracuellos (2020-11-22 01:55:53)
> > > > diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink
On Mon, 14 Dec 2020, Will McVicker wrote:
> > The HID subsystem allows an "HID report field" to have a different
> > number of "values" and "usages" when it is allocated. When a field
> > struct is created, the size of the usage array is guaranteed to be at
> > least as large as the values array,
On Thu, Dec 10, 2020 at 6:04 AM wrote:
>
> From: Yogesh Lal
>
> Add a kernel parameter stack_hash_order to configure STACK_HASH_SIZE.
>
> Aim is to have configurable value for STACK_HASH_SIZE, so that one
> can configure it depending on usecase there by reducing the static
> memory overhead.
>
>
Quoting Zhen Lei (2020-12-06 20:55:27)
> Eliminate the following yamllint warnings:
> ./Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml
> :32:13:[warning] wrong indentation: expected 14 but found 12 (indentation)
> :35:9: [warning] wrong indentation: expected 10 but found 8 (indentation)
On Thu, Dec 17, 2020 at 11:25 AM Dmitry Vyukov wrote:
>
> On Thu, Dec 10, 2020 at 6:04 AM wrote:
> >
> > From: Yogesh Lal
> >
> > Add a kernel parameter stack_hash_order to configure STACK_HASH_SIZE.
> >
> > Aim is to have configurable value for STACK_HASH_SIZE, so that one
> > can configure it
On Tue, 2020-12-15 at 19:28 +0800, Kuan-Ying Lee wrote:
> When cpu is going offline, set q->offline as true
> and interrupt happened. The interrupt may call the
> quarantine_put. But quarantine_put do not free the
> the object. The object will cause memory leak.
>
> Add qlink_free() to free the ob
On Sun, Dec 13, 2020 at 11:45:34PM +0800, Muchun Song wrote:
> static inline unsigned int free_vmemmap_pages_per_hpage(struct hstate *h)
> {
> - return h->nr_free_vmemmap_pages;
> + return h->nr_free_vmemmap_pages && is_power_of_2(sizeof(struct page));
This is wrong as it will return eit
Quoting Sergio Paracuellos (2020-12-17 02:14:10)
> On Thu, Dec 17, 2020 at 11:07 AM Stephen Boyd wrote:
> >
> > Quoting Sergio Paracuellos (2020-12-17 02:01:39)
> > >
> > > On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd wrote:
> > > >
> > > > Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> > > >
Quoting Liu Ying (2020-12-01 21:33:35)
> This patch set adds some SCU clocks support for i.MX8qxp DC0/MIPI-LVDS
> subsystems.
>
> With this patch set, some basic clocks for i.MX8qxp LVDS displays can be got
> by drivers.
>
> v1->v2:
> * Drop LPCG clocks as they can be registered directly in an in
On Thu, Dec 17, 2020 at 11:14 AM syzbot
wrote:
>
> Hello,
>
> syzbot found the following issue on:
>
> HEAD commit:accefff5 Merge tag 'arm-soc-omap-genpd-5.11' of git://git...
> git tree: upstream
> console output: https://syzkaller.appspot.com/x/log.txt?x=14567b7f50
> kernel config:
On Thu, Dec 17, 2020 at 11:32 AM Stephen Boyd wrote:
>
> Quoting Sergio Paracuellos (2020-12-17 02:14:10)
> > On Thu, Dec 17, 2020 at 11:07 AM Stephen Boyd wrote:
> > >
> > > Quoting Sergio Paracuellos (2020-12-17 02:01:39)
> > > >
> > > > On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd wrote:
> >
On 16/12/20 18:26, Reinette Chatre wrote:
> Hi Valentin,
>> So that's part paranoia and part nonsense from my end - the contents of
>> smp_call() shouldn't matter here.
>>
>> If we distill the code to:
>>
>>tsk->closid = x;
>>
>>if (task_curr(tsk))
>>smp_call(...);
>>
>> It is som
On Sun, Dec 13, 2020 at 7:38 PM Adam Ford wrote:
> The Bluetooth chip is capable of operating at 4Mbps, but the
> max-speed setting was on the UART node instead of the Bluetooth
> node, so the chip didn't operate at the correct speed resulting
> in choppy audio. Fix this by setting the max-speed
On Sun, Dec 13, 2020 at 7:38 PM Adam Ford wrote:
> VSPI0 and VSPB are already enabled by default. There is no need
> to add extra nodes to enable them. Remove the redundant nodes.
>
> Signed-off-by: Adam Ford
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.12.
Gr{oetj
This change tries to address an issue, when BIOS disabled turbo
but HWP_CAP guaranteed is changed later and user space wants to take
advantage of this increased guaranteed performance.
The HWP_CAP.GUARANTEED value is not a static value. It can be changed
by some out of band agent or during Intel S
On Thu, Dec 17, 2020 at 6:32 PM Oscar Salvador wrote:
>
> On Sun, Dec 13, 2020 at 11:45:34PM +0800, Muchun Song wrote:
> > static inline unsigned int free_vmemmap_pages_per_hpage(struct hstate *h)
> > {
> > - return h->nr_free_vmemmap_pages;
> > + return h->nr_free_vmemmap_pages && is_po
On 12/17/20 11:14 AM, Takashi Iwai wrote:
On Thu, 17 Dec 2020 10:55:42 +0100,
Takashi Iwai wrote:
On Thu, 17 Dec 2020 10:43:45 +0100,
Lars-Peter Clausen wrote:
On 12/17/20 5:15 PM, Robin Gong wrote:
Since mmap for userspace is based on page alignment, add page alignment
for iram alloc from poo
On Wed, Dec 16, 2020 at 02:01:58PM -0600, Josh Poimboeuf wrote:
> So this is kind of tricky, because the unreachable() annotation usually
> means "the previous instruction is a dead end". Most of the time, the
> next instruction -- the one actually pointed to by the annotation -- is
> actually rea
On Wed, Dec 16, 2020 at 01:19:31PM -0800, Paul E. McKenney wrote:
> Given that there is no optimization potential, then the main reason to use
> data_race() instead of *_ONCE() is to prevent KCSAN from considering the
> accesses when looking for data races. But that is mostly for debugging
> acces
Hi Paul,
Thanks for your inputs.
On Wed, 16 Dec 2020 at 21:33, Paul E. McKenney wrote:
>
> On Wed, Dec 16, 2020 at 03:40:04PM +0530, Naresh Kamboju wrote:
> > Linux Kernel Functional Testing (LKFT) started running rcu-torture tests on
> > qemu_arm64, qemu_arm qemu_x86_64 and qemu_i386 from our C
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