This driver uses SPI-MEM framework and is capable to operate with
single, dual, quad and octal SPI-NOR memories.
Low-level controller work mode (STIG) is utilized to communicate
with flash memories.
Signed-off-by: Jayshri Pawar
Signed-off-by: Konrad Kociolek
---
drivers/spi/Kconfig|
Command processing
Driver uses STIG work mode to communicate with flash memories.
In this mode, controller sends low-level instructions to memory.
Each instruction is 128-bit width. There is special instruction
DataSequence which carries information about data phase.
Driver uses Slave DMA interface
Alex,
I had to revise the patch. Please see attachment. It is actually two more SSIDs
affected to that.
Best regards,
Edgar
-Original Message-
From: Merger, Edgar [AUTOSOL/MAS/AUGS]
Sent: Dienstag, 8. Dezember 2020 09:23
To: 'Deucher, Alexander' ; 'Huang, Ray'
; 'Kuehling, Felix'
Cc:
Add dt-bindings documentation for Cadence XSPI controller
to support SPI based flash memories.
Signed-off-by: Jayshri Pawar
Signed-off-by: Konrad Kociolek
---
.../devicetree/bindings/spi/cdns,xspi.yaml | 164 +
1 file changed, 164 insertions(+)
create mode 100644 Do
On Tue, Dec 08, 2020 at 09:01:49PM -0800, Joe Perches wrote:
> On Tue, 2020-12-08 at 16:34 -0800, Kees Cook wrote:
>
> > If not "Adjusted-by", what about "Tweaked-by", "Helped-by",
> > "Corrected-by"?
>
> Improved-by: / Enhanced-by: / Revisions-by:
>
I don't think we should give any credit for
This patch mainly adds support for mt8192 Multimedia IOMMU and SMI.
mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
table format. The M4U-SMI HW diagram is as below:
EMI
|
M4U
Convert MediaTek IOMMU to DT schema.
Signed-off-by: Yong Wu
Reviewed-by: Rob Herring
---
.../bindings/iommu/mediatek,iommu.txt | 105 ---
.../bindings/iommu/mediatek,iommu.yaml| 167 ++
2 files changed, 167 insertions(+), 105 deletions(-)
delete mode 100
Aspeed AST2600 is a server management SoC which has 16 PWM channels and
16 fan tacho channel.
This series of patch provides AST2600 PWM/Fan tacho support in hwmon class.
The driver provides a sysfs interface, and user can configure PWM duty cycle
and read current FAN speed in RPM.
Troy Lee (4):
Only rename the header guard for all the SoC larb port header file.
No funtional change.
Suggested-by: Krzysztof Kozlowski
Signed-off-by: Yong Wu
---
include/dt-bindings/memory/mt2701-larb-port.h | 4 ++--
include/dt-bindings/memory/mt2712-larb-port.h | 4 ++--
include/dt-bindings/memory/mt6779
This patch adds decriptions for mt8192 IOMMU and SMI.
mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
table format. The M4U-SMI HW diagram is as below:
EMI
|
M4U
|
On 2020-12-09 15:09, Ziqi Chen wrote:
As per specs, e.g, JESD220E chapter 7.2, while powering
off/on the ufs device, RST_N signal and REF_CLK signal
should be between VSS(Ground) and VCCQ/VCCQ2.
Power down:
1. Assert RST_N low
2. Turn-off REF_CLK
3. Turn-off VCC
4. Turn-off VCCQ/VCCQ2.
power on:
MediaTek extend the bit5 in lvl1 and lvl2 descriptor as PA34.
Signed-off-by: Yong Wu
Acked-by: Will Deacon
Reviewed-by: Robin Murphy
---
drivers/iommu/io-pgtable-arm-v7s.c | 9 +++--
drivers/iommu/mtk_iommu.c | 2 +-
include/linux/io-pgtable.h | 4 ++--
3 files changed, 10
The current _ARM_V7S_LVL_BITS/ARM_V7S_LVL_SHIFT use a formula to calculate
the corresponding value for level1 and level2 to pretend the code sane.
Actually their level1 and level2 values are different from each other.
This patch only clarify the two macro. No functional change.
Suggested-by: Robin
Add "cfg" as a parameter for some macros. This is a preparing patch for
mediatek extend the lvl1 pgtable. No functional change.
Signed-off-by: Yong Wu
Acked-by: Will Deacon
Reviewed-by: Robin Murphy
---
drivers/iommu/io-pgtable-arm-v7s.c | 36 +++---
1 file changed, 18
Add a HW flag for if the HW support 34bit IOVA. the previous SoC
still use 32bit. normally the lvl1 pgtable size is 16KB when ias == 32.
if ias == 34, lvl1 pgtable size is 16KB * 4. The purpose of this patch
is to save 16KB*3 continuous memory for the previous SoC.
Signed-off-by: Yong Wu
---
dri
This patch adds pm runtime callback.
In pm runtime case, all the registers backup/restore and bclk are
controlled in the pm_runtime callback, then pm_suspend is not needed in
this case.
runtime PM is disabled when suspend, thus we call
pm_runtime_status_suspended instead of pm_runtime_suspended.
In the lastest SoC, M4U has its special power domain. thus, If the engine
begin to work, it should help enable the power for M4U firstly.
Currently if the engine work, it always enable the power/clocks for
smi-larbs/smi-common. This patch adds device_link for smi-common and M4U.
then, if smi-common
For multiple iommu_domains, we need to reserve some iova regions. Take a
example, If the default iova region is 0 ~ 4G, but the 0x4000_ ~
0x43ff_ is only for the special CCU0 domain. Thus we should exclude
this region for the default iova region.
This patch adds iova reserved flow. It's a
After extending v7s, our pagetable already support iova reach
16GB(34bit). the master got the iova via dma_alloc_attrs may reach
34bits, but its HW register still is 32bit. then how to set the
bit32/bit33 iova? this depend on a SMI larb setting(bank_sel).
we separate whole 16GB iova to four banks:
Hi,
On Sat, 5 Dec 2020 08:04:25 +0100
"H. Nikolaus Schaller" wrote:
> Hi Linus,
>
> > Am 05.12.2020 um 01:25 schrieb Linus Walleij :
> >
> > On Fri, Dec 4, 2020 at 5:52 PM H. Nikolaus Schaller
> > wrote:
> >
> >> But what I don't know is if I can omit spi-cs-high and have to keep
> >> ACT
I am the author of MediaTek iommu driver, and will to maintain and
develop it further.
Add myself to cover these items.
Signed-off-by: Yong Wu
Reviewed-by: Chun-Kuang Hu
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e73636b75f29..46
In attach device, it will update the pagetable base address register.
Move the hw_init function also here. Then it only need call
pm_runtime_get/put one time here if m4u has power domain.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 10 ++
1 file changed, 6 insertions(+), 4 del
Add mt8192 iommu support.
For multi domain, Add 1M gap for the vdec domain size. That is because
vdec HW has a end address register which require (start_addr +
len) rather than (start_addr + len - 1). Take a example, if the start_addr
is 0xfff0, size is 0x10, then the end_address is 0xfff0
From: Martin KaFai Lau
Date: Tue, 8 Dec 2020 19:09:03 -0800
> On Tue, Dec 08, 2020 at 05:17:48PM +0900, Kuniyuki Iwashima wrote:
> > From: Martin KaFai Lau
> > Date: Mon, 7 Dec 2020 23:34:41 -0800
> > > On Tue, Dec 08, 2020 at 03:31:34PM +0900, Kuniyuki Iwashima wrote:
> > > > From: Mar
Add "struct mtk_iommu_data *" in the "struct mtk_iommu_domain",
reduce the call mtk_iommu_get_m4u_data().
No functional change.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b
On Wed, Dec 09, 2020 at 08:58:46AM +0200, Eli Cohen wrote:
> On Wed, Dec 09, 2020 at 01:46:22AM -0500, Michael S. Tsirkin wrote:
> > On Wed, Dec 09, 2020 at 08:02:30AM +0200, Eli Cohen wrote:
> > > On Tue, Dec 08, 2020 at 04:45:04PM -0500, Michael S. Tsirkin wrote:
> > > > On Sun, Dec 06, 2020 at 1
Add fail handle for iommu_device_sysfs_add and iommu_device_register.
Fixes: b16c0170b53c ("iommu/mediatek: Make use of iommu_device_register
interface")
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drive
If the iova is over 32bit, the fault status register bit is a little
different.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 164479e1f5c5..ed
In the previous SoC, the M4U HW is in the EMI power domain which is
always on. the latest M4U is in the display power domain which may be
turned on/off, thus we have to add pm_runtime interface for it.
When the engine work, the engine always enable the power and clocks for
smi-larb/smi-common, the
Defaultly the iova range is 0-4G. here we add a single-domain(0-4G)
for the previous SoC. this also is a preparing patch for supporting
multi-domains.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.
Some HW IP(ex: CCU) require the special iova range. That means the
iova got from dma_alloc_attrs for that devices must locate in his
special range. In this patch, we allocate a special iova_range for
each a special requirement and create each a iommu domain for each
a iova_range.
meanwhile we stil
If the iova is 34bit, the iova[32][33] is the bit0/1 in the tlb flush
register. Add a new macro for this.
there is a minor change unrelated with this patch. it also use the new
macro.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 11 +++
1 file changed, 7 insertions(+), 4 delet
Use the common larb-port header in the source code.
Signed-off-by: Yong Wu
Acked-by: Krzysztof Kozlowski
---
drivers/iommu/mtk_iommu.c | 7 ---
drivers/iommu/mtk_iommu.h | 1 +
drivers/memory/mtk-smi.c | 1 +
include/soc/mediatek/smi.h | 2 --
4 files changed, 2 insertions(+), 9 deletio
The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
(4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
34bit.
Signed-off-by: Yong Wu
Reviewed-by: Robin Murphy
---
drivers/iommu/io-pgtable-arm-v7s.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
Add Aspeed AST2600 PWM/Fan tacho driver. AST2600 has 16 PWM channel and
16 FAN tacho channel.
Signed-off-by: Troy Lee
---
drivers/hwmon/Kconfig| 10 +
drivers/hwmon/Makefile |1 +
drivers/hwmon/aspeed2600-pwm-tacho.c | 1053 ++
3 files
Use the ias for the valid iova checking in arm_v7s_unmap. This is a
preparing patch for supporting iova 34bit for MediaTek.
Signed-off-by: Yong Wu
Reviewed-by: Robin Murphy
---
drivers/iommu/io-pgtable-arm-v7s.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/i
On Wed, Dec 09, 2020 at 05:34:19AM +0900, Sergey Senozhatsky wrote:
> On (20/12/04 10:12), Petr Mladek wrote:
> > On Tue 2020-12-01 21:59:40, John Ogness wrote:
> > > Currently @clear_seq access is protected by @logbuf_lock. Once
> > > @logbuf_lock is removed some other form of synchronization will
This stopped happening a while ago, let's close this to get
notifications about new instances.
One of likely candidates:
#syz fix: net: partially revert dynamic lockdep key changes
Put all the macros about smi larb/port togethers, this is a preparing
patch for extending LARB_NR and adding new dom-id support.
Signed-off-by: Yong Wu
Acked-by: Rob Herring
Acked-by: Krzysztof Kozlowski
---
include/dt-bindings/memory/mt2712-larb-port.h | 2 +-
include/dt-bindings/memory/mt6
In the latest SoC, there are several HW IP require a sepecial iova
range, mainly CCU and VPU has this requirement. Take CCU as a example,
CCU require its iova locate in the range(0x4000_ ~ 0x43ff_).
In this patch we add a domain definition for the special port. In the
example of CCU, If we
On Sun, Oct 27, 2019 at 4:31 AM syzbot
wrote:
>
> Hello,
>
> syzbot found the following crash on:
>
> HEAD commit:65921376 Merge branch 'net-fix-nested-device-bugs'
> git tree: net
> console output: https://syzkaller.appspot.com/x/log.txt?x=1637fdc0e0
> kernel config: https://syzkal
Create a common node in aspeed-g6.dtsi and add fan nodes for ast2600-evb
dts file.
Signed-off-by: Troy Lee
---
arch/arm/boot/dts/aspeed-ast2600-evb.dts | 149 +++
arch/arm/boot/dts/aspeed-g6.dtsi | 10 ++
2 files changed, 159 insertions(+)
diff --git a/arch/arm/boot
Extend the max larb number definition as mt8192 has larb_nr over 16.
Signed-off-by: Yong Wu
Acked-by: Rob Herring
Acked-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml | 2 +-
include/dt-bindings/memory/mtk-smi-larb-port.h | 4 ++--
2 files
For supporting a new AST2600 PWM/Fan hwmon driver, we add a new binding.
Signed-off-by: Troy Lee
---
.../bindings/hwmon/aspeed2600-pwm-tacho.txt | 69 +++
1 file changed, 69 insertions(+)
create mode 100644
Documentation/devicetree/bindings/hwmon/aspeed2600-pwm-tacho.txt
dif
Updating index.rst and adding aspeed_pwm_tachometer.rst to address the
driver.
Signed-off-by: Troy Lee
---
Documentation/hwmon/aspeed_pwm_tachometer.rst | 24 +++
Documentation/hwmon/index.rst | 1 +
2 files changed, 25 insertions(+)
create mode 100644 Documenta
From: Peng Fan
Not sure whether this is correct fix for aarch64 build, just a try.
I still need to drop -Werror to make it build, but not included in this
patchset.
Peng Fan (3):
tools/virtio: include asm/bug.h
tools/virtio: add krealloc_array
tools/virtio: add barrier for aarch64
tools/
From: Peng Fan
krealloc_array is used in drivers/vhost/vringh.c, add it to avoid build
failure.
Drop WARN_ON_ONCE, because duplicated with the one in bug.h
Signed-off-by: Peng Fan
---
tools/virtio/linux/kernel.h | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git
From: Peng Fan
Add barrier for aarch64 for cross compiling, and most are from Linux Kernel.
Signed-off-by: Peng Fan
---
tools/virtio/asm/barrier.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/tools/virtio/asm/barrier.h b/tools/virtio/asm/barrier.h
index 04d563fc9b95..468435
Le mercredi 09 déc. 2020 à 14:24:04 (+0800), Aubrey Li a écrit :
> Add idle cpumask to track idle cpus in sched domain. Every time
> a CPU enters idle, the CPU is set in idle cpumask to be a wakeup
> target. And if the CPU is not in idle, the CPU is cleared in idle
> cpumask during scheduler tick t
From: Peng Fan
WARN_ON is used in drivers/vhost/vringh.c, to avoid build failure,
need include asm/bug.h
Signed-off-by: Peng Fan
---
tools/virtio/linux/bug.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tools/virtio/linux/bug.h b/tools/virtio/linux/bug.h
index b14c2c3b6b85..813baf13f6
1. When the x25 module gets loaded, layer 2 may already be running and
connected. In this case, although we are in X25_LINK_STATE_0, we still
need to handle the Restart Request received, rather than ignore it.
2. When we are in X25_LINK_STATE_2, we have already sent a Restart Request
and is waitin
On Tue, Dec 08, 2020 at 11:36:44PM +0106, John Ogness wrote:
> For the state variable we chose atomic_long_t instead of atomic64_t for
> this reason. atomic_long_t operations are available atomically on all
> architectures.
Please put on your eye cancer gear and inspect the atomic implementation
o
Your two new exports don't actually seem to get used in modular code
at all in this series.
On 2020/12/7 7:12, Linus Walleij wrote:
Hi Luo!
thanks for your patch! I see that Andy already provided a crowd
of comments, here are some more!
On Wed, Dec 2, 2020 at 10:32 AM Luo Jiaxing wrote:
+config GPIO_HISI
+ tristate "HISILICON GPIO controller driver"
+ depends on (ARM6
On 12/09, Chao Yu wrote:
> On 2020/12/9 12:28, Chao Yu wrote:
> > On 2020/12/9 11:54, Jaegeuk Kim wrote:
> > > Ah, could you please write another patch to adjust the new changes?
> >
> > No problem, will drop "f2fs: compress:support chksum" based on your dev
> > branch, and
> > apply all compress
Hi Can,
On Tue, 2020-12-08 at 22:58 -0800, Can Guo wrote:
> ufshcd_hba_exit() is always called after ufshcd_exit_clk_scaling() and
> ufshcd_exit_clk_gating(), so no need to suspend clock scaling again in
> ufshcd_hba_exit().
>
> Signed-off-by: Can Guo
> ---
> drivers/scsi/ufs/ufshcd.c | 5 +
On 12/09, Chao Yu wrote:
> On 2020/12/3 14:56, Daeho Jeong wrote:
> > From: Daeho Jeong
> > + f2fs_balance_fs(F2FS_I_SB(inode), true);
>
> Trivial cleanup:
>
> f2fs_balance_fs(sbi, true);
>
> > + f2fs_balance_fs(F2FS_I_SB(inode), true);
>
> Ditto,
>
> Jaegeuk could fix this directly?
Let
On Wed, 09 Dec 2020 05:57:30 +0100,
Chris Chiu wrote:
>
> The ASUS laptop Q524UQK with ALC255 codec can't detect the headset
> microphone until ALC255_FIXUP_ASUS_MIC_NO_PRESENCE quirk applied.
>
> Signed-off-by: Chris Chiu
> Signed-off-by: Jian-Hong Pan
Applied now. Thanks.
Takashi
On 12/8/20 8:30 PM, Florent Revest wrote:
On Fri, 2020-12-04 at 20:03 +0100, Daniel Borkmann wrote:
On 12/4/20 7:56 PM, Daniel Borkmann wrote:
On 12/3/20 10:33 PM, Florent Revest wrote:
This creates a new helper proto because the existing
bpf_get_socket_cookie_sock_proto has a ARG_PTR_TO_CTX a
On Tue, Dec 08, 2020 at 11:01:50PM +0200, Vasyl Vavrychuk wrote:
> From: Mathias Crombez
> Cc: sta...@vger.kernel.org
I don't believe this is appropriate for stable, looks like
a new feature to me.
>
> Without multi-touch slots allocated, ABS_MT_SLOT events will be lost by
> input_handle_abs_e
On 2020-12-09 16:22, Stanley Chu wrote:
Hi Can,
On Tue, 2020-12-08 at 22:58 -0800, Can Guo wrote:
ufshcd_hba_exit() is always called after ufshcd_exit_clk_scaling() and
ufshcd_exit_clk_gating(), so no need to suspend clock scaling again in
ufshcd_hba_exit().
Signed-off-by: Can Guo
---
driver
pci_set_mwi() and pci_try_set_mwi() do exactly the same, just that the
former one is declared as __must_check. However also some callers of
pci_set_mwi() have a comment that it's an optional feature. I don't
think there's much sense in this separation and the use of
__must_check. Therefore remove p
On Tue, 08 Dec 2020 22:25:43 +0100,
Connor McAdams wrote:
>
> +static void chipio_8051_write_exram(struct hda_codec *codec,
> + unsigned int addr, unsigned int data, bool use_mutex)
> +{
> + struct ca0132_spec *spec = codec->spec;
> + unsigned int tmp;
> +
> + if (use_mutex
On Tue, 2020-12-01 at 14:35 -0800, mgr...@linux.intel.com wrote:
> Refactor the too large IOCTL function to call helper functions.
[]
> diff --git a/drivers/misc/xlink-core/xlink-ioctl.c
> b/drivers/misc/xlink-core/xlink-ioctl.c
[]
> +int ioctl_write_data(unsigned long arg)
> +{
> + struct xli
On 2020/12/9 16:23, Jaegeuk Kim wrote:
On 12/09, Chao Yu wrote:
On 2020/12/9 12:28, Chao Yu wrote:
On 2020/12/9 11:54, Jaegeuk Kim wrote:
Ah, could you please write another patch to adjust the new changes?
No problem, will drop "f2fs: compress:support chksum" based on your dev branch,
and
a
On Thu, Dec 03, 2020 at 11:48:56AM +, Pavel Begunkov wrote:
> It's inlined and the on-stack iter is completely optimised out. Frankly,
> I'd rather not open-code bvec_iter_advance(), at least for this chunk to
> be findable from bvec.h, e.g. grep bvec_iter and bvec_for_each. Though,
> I don't l
* Gautham R Shenoy [2020-12-08 22:55:40]:
> >
> > NIT:
> > tglx mentions in one of his recent comments to try keep a reverse fir tree
> > ordering of variables where possible.
>
> I suppose you mean moving the longer local variable declarations to to
> the top and shorter ones to the bottom. Th
Ok, seems like the patches made it to the lists, while oyu only
send the cover letter to my address which is very strange.
> diff --git a/include/linux/uio.h b/include/linux/uio.h
> index 72d88566694e..af626eb970cf 100644
> --- a/include/linux/uio.h
> +++ b/include/linux/uio.h
> @@ -18,6 +18,8 @@
On Sat, Dec 5, 2020 at 8:07 AM H. Nikolaus Schaller wrote:
> I find it interesting that so far nobody wants to take responsibility
> for a decision
(...)
What causes some consternation in this discussion is the appeal
to higher authority. The kernel community in general does not like
authority/r
* Gautham R Shenoy [2020-12-08 23:26:47]:
> > The drawback of this is even if cpus 0,2,4,6 are released L1 cache will not
> > be released. Is this as expected?
>
> cacheinfo populates the cache->shared_cpu_map on the basis of which
> CPUs share the common device-tree node for a particular cache.
Heiner Kallweit writes:
> pci_set_mwi() and pci_try_set_mwi() do exactly the same, just that the
> former one is declared as __must_check. However also some callers of
> pci_set_mwi() have a comment that it's an optional feature. I don't
> think there's much sense in this separation and the use o
> + /*
> + * In practice groups of pages tend to be accessed/reclaimed/refaulted
> + * together. To not go over bvec for those who didn't set BIO_WORKINGSET
> + * approximate it by looking at the first page and inducing it to the
> + * whole bio
> + */
> + if (unlik
Added support for Xilinx ZynqMP pinctrl driver support and
also updated the Xilinx firmware driver to support pinctrl
functionality.
This driver will query the pin information from the firmware
and allow configuring the pins as per the request.
Sai Krishna Potthuri (3):
firmware: xilinx: Added p
Add pinctrl support to query platform specific information (pins)
from firmware.
Signed-off-by: Sai Krishna Potthuri
---
drivers/firmware/xilinx/zynqmp.c | 114 +++
include/linux/firmware/xlnx-zynqmp.h | 90 +
2 files changed, 204 insertions(+)
d
Added pinctrl driver for Xilinx ZynqMP platform.
This driver queries pin information from firmware and registers
pin control accordingly.
Signed-off-by: Sai Krishna Potthuri
---
drivers/pinctrl/Kconfig | 13 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/pinctrl-zynqmp.c
Added documentation and dt-bindings file which contains MIO pin
configuration defines for Xilinx ZynqMP pinctrl driver.
Signed-off-by: Sai Krishna Potthuri
---
.../bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml | 329 ++
include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 29 ++
2 files
On 2020/12/9 16:31, Chao Yu wrote:
On 2020/12/9 16:23, Jaegeuk Kim wrote:
On 12/09, Chao Yu wrote:
On 2020/12/9 12:28, Chao Yu wrote:
On 2020/12/9 11:54, Jaegeuk Kim wrote:
Ah, could you please write another patch to adjust the new changes?
No problem, will drop "f2fs: compress:support chks
On Wed, Dec 9, 2020 at 6:51 AM Chunyan Zhang wrote:
> EIC controller have unfixed numbers of banks on different Spreadtrum SoCs,
> and each bank has its own base address, the loop of getting there base
> address in driver should break if the resource gotten via
> platform_get_resource() is NULL a
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: 758c9373d84168dc7d039cf85a0e920046b17b41
Gitweb:
https://git.kernel.org/tip/758c9373d84168dc7d039cf85a0e920046b17b41
Author:Andy Lutomirski
AuthorDate:Thu, 03 Dec 2020 21:07:05 -08:00
Commit
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: 2ecedd7569080fd05c1a457e8af2165afecfa29f
Gitweb:
https://git.kernel.org/tip/2ecedd7569080fd05c1a457e8af2165afecfa29f
Author:Andy Lutomirski
AuthorDate:Thu, 03 Dec 2020 21:07:04 -08:00
Commit
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: e45cdc71d1fa5ac3a57b23acc31eb959e4f60135
Gitweb:
https://git.kernel.org/tip/e45cdc71d1fa5ac3a57b23acc31eb959e4f60135
Author:Andy Lutomirski
AuthorDate:Thu, 03 Dec 2020 21:07:06 -08:00
Commit
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: a493d1ca1a03b532871f1da27f8dbda2b28b04c4
Gitweb:
https://git.kernel.org/tip/a493d1ca1a03b532871f1da27f8dbda2b28b04c4
Author:Andy Lutomirski
AuthorDate:Thu, 03 Dec 2020 21:07:03 -08:00
Commit
Hi Andreas,
> Am 09.12.2020 um 09:04 schrieb Andreas Kemnade :
>
> Hi,
>
> On Sat, 5 Dec 2020 08:04:25 +0100
> "H. Nikolaus Schaller" wrote:
>
>> Hi Linus,
>>
>>> Am 05.12.2020 um 01:25 schrieb Linus Walleij :
>>>
>>> On Fri, Dec 4, 2020 at 5:52 PM H. Nikolaus Schaller
>>> wrote:
>>>
Expand 'compress_algorithm' mount option to accept parameter as format of
:, by this way, it gives a way to allow user to do more
specified config on lz4 and zstd compression level, then f2fs compression
can provide higher compress ratio.
In order to set compress level for lz4 algorithm, it needs
Add a new directory 'stat' in path of /sys/fs/f2fs//, later
we can add new readonly stat sysfs file into this directory, it will
make directory less mess.
Signed-off-by: Chao Yu
---
fs/f2fs/f2fs.h | 5 +++-
fs/f2fs/sysfs.c | 69 +
2 files change
Support to use address space of inner inode to cache compressed block,
in order to improve cache hit ratio of random read.
Signed-off-by: Chao Yu
---
Documentation/filesystems/f2fs.rst | 3 +
fs/f2fs/compress.c | 198 +++--
fs/f2fs/data.c
If kernel doesn't support certain kinds of compress algorithm, deny to set
them as compress algorithm of f2fs via 'compress_algorithm=%s' mount option.
Signed-off-by: Chao Yu
---
fs/f2fs/super.c | 16
1 file changed, 16 insertions(+)
diff --git a/fs/f2fs/super.c b/fs/f2fs/super
Introduce /sys/fs/f2fs//stat/sb_status to show superblock
status in real time as below:
IS_DIRTY: no
IS_CLOSE: no
IS_SHUTDOWN:no
IS_RECOVERED: no
IS_RESIZEFS:no
NEED_FSCK: no
POR_DOING: no
NEED_SB_WRITE:
On 12/9/20 1:53 AM, Mathieu Poirier wrote:
> On Tue, Dec 08, 2020 at 07:35:18PM +0100, Arnaud POULIQUEN wrote:
>> Hi Mathieu,
>>
>>
>> On 11/26/20 10:06 PM, Mathieu Poirier wrote:
>>> Introduce function rproc_detach() to enable the remoteproc
>>> core to release the resources associated with a r
On 12/9/20 8:58 AM, Dan Carpenter wrote:
> On Tue, Dec 08, 2020 at 09:01:49PM -0800, Joe Perches wrote:
>> On Tue, 2020-12-08 at 16:34 -0800, Kees Cook wrote:
>>
>> > If not "Adjusted-by", what about "Tweaked-by", "Helped-by",
>> > "Corrected-by"?
>>
>> Improved-by: / Enhanced-by: / Revisions-by:
On 11/26/20 10:06 PM, Mathieu Poirier wrote:
> This patch introduces the capability to detach a remote processor
> that has been attached to or booted by the remoteproc core. For
> that to happen a rproc::ops::detach() operation need to be
> available.
>
> Signed-off-by: Mathieu Poirier
> Rev
Hi Linus,
> Am 09.12.2020 um 09:38 schrieb Linus Walleij :
>
> On Sat, Dec 5, 2020 at 8:07 AM H. Nikolaus Schaller
> wrote:
>
>> I find it interesting that so far nobody wants to take responsibility
>> for a decision
> (...)
>
>
>>> What I can do is to provide just a skeleton for the table t
syzbot reported a bug which could cause shift-out-of-bounds issue,
fix it.
Call Trace:
__dump_stack lib/dump_stack.c:79 [inline]
dump_stack+0x107/0x163 lib/dump_stack.c:120
ubsan_epilogue+0xb/0x5a lib/ubsan.c:148
__ubsan_handle_shift_out_of_bounds.cold+0xb1/0x181 lib/ubsan.c:395
sanity_check_
Hello Stephen
Thank you for writing this page! Some comments/questions below.
On Tue, 8 Dec 2020 at 22:51, Stephen Kitt wrote:
>
> This documents close_range(2) based on information in
> 278a5fbaed89dacd04e9d052f4594ffd0e0585de and
> 60997c3d45d9a67daf01c56d805ae4fec37e0bd8.
(Thanks for noting
On 09.12.20 08:36, Muchun Song wrote:
> On Mon, Dec 7, 2020 at 8:39 PM David Hildenbrand wrote:
>>
>> On 30.11.20 16:18, Muchun Song wrote:
>>> In the later patch, we can use the free_vmemmap_page() to free the
>>> unused vmemmap pages and initialize a page for vmemmap page using
>>> via prepare_v
On Tue, Dec 8, 2020 at 3:07 PM Enrico Weigelt, metux IT consult
wrote:
> I've been looking for some more direct notification callback for gpio
> consumers: here the consumer would register itself as a listener on
> some gpio_desc and called back when something changes (with data what
> exactly ch
On 08.12.20 15:19, Andy Shevchenko wrote:
Hi,
> Have you able to test them all?
Not yet. It's still an *RFC*, I just like to discuss whether the whole
idea makes sense at all.
In case we come to the consensus that we should do it, I'm going to
split up the patch and rework everything more caref
On 07.12.20 14:11, Muchun Song wrote:
> On Mon, Dec 7, 2020 at 8:36 PM David Hildenbrand wrote:
>>
>> On 30.11.20 16:18, Muchun Song wrote:
>>> Every HugeTLB has more than one struct page structure. The 2M HugeTLB
>>> has 512 struct page structure and 1G HugeTLB has 4096 struct page
>>> structures
On Wed, 2020-12-09 at 10:58 +0300, Dan Carpenter wrote:
> On Tue, Dec 08, 2020 at 09:01:49PM -0800, Joe Perches wrote:
> > On Tue, 2020-12-08 at 16:34 -0800, Kees Cook wrote:
> >
> > > If not "Adjusted-by", what about "Tweaked-by", "Helped-by",
> > > "Corrected-by"?
> >
> > Improved-by: / Enhance
On 2020/11/17 18:25, John Garry wrote:
> Add a helper function to free the CPU rcache for all online CPUs.
>
> There also exists a function of the same name in
> drivers/iommu/intel/iommu.c, but the parameters are different, and there
> should be no conflict.
>
> Signed-off-by: John Garry
> ---
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