On Mon, Nov 2, 2020 at 3:26 PM Qian Cai wrote:
>
> On Thu, 2020-10-29 at 16:20 +0100, Miklos Szeredi wrote:
> > On Thu, Oct 29, 2020 at 4:02 PM Qian Cai wrote:
> > > On Wed, 2020-10-07 at 16:08 -0400, Qian Cai wrote:
> > > > Running some fuzzing by a unprivileged user on virtiofs could trigger
>
Re-factor master clock driver by splitting it into 2 clocks: prescaller
and divider clocks. Based on registered clock flags the prescaler's rate
could be changed at runtime. This is necessary for platforms supporting
DVFS (e.g. SAMA7G5) where master clock could be changed at run-time.
Signed-off-b
Fix the alignment issue pointed out by checkpatch
Signed-off-by: Siddhant Gupta
---
drivers/staging/mt7621-pci/pci-mt7621.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index f961b353c22
Add the documentation for the Microsemi Serval pinmuxing and gpio
controller.
Signed-off-by: Gregory CLEMENT
---
.../devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,oc
From: Lars Povlsen
This patch adds support for Serval pinctrl, using the ocelot driver as
basis. It adds pinconfig support as well, as supported by the
platform.
gclement: Split from a larger patch adding support all platforms in
the same time.
Signed-off-by: Lars Povlsen
Signed-off-by: Gregor
Hello,
Ocelot SoC belongs to a larger family of SoCs which use the same
interrupt controller with a few variation.
This series of patches add support for Luton and Serval, they are all
MIPS based.
The first patches of the series also updates the binding documentation
with the new compatible stri
Add the documentation for the Microsemi Luton pinmuxing and gpio
controller.
Signed-off-by: Gregory CLEMENT
---
.../devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt| 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocel
From: Lars Povlsen
This patch adds support for Luton pinctrl, using the ocelot driver as
basis. It adds pinconfig support as well, as supported by the
platform.
gclement: Split from a larger patch adding support all platforms in
the same time.
Signed-off-by: Lars Povlsen
Signed-off-by: Gregory
On Fri, Nov 06, 2020 at 12:59:07AM -0800, Prashant Malani wrote:
> Hi Greg,
>
> Thanks for looking at the patch.
>
> On Fri, Nov 06, 2020 at 08:20:59AM +0100, Greg Kroah-Hartman wrote:
> > On Thu, Nov 05, 2020 at 05:28:03PM -0800, Prashant Malani wrote:
> > > Use the PD VDO Type C cable plug type
On Thu, 5 Nov 2020 at 10:37, Jarkko Sakkinen wrote:
>
> On Tue, Nov 03, 2020 at 09:31:42PM +0530, Sumit Garg wrote:
> > Add support for TEE based trusted keys where TEE provides the functionality
> > to seal and unseal trusted keys using hardware unique key. Also, this is
> > an alternative in cas
I am Mr.Hamad ,i work as an accountant in a bank, i am contacting you
in regards to a business transfer of a huge sum of money from a
deceased account.I need your urgent assistance in transferring the sum
of $11.6million dollars to your private bank account,the fund belongs
to one of our foreign cu
The watchpoint encoding masks for size and address were off-by-one bit
each, with the size mask using 1 unnecessary bit and the address mask
missing 1 bit. However, due to the way the size is shifted into the
encoded watchpoint, we were effectively wasting and never using the
extra bit.
For exampl
Alex Shi writes:
> This macro is useless, and could cause gcc warning:
> arch/x86/kernel/kvmclock.c:47:0: warning: macro "HV_CLOCK_SIZE" is not
> used [-Wunused-macros]
> Let's remove it.
>
> Signed-off-by: Alex Shi
> Cc: Paolo Bonzini
> Cc: Sean Christopherson
> Cc: Vitaly Kuznetsov
> Cc:
On Fri, Oct 30, 2020 at 4:45 PM Arnd Bergmann wrote:
> This is the rebased version of my ARM set_fs patches on top of
> v5.10-rc1, dropping the TASK_SIZE_MAX patch but leaving everything
> else unchanged.
>
> I have tested the oabi-compat changes using the LTP tests for the three
> modified sysca
On 05-11-20, 16:18, Manivannan Sadhasivam wrote:
> From: Naveen Yadav
>
> Add Global Clock Controller (GCC) support for SDX55 SoCs from Qualcomm.
>
> Signed-off-by: Naveen Yadav
> [mani: converted to parent_data, commented critical clocks, cleanups]
> Signed-off-by: Manivannan Sadhasivam
> ---
On 05-11-20, 16:18, Manivannan Sadhasivam wrote:
> Add support for following clocks maintained by RPMh in SDX55 SoCs.
>
> * BI TCXO
> * RF_CLK1
> * RF_CLK1_AO
> * RF_CLK2
> * RF_CLK2_AO
> * QPIC (Qualcomm Technologies, Inc. Parallel Interface Controller)
Reviewed-by: Vinod Koul
--
~Vinod
On Thu, Nov 5, 2020 at 3:17 PM Bjorn Helgaas wrote:
>
> On Thu, Nov 05, 2020 at 11:46:06AM +0200, Joonas Lahtinen wrote:
> > Quoting Bjorn Helgaas (2020-11-04 19:35:56)
> > > [+cc Jani, Joonas, Rodrigo, David, Daniel]
> > >
> > > On Wed, Nov 04, 2020 at 05:35:06PM +0530, Tejas Upadhyay wrote:
> >
On Wed, 2020-11-04 at 16:39 -0600, Rob Herring wrote:
> On Mon, Nov 02, 2020 at 03:18:48PM +0800, Macpaul Lin wrote:
> > Option "mediatek,keep-clock-on" means to keep clock on during system
> > suspend and resume. Some platform will flush register settings if clock has
> > been disabled when system
On 05-11-20, 15:14, Linus Walleij wrote:
> On Tue, Nov 3, 2020 at 6:58 AM Vinod Koul wrote:
>
> > From: Jeevan Shriram
> >
> > Add initial Qualcomm SDX55 pinctrl driver to support pin configuration
> > with pinctrl framewor for SDX55 SoC.
> >
> > Signed-off-by: Jeevan Shriram
> > [ported from d
From: Voon Weifeng
Set all EHL/TGL phy_addr to -1 so that the driver will automatically
detect it at run-time by probing all the possible 32 addresses.
Signed-off-by: Voon Weifeng
Signed-off-by: Wong Vee Khee
---
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 6 +-
1 file changed, 1
idt_create_dev never return NULL and fix smatch warning.
Signed-off-by: Wang Qing
---
drivers/ntb/hw/idt/ntb_hw_idt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ntb/hw/idt/ntb_hw_idt.c b/drivers/ntb/hw/idt/ntb_hw_idt.c
index d54261f..e7a4c2a
--- a/drivers/ntb
On 2020-11-05 23:00, Thomas Gleixner wrote:
On Thu, Nov 05 2020 at 09:20, Marc Zyngier wrote:
On 2020-11-04 23:14, Thomas Gleixner wrote:
/* Resource alignment requirements */
resource_size_t (*align_resource)(struct pci_dev *dev,
If that's the direction of travel, we also nee
Hi Greg,
On Fri, Nov 06, 2020 at 10:33:02AM +0100, Greg Kroah-Hartman wrote:
> On Fri, Nov 06, 2020 at 12:59:07AM -0800, Prashant Malani wrote:
> > Hi Greg,
> >
> > Did you not receive these?
>
> Ah, I got 1, 2, and 5, and now 6. That's confusing, think about if you
> were to receive such a ser
Hi,
SAMA7G5 is capable of DVFS. The supported CPU clock frequencies could be
obtained from CPU PLL. The hardware block diagram for clock feeding the
CPU is as follows:
++
+-->|divider1|--> CPU clock
| +
Option "mediatek,str-clock-on" means to keep clock on during system
suspend and resume. Some platform will flush register settings if clock has
been disabled when system is suspended. Set this option to avoid clock off.
Change-Id: Id841f58e9d7fb3656511072b3eb14d0d355e2dd5
Signed-off-by: Macpaul Li
Some platform dose not support turn off clock when system suspending.
We add an option "mediatek,str-clock-on" for distinquish these platforms.
When "mediatek,str-clock-on" has been set, xhci-mtk driver will skip
turning clock on and off during system suspend and resume.
Signed-off-by: Macpaul Lin
From: Eugen Hristev
Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock
from phandle in DT.
Suggested-by: Claudiu Beznea
Signed-off-by: Eugen Hristev
[claudiu.bez...@microchip.com: adapt commit message, add CPU PLL]
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sama7g5.c |
From: Etienne Carriere
Do not print an error trace when deferring probe for clock resources.
Signed-off-by: Etienne Carriere
Signed-off-by: Christophe Roullier
---
drivers/watchdog/stm32_iwdg.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/watchdog/stm32_iw
From: Eugen Hristev
This SoC has the 5th divisor for the mck0 master clock.
Adapt the characteristics accordingly.
Reported-by: Mihai Sain
Signed-off-by: Eugen Hristev
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sama7g5.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
From: Eugen Hristev
clk-master can have 5 divisors with a field width of 3 bits
on some products.
Change the mask and number of divisors accordingly.
Reported-by: Mihai Sain
Signed-off-by: Eugen Hristev
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/clk-master.c | 2 +-
drivers/clk/at91
On Fri, Nov 06, 2020 at 12:08:22AM +0800, Muchun Song wrote:
> > I do not think you need this.
> > We already have hugepages_supported().
>
> Maybe some architectures support hugepage, but the vmemmap do not
> use the hugepage map. In this case, we need it. But I am not sure if it
> exists in the
pmc_data_allocate() has been changed. pmc_data_free() was removed.
Adapt the code taking this into consideration. With this the programmable
clocks were also saved in sama7g5_pmc so that they could be later
referenced.
Fixes: cb783bbbcf54 ("clk: at91: sama7g5: add clock support for sama7g5")
Signe
Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher
than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at
1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sama7g5.c | 61 +++
From: Eugen Hristev
Add SAMA7G5 specific PLL defines to be referenced in a phandle as a
PMC_TYPE_CORE clock.
Suggested-by: Claudiu Beznea
Signed-off-by: Eugen Hristev
[claudiu.bez...@microchip.com: adapt comit message, adapt sama7g5.c]
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sama7
MCK0 is changed at runtime by DVFS. Due to this, since not all IPs
are glitch free aware at MCK0 changes, remove MCK0 from parent list
of other clocks (e.g. generic clock, programmable/system clock, MCKX).
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sama7g5.c | 55 ++--
On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and
CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is
also changed by DVFS to avoid over/under clocking of MCK0 consumers.
The lower limit is changed to be able to set MCK0 accordingly by
DVFS.
Signed-off-by: Claudiu B
Re-factor master clock driver by splitting it into 2 clocks: prescaller
and divider clocks. Based on registered clock flags the prescaler's rate
could be changed at runtime. This is necessary for platforms supporting
DVFS (e.g. SAMA7G5) where master clock could be changed at run-time.
Signed-off-b
Allow runtime frequency changes for PLLs registered with proper flags.
This is necessary for CPU PLL on SAMA7G5 which is used by DVFS.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/clk-sam9x60-pll.c | 102 ++---
drivers/clk/at91/pmc.h | 4 +-
dr
Register CPU clock as being the master clock prescaler. This would
be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
frequencies supported by SAMA7G5 could be directly received from
CPUPLL + master clock p
On Fri, 6 Nov 2020 at 08:34, wrote:
>
> From: Patrice Chotard
>
> Add dev_wakeup_path() helper to avoid to spread
> dev->power.wakeup_path test in drivers.
>
> Cc: amelie.delau...@st.com,
> erwan_le...@st.com,
> fabrice.gasn...@st.com,
> alexandre.tor...@st.com,
> alain.vol...@st.
detect this unneeded assignment and optimize this anyway,
the resulting object code is identical before and after this change.
No functional change. No change to object code.
Signed-off-by: Lukas Bulwahn
---
applies cleanly on current master and next-20201106
Stephen, Michael, please pick this minor non-u
Hello Christophe,
On 11/6/20 10:46 AM, Christophe Roullier wrote:
> From: Etienne Carriere
>
> Do not print an error trace when deferring probe for clock resources.
>
> Signed-off-by: Etienne Carriere
> Signed-off-by: Christophe Roullier
> ---
> drivers/watchdog/stm32_iwdg.c | 6 --
> 1
> From: Jason Gunthorpe
> Sent: Wednesday, November 4, 2020 9:54 PM
>
> On Wed, Nov 04, 2020 at 01:34:08PM +, Tian, Kevin wrote:
> > > From: Jason Gunthorpe
> > > Sent: Wednesday, November 4, 2020 8:40 PM
> > >
> > > On Wed, Nov 04, 2020 at 03:41:33AM +, Tian, Kevin wrote:
> > > > > From
On the architectures with perf memory profiling, two types of hardware
events have been supported: load and store; if want to profile memory
for both load and store operations, the tool will use these two events
at the same time, the usage is:
# perf mem record -t load,store -- uname
But this c
This patch series is v4 for support perf mem/c2c AUX trace.
Comparing to patch set v3, this patch set adds back the patch 06/09 for
introducing the itrace option '-M', this allows to synthenize memory
event from the AUX trace data.
Since perf mem/c2c tools are focus on memory profiling, this patc
Different architectures might use different event or different event
parameters for memory profiling, this patch introduces weak function
perf_mem_events__ptr(), which allows to return back architecture
specific memory event.
Since the variable 'perf_mem_events' can be only accessed by the
functio
Perf tool searches memory event name under the folder
'/sys/devices/cpu/events/', this leads to the limitation for selection
memory profiling event which must be under this folder. Thus it's
impossible to use any other event as memory event which is not under
this specific folder, e.g. Arm SPE har
When user doesn't specify event name, perf c2c tool enables both the
load and store events, and this leads to failure for opening the
duplicate PMU device for AUX trace.
After the memory event PERF_MEM_EVENTS__LOAD_STORE is introduced, when
the user doesn't specify event name, this patch converts
This patch is to add itrace option '-M' to synthesize memory event.
Signed-off-by: Leo Yan
---
tools/perf/Documentation/itrace.txt | 1 +
tools/perf/util/auxtrace.c | 4
tools/perf/util/auxtrace.h | 2 ++
3 files changed, 7 insertions(+)
diff --git a/tools/perf/Documentat
Perf memory tool doesn't support AUX trace data so it cannot receive the
hardware tracing data. On Arm64, although it doesn't support PMU events
for memory load and store, but Arm SPE is a good candidate for memory
profiling, the hardware tracer can record memory accessing operations
with affiliat
It's needless to initialize memory events for reporting, this patch
moves memory event initialization for only recording. Furthermore,
the change allows to parse perf data on cross platforms, e.g. perf
tool can report result properly even the machine doesn't support
the memory events.
Signed-off-
This patch adds the AUX callbacks in session structure, so support
AUX trace for "perf c2c" tool; make itrace memory event as default for
"perf c2c", this tells the AUX trace decoder to synthesize samples and
can be used for statistics.
Signed-off-by: Leo Yan
---
tools/perf/builtin-c2c.c | 12 ++
This patch adds Arm SPE events for perf memory profiling:
'spe-load': event for only recording memory load ops;
'spe-store': event for only recording memory store ops;
'spe-ldst': event for recording memory load and store ops.
Signed-off-by: Leo Yan
---
tools/perf/arch/arm64/util/Build
On Fri, Nov 06, 2020 at 07:22:10AM +0100, Lukas Bulwahn wrote:
> make clang-analyzer on x86_64 defconfig caught my attention with:
>
> kernel/taskstats.c:120:2: warning: Value stored to 'rc' is never read \
> [clang-analyzer-deadcode.DeadStores]
> rc = 0;
> ^
>
> Commit d9
Hi Srinivas,
thanks for your patch!
On Thu, Nov 5, 2020 at 1:04 PM Srinivas Kandagatla
wrote:
> Add initial pinctrl driver to support pin configuration for
> LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
> on SM8250.
>
> Signed-off-by: Srinivas Kandagatla
So this is in esse
On Fri, Nov 06, 2020 at 05:46:34AM -0300, Marcelo Ricardo Leitner wrote:
> On Thu, Nov 05, 2020 at 11:39:47AM +0100, Petr Malat wrote:
> > Function sctp_dst_mtu() never returns lower MTU than
> > SCTP_TRUNC4(SCTP_DEFAULT_MINSEGMENT) even when the actual MTU is less,
> > in which case we rely on the
change to object code.
>
> Signed-off-by: Lukas Bulwahn
Indeed, parent is always assigned a new value before that one is read.
Reviewed-by: Nathan Chancellor
> ---
> applies cleanly on current master and next-20201106
>
> Stephen, Michael, please pick this minor non-urge
On Wed, Nov 04, 2020 at 07:35:26PM +, Lee Jones wrote:
> Fixes the following W=1 kernel build warning(s):
>
> drivers/tty/serial/8250/8250_port.c:349:14: warning: no previous prototype
> for ‘au_serial_in’ [-Wmissing-prototypes]
> drivers/tty/serial/8250/8250_port.c:359:6: warning: no previ
MCP16502 have multiple configuration registers for each regulator (as
described in enum mcp16502_reg). Adapt the code to be able to get/set
all these registers. This is necessary for the following commits.
Signed-off-by: Claudiu Beznea
---
drivers/regulator/mcp16502.c | 43 ++
Selectors b/w zero and VDD_LOW_SEL are not valid. Use linear_min_sel.
Fixes: 919261c03e7ca ("regulator: mcp16502: add regulator driver for MCP16502")
Signed-off-by: Claudiu Beznea
---
drivers/regulator/mcp16502.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/regulator/mcp16502.c b/
Do not continue if selector has already been located.
Signed-off-by: Claudiu Beznea
---
drivers/regulator/core.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index 19a330492884..4584b5b988ab 100644
--- a/drivers/regulator/core.c
+++ b
MCP16502 have configurable ramp delay support (via DVSR bits in
regulators' CFG register).
Signed-off-by: Claudiu Beznea
---
drivers/regulator/mcp16502.c | 86 ++--
1 file changed, 84 insertions(+), 2 deletions(-)
diff --git a/drivers/regulator/mcp16502.c
There are regulators whose min selector is not zero. Selectors loops
(looping b/w zero and regulator::desc::n_voltages) might throw errors
because invalid selectors are used (lower than
regulator::desc::linear_min_sel). For this situations validate selectors
against regulator::desc::linear_min_sel.
Hi,
This series adds support for ramp delay on mcp16502. It also adds
some cleanup on mcp16502.
Apart from that patches 1/6 fixes the selector validation in case
the regulator::desc::linear_min_sel is not zero.
Thank you,
Claudiu Beznea
Claudiu Beznea (6):
regulator: core: validate selector a
struct mcp16502 has no members called rdev or rmap. Remove the
documentation.
Signed-off-by: Claudiu Beznea
---
drivers/regulator/mcp16502.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/regulator/mcp16502.c b/drivers/regulator/mcp16502.c
index 0cd4f5936e94..7a46641da60e 100644
--
On Wed, Nov 04, 2020 at 07:35:13PM +, Lee Jones wrote:
> This set is part of a larger effort attempting to clean-up W=1
> kernel builds, which are currently overwhelmingly riddled with
> niggly little warnings.
Many of these now applied, please update the series against my
tty-testing branch a
On Fri, 2020-11-06 at 17:46 +0800, Macpaul Lin wrote:
> Option "mediatek,str-clock-on" means to keep clock on during system
> suspend and resume. Some platform will flush register settings if clock has
> been disabled when system is suspended. Set this option to avoid clock off.
>
> Change-Id: Id8
From: Terry Zhou
There is an error in the current code that the XTAL MODE
pin was set to NB MPP1_31 which should be NB MPP1_9.
The latch register of NB MPP1_9 has different offset of 0x8.
Signed-off-by: Terry Zhou
[pali: Fix pin name in commit message]
Signed-off-by: Pali Rohár
Fixes: 7ea82504
On Sun, Nov 01, 2020 at 12:32:44PM +0200, Hassan Shahbazi wrote:
> On Sun, Nov 01, 2020 at 07:39:48AM +0100, Greg KH wrote:
> > On Sun, Nov 01, 2020 at 02:20:10AM +0200, Hassan Shahbazi wrote:
> > > Fix the checkpath.pl issue on fb_watterott.c. write_vmem and
> > > write_vmem_8bit functions are wit
On Fri, Nov 6, 2020 at 5:08 AM John Hubbard wrote:
>
> On 11/5/20 4:49 AM, Jason Gunthorpe wrote:
> > On Thu, Nov 05, 2020 at 10:25:24AM +0100, Daniel Vetter wrote:
> >>> /*
> >>> * If we can't determine whether or not a pte is special, then fail
> >>> immediately
> >>> * for ptes. Note, we c
On Wed, Nov 04, 2020 at 04:54:16PM +0200, Jarkko Sakkinen wrote:
> From: Sean Christopherson
>
> Background
> ==
>
> 1. SGX enclave pages are populated with data by copying from normal memory
>via ioctl() (SGX_IOC_ENCLAVE_ADD_PAGES), which will be added later in
>this series.
> 2
On Thu, 5 Nov 2020, Steven Rostedt wrote:
> From: "Steven Rostedt (VMware)"
>
> If a ftrace callback does not supply its own recursion protection and
> does not set the RECURSION_SAFE flag in its ftrace_ops, then ftrace will
> make a helper trampoline to do so before calling the callback instead
On Fri, 06 Nov 2020, Greg Kroah-Hartman wrote:
> On Wed, Nov 04, 2020 at 07:35:26PM +, Lee Jones wrote:
> > Fixes the following W=1 kernel build warning(s):
> >
> > drivers/tty/serial/8250/8250_port.c:349:14: warning: no previous prototype
> > for ‘au_serial_in’ [-Wmissing-prototypes]
> >
在 2020/11/5 22:24, Marc Zyngier 写道:
On 2020-11-05 14:06, xuqiang (M) wrote:
在 2020/11/5 21:12, Marc Zyngier 写道:
Please don't top-post.
On 2020-11-05 11:54, xuqiang (M) wrote:
The kernel sends three commands in the following sequence:
1.mapd(deviceA, ITT_addr1, valid:1)
2.mapti(deviceA):IT
On 05-11-20, 19:23, Rafael J. Wysocki wrote:
> Index: linux-pm/include/linux/cpufreq.h
> ===
> --- linux-pm.orig/include/linux/cpufreq.h
> +++ linux-pm/include/linux/cpufreq.h
> @@ -63,6 +63,8 @@ struct cpufreq_policy {
>
> uns
On Thu, 5 Nov 2020, Steven Rostedt wrote:
> From: "Steven Rostedt (VMware)"
>
> If for some reason a function is called that triggers the recursion
> detection of live patching, trigger a warning. By not executing the live
> patch code, it is possible that the old unpatched function will be call
On 06/11/20 07:51, yadong...@intel.com wrote:
@@ -4036,6 +4060,8 @@ static void sync_vmcs02_to_vmcs12(struct kvm_vcpu *vcpu,
struct vmcs12 *vmcs12)
if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
+ else if (vcpu->arc
On Wed, Nov 04, 2020 at 02:30:04PM +0100, Miguel Ojeda wrote:
> Thanks a lot for all the work, Lars. Queued in -next.
I got an email [1] with a report about a build failure in
hd44780_common. The fix is simple but I don't know the process from here
on. Should I post a v7 of the whole patchset or o
Add option to prevent firmware/configuration loading during each boot.
Andrej Valek (3):
Input: st1232 - add support resolution reading
dt-bindings: goodix
Input: goodix - add option to disable firmware loading
.../bindings/input/touchscreen/goodix.yaml| 2 +-
drivers/input/touchscree
Firmware file loadind for GT911 controller takes too much time (~60s).
There is no check that configuration is the same which is already present.
This happens always during boot, which makes touchscreen unusable.
Add there an option to prevent firmware file loading, but keep it enabled
by default.
Hard-coding resolution for st1633 device was wrong. Some of LCDs like
YTS700TLBC-02-100C has assembled Sitronix st1633 touchcontroller too. But
the resolution is not 320x480 as was hard-coded.
Add new function which reads correct resolution directly from register.
Signed-off-by: Andrej Valek
---
Add information about option how to disable FW loading for each boot.
Signed-off-by: Andrej Valek
---
Documentation/devicetree/bindings/input/touchscreen/goodix.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/input/touchscreen/goodix.yam
+ Ard, who wrote this code.
On Fri, Nov 06, 2020 at 07:14:36AM +0200, Adrian Ratiu wrote:
> Due to a Clang bug [1] neon autoloop vectorization does not happen or
> happens badly with no gains and considering previous GCC experiences
> which generated unoptimized code which was worse than the defau
On Fri, 06 Nov 2020, Lee Jones wrote:
> On Fri, 06 Nov 2020, Greg Kroah-Hartman wrote:
>
> > On Wed, Nov 04, 2020 at 07:35:26PM +, Lee Jones wrote:
> > > Fixes the following W=1 kernel build warning(s):
> > >
> > > drivers/tty/serial/8250/8250_port.c:349:14: warning: no previous
> > > prot
On 05/11/20 16:53, Vitaly Kuznetsov wrote:
The current implementation of Hyper-V SynIC[1] request to deactivate
APICv when SynIC is enabled, since the AutoEOI feature of SynIC is not
compatible with APICv[2].
Actually, windows doesn't use AutoEOI if deprecating AutoEOI bit is set
(CPUID.4004
On 04/11/20 10:35, David Woodhouse wrote:
On Wed, 2020-10-28 at 15:35 +0100, Peter Zijlstra wrote:
On Tue, Oct 27, 2020 at 02:39:43PM +, David Woodhouse wrote:
From: David Woodhouse
This allows an exclusive wait_queue_entry to be added at the head of the
queue, instead of the tail as norm
On Thu, Nov 05, 2020 at 04:45:46PM +, Mark Brown wrote:
> The following changes since commit 3650b228f83adda7e5ee532e2b90429c03f7b9ec:
>
> Linux 5.10-rc1 (2020-10-25 15:14:11 -0700)
>
> are available in the Git repository at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sp
In order to account for any potential overflows that could occur.
Signed-off-by: Alexandru Ardelean
---
drivers/hwmon/ltc2945.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/hwmon/ltc2945.c b/drivers/hwmon/ltc2945.c
index 1cea710df668..75d997d31e01 10
The sense resistor is a parameter of the board. It should be configured in
the driver via a device-tree / ACPI property, so that the proper current
measurements can be done in the driver.
It shouldn't be necessary that userspace need to know about the value of
the resistor. It makes things a bit h
On 29/09/20 17:09, Vitaly Kuznetsov wrote:
Changes since v2:
- Keep vCPU version of the ioctl intact but make it 'deprecated' in
api.rst [Paolo Bonzini]
- First two patches of v2 series already made it to kvm/queue
QEMU series using the feature:
https://lists.gnu.org/archive/html/qemu-devel/2
On Fri, Nov 06, 2020 at 10:34:56AM +0100, Marco Elver wrote:
> The watchpoint encoding masks for size and address were off-by-one bit
> each, with the size mask using 1 unnecessary bit and the address mask
> missing 1 bit. However, due to the way the size is shifted into the
> encoded watchpoint, w
On Fri, Nov 06, 2020 at 10:03:21AM +0100, Marco Elver wrote:
> On Fri, 6 Nov 2020 at 02:23, Boqun Feng wrote:
> > Hi Marco,
> >
> > On Thu, Nov 05, 2020 at 02:03:24PM -0800, paul...@kernel.org wrote:
> > > From: Marco Elver
> > >
> > > The watchpoint encoding masks for size and address were off-b
The intent is to add pass the value of the sense resistor in the driver.
This change wraps a 'struct ltc2945_state', and moves the regmap reference
on that object.
Then we can add the value of the sense resistor, or other information that
would be useful for the driver.
Signed-off-by: Alexandru A
On Thu 2020-11-05 19:14:27, Matteo Croce wrote:
> On Thu, Nov 5, 2020 at 7:09 PM Petr Mladek wrote:
> > > + if (reboot_cpu >= num_possible_cpus()) {
> > > + pr_err("Ignoring the CPU number in reboot=
> > > option. "
> > > +
On Fri, Nov 06, 2020 at 10:05:52AM +, Lee Jones wrote:
> On Fri, 06 Nov 2020, Greg Kroah-Hartman wrote:
>
> > On Wed, Nov 04, 2020 at 07:35:26PM +, Lee Jones wrote:
> > > Fixes the following W=1 kernel build warning(s):
> > >
> > > drivers/tty/serial/8250/8250_port.c:349:14: warning: no
Hi Boris,
Thanks for your comments and suggestions.
> -Original Message-
> From: Boris Brezillon
> Sent: Friday, November 6, 2020 5:06 PM
> To: Chin-Ting Kuo
> Subject: Re: [v3 4/4] spi: aspeed: Add ASPEED FMC/SPI memory controller
> driver
>
> On Fri, 6 Nov 2020 08:58:23 +
> Chin-
This change converts the old device-tree binding for ADAU1977 from text
format to the new yaml format.
Signed-off-by: Alexandru Ardelean
---
.../bindings/sound/adi,adau1977.txt | 61 ---
.../bindings/sound/adi,adau1977.yaml | 77 +++
2 files changed
Option "mediatek,str-clock-on" means to keep clock on during system
suspend and resume. Some platform will flush register settings if clock has
been disabled when system is suspended. Set this option to avoid clock off.
Fixes: 0cbd4b34cda9 ("xhci: mediatek: support MTK xHCI host controller")
Signe
On Fri, Nov 06, 2020 at 10:48:24AM +0100, Petr Malat wrote:
> On Fri, Nov 06, 2020 at 05:46:34AM -0300, Marcelo Ricardo Leitner wrote:
> > On Thu, Nov 05, 2020 at 11:39:47AM +0100, Petr Malat wrote:
> > > Function sctp_dst_mtu() never returns lower MTU than
> > > SCTP_TRUNC4(SCTP_DEFAULT_MINSEGMENT
Some platform dose not support turn off clock when system suspending.
We add an option "mediatek,str-clock-on" for distinquish these platforms.
When "mediatek,str-clock-on" has been set, xhci-mtk driver will skip
turning clock on and off during system suspend and resume.
Fixes: 0cbd4b34cda9 ("xhci
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