On Thu, Nov 5, 2020 at 1:47 AM Leon Romanovsky wrote:
>
> On Thu, Nov 05, 2020 at 01:19:09AM -0800, Dan Williams wrote:
> > Some doc fixups, and minor code feedback. Otherwise looks good to me.
> >
> > On Thu, Oct 22, 2020 at 5:35 PM Dave Ertman
> > wrote:
> > >
>
> <...>
>
> > >
> > > +config A
On Thu, 2020-11-05 at 14:53 +1100, Victor Ding wrote:
> On Wed, Nov 4, 2020 at 1:17 PM Srinivas Pandruvada
> wrote:
> > On Wed, 2020-11-04 at 12:43 +1100, Victor Ding wrote:
> > > On Wed, Nov 4, 2020 at 4:09 AM Srinivas Pandruvada
> > > wrote:
> > > > On Tue, 2020-11-03 at 17:10 +1100, Victor Din
On 10/9/20 6:05 AM, Christian Brauner wrote:
On Thu, Oct 08, 2020 at 03:26:29PM +0300, Tommi Rantala wrote:
Fix multiple definition of sock_name compilation error:
tools/testing/selftests/android/ion/ipcsocket.h:8: multiple definition of
`sock_name'
Signed-off-by: Tommi Rantala
---
Ion
+sta...@vger.kernel.org
On 11/1/20 11:34 AM, Chris Ye wrote:
Kernel 5.4 introduces HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE, devices
need to be set explicitly with this flag.
Signed-off-by: Chris Ye
---
drivers/hid/hid-ids.h| 4
drivers/hid/hid-quirks.c | 4
2 files changed, 8
On 11/5/20, 10:27 AM, Rob Herring wrote:
>
> On Thu, Nov 5, 2020 at 2:33 AM Marek Szyprowski
> wrote:
> >
> > Hi Rob,
> >
> > On 04.11.2020 22:35, Rob Herring wrote:
> > > On Thu, Oct 29, 2020 at 02:40:13PM +0100, Marek Szyprowski wrote:
> > >> Add dt-bindings for the Samsung Exynos PCIe controll
From: Yadong Qi
Background: We have a lightweight HV, it needs INIT-VMExit and
SIPI-VMExit to wake-up APs for guests since it do not monitor
the Local APIC. But currently virtual wait-for-SIPI(WFS) state
is not supported in nVMX, so when running on top of KVM, the L1
HV cannot receive the INIT-VM
The first patch is new, the second is a rebase of Yadong's patch
Paolo Bonzini (1):
KVM: x86: fix apic_accept_events vs check_nested_events
Yadong Qi (1):
KVM: x86: emulate wait-for-SIPI and SIPI-VMExit
arch/x86/include/asm/vmx.h | 1 +
arch/x86/include/uapi/asm/vmx.h | 2 ++
arch/x8
On 11/5/20 9:42 AM, Michal Simek wrote:
> Hi,
>
> čt 5. 11. 2020 v 17:18 odesílatel Jens Axboe napsal:
>>
>> Gentle nudge on this one.
>>
>> On 10/29/20 10:16 AM, Jens Axboe wrote:
>>> Wire up TIF_NOTIFY_SIGNAL handling for microblaze.
>>>
>>> Cc: Michal Simek
>>> Signed-off-by: Jens Axboe
>>>
vmx_apic_init_signal_blocked is buggy in that it returns true
even in VMX non-root mode. In non-root mode, however, INITs
are not latched, they just cause a vmexit. Previously,
KVM was waiting for them to be processed when kvm_apic_accept_events
and in the meanwhile it ate the SIPIs that the proc
Hello,
Ocelot SoC belongs to a larger family of SoCs which use the same
interrupt controller with a few variation.
This series of patches add support for Luton, Serval and Jaguar2, they
are all MIPS based.
The first patches of the series also updates the binding documentation
with the new compat
Add the Device Tree binding documentation for the Microsemi Jaguar2
interrupt controller that is part of the ICPU. It is connected directly to
the MIPS core interrupt controller.
Signed-off-by: Gregory CLEMENT
---
.../interrupt-controller/mscc,ocelot-icpu-intr.txt | 7 ---
1 file cha
This patch extends irqchip driver for ocelot to be used with an other
vcoreiii base platform: Serval.
Based on a larger patch from Lars Povlsen
Signed-off-by: Gregory CLEMENT
---
drivers/irqchip/irq-mscc-ocelot.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/
This patch extends irqchip driver for ocelot to be used with an other
vcoreiii base platform: Jaguar2.
Based on a larger patch from Lars Povlsen
Signed-off-by: Gregory CLEMENT
---
drivers/irqchip/irq-mscc-ocelot.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers
On Thu, Nov 05, 2020 at 09:02:49AM -0800, Minchan Kim wrote:
> This reverts commit e47110e90584a22e9980510b00d0dfad3a83354e.
>
> While I was doing zram testing, I found sometimes decompression failed
> since the compression buffer was corrupted. With investigation,
> I found below commit calls con
Add the Device Tree binding documentation for the Microsemi Serval
interrupt controller that is part of the ICPU. It is connected directly to
the MIPS core interrupt controller.
Signed-off-by: Gregory CLEMENT
---
.../bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt| 3 ++-
1 file chan
Hi Andre,
I love your patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v5.10-rc2 next-20201105]
[cannot apply to arm64/for-next/core kvmarm/next arm-perf/for-next/perf]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And
On Thu 05-11-20 08:50:58, Suren Baghdasaryan wrote:
> On Thu, Nov 5, 2020 at 4:20 AM Michal Hocko wrote:
> >
> > On Wed 04-11-20 12:40:51, Minchan Kim wrote:
> > > On Wed, Nov 04, 2020 at 07:58:44AM +0100, Michal Hocko wrote:
> > > > On Tue 03-11-20 13:32:28, Minchan Kim wrote:
> > > > > On Tue, N
Hi Andre,
I love your patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v5.10-rc2 next-20201105]
[cannot apply to arm64/for-next/core kvmarm/next arm-perf/for-next/perf]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And
Add the Device Tree binding documentation for the Microsemi Luton
interrupt controller that is part of the ICPU. It is connected directly to
the MIPS core interrupt controller.
Signed-off-by: Gregory CLEMENT
---
.../bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt | 4 +++-
1 file chang
On 05/11/20 16:33, Daniel Bristot de Oliveira wrote:
> On 11/5/20 5:12 PM, Juri Lelli wrote:
>> On 05/11/20 15:49, Valentin Schneider wrote:
>>> For my own sake, what affinity problems are you thinking of?
>>>
>>> With proxy exec we have this "funny" dance of shoving the entire blocked-on
>>> cha
syzbot suspects this issue was fixed by commit:
commit f8e48a3dca060e80f672d398d181db1298fbc86c
Author: Peter Zijlstra
Date: Thu Oct 22 10:23:02 2020 +
lockdep: Fix preemption WARN for spurious IRQ-enable
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=17bbfa8a50
star
On Mon, Nov 02, 2020 at 04:19:59PM +0200, Cristian Pop wrote:
> Optional attribute for better identification of the channels.
>
> Signed-off-by: Cristian Pop
> ---
> Changes in v7:
> - Add "additionalProperties: false" for channel child nodes.
> - Fix "reg" spelling.
> .../bindings/iio/adc/adi
On 17/07/20 13:34, Cathy Avery wrote:
When running tests that can result in a vcpu being left in an
indeterminate state it is useful to be able to run the test on
a vcpu other than 0. This patch allows test_run to be executed
on any vcpu indicated by the on_vcpu member of the svm_test struct.
The
On Thu, Nov 5, 2020 at 9:16 AM Michal Hocko wrote:
>
> On Thu 05-11-20 08:50:58, Suren Baghdasaryan wrote:
> > On Thu, Nov 5, 2020 at 4:20 AM Michal Hocko wrote:
> > >
> > > On Wed 04-11-20 12:40:51, Minchan Kim wrote:
> > > > On Wed, Nov 04, 2020 at 07:58:44AM +0100, Michal Hocko wrote:
> > > >
On Wed, Nov 04, 2020 at 03:01:17PM -0500, Felix Kuehling wrote:
> On 2020-11-04 10:13 a.m., Deepak R Varma wrote:
> > idr_init() uses base 0 which is an invalid identifier. The new function
> > idr_init_base allows IDR to set the ID lookup from base 1. This avoids
> > all lookups that otherwise sta
+sta...@vger.kernel.org
On 11/3/20 9:36 AM, Benjamin Tissoires wrote:
Hi Chris,
On Mon, Nov 2, 2020 at 6:24 PM Chris Ye wrote:
Hi Benjamin,
I've tried the hid-tool for testing on my linux machine and it
works. However the issue comes from a game controller I don't posses in
hand right
On Thu, Nov 05, 2020 at 12:18:45AM +0100, Andrey Konovalov wrote:
> diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c
> index 06ba6c923ab7..fcfbefcc3174 100644
> --- a/arch/arm64/kernel/mte.c
> +++ b/arch/arm64/kernel/mte.c
> @@ -121,6 +121,13 @@ void *mte_set_mem_tag_range(void *addr,
On 10/30/20 9:38 PM, Thomas Gleixner wrote:
> Coming back to your test coverage argument. I really don't see a problem
> with the requirement of having qemu installed in order to run 'make
> check'.
Cost. It's is cheaper and easier to maintain and deploy containers.
A full VM requires maintaining
On Thu, Nov 5, 2020 at 3:14 PM Vincenzo Frascino
wrote:
>
>
>
> On 11/5/20 12:14 PM, Andrey Konovalov wrote:
> > On Thu, Nov 5, 2020 at 12:39 PM Vincenzo Frascino
> > wrote:
> >>
> >> On 11/5/20 11:35 AM, Andrey Konovalov wrote:
> >>> This will work. Any preference on the name of this function?
>
On Thu, Nov 05, 2020 at 03:54:07AM +0100, Michał Mirosław wrote:
> Help debugging the case when set_machine_constraints() needs to be
> repeated.
This doesn't seem to apply against current code for some reason, git am
can't find the SHA1 it's based on.
signature.asc
Description: PGP signature
On Thu, Nov 5, 2020 at 6:26 PM Catalin Marinas wrote:
>
> On Thu, Nov 05, 2020 at 12:18:45AM +0100, Andrey Konovalov wrote:
> > diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c
> > index 06ba6c923ab7..fcfbefcc3174 100644
> > --- a/arch/arm64/kernel/mte.c
> > +++ b/arch/arm64/kernel/m
On Thu, Nov 05, 2020 at 12:18:47AM +0100, Andrey Konovalov wrote:
> diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c
> index 14b0c19a33e3..cc7e0f8707f7 100644
> --- a/arch/arm64/kernel/mte.c
> +++ b/arch/arm64/kernel/mte.c
> @@ -23,6 +23,8 @@
> #include
> #include
>
> +u64 gcr_k
On Thu, Nov 05, 2020 at 12:18:52AM +0100, Andrey Konovalov wrote:
> Some #ifdef CONFIG_KASAN checks are only relevant for software KASAN
> modes (either related to shadow memory or compiler instrumentation).
> Expand those into CONFIG_KASAN_GENERIC || CONFIG_KASAN_SW_TAGS.
>
> Signed-off-by: Andre
On Thu, Nov 5, 2020 at 6:30 PM Catalin Marinas wrote:
>
> On Thu, Nov 05, 2020 at 12:18:47AM +0100, Andrey Konovalov wrote:
> > diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c
> > index 14b0c19a33e3..cc7e0f8707f7 100644
> > --- a/arch/arm64/kernel/mte.c
> > +++ b/arch/arm64/kernel/m
On Thu, Nov 05, 2020 at 05:16:02PM +, Matthew Wilcox wrote:
> On Thu, Nov 05, 2020 at 09:02:49AM -0800, Minchan Kim wrote:
> > This reverts commit e47110e90584a22e9980510b00d0dfad3a83354e.
> >
> > While I was doing zram testing, I found sometimes decompression failed
> > since the compression
On 11/5/20 8:04 AM, Borislav Petkov wrote:
...
>> Add a vm_ops->mprotect() hook so that mprotect() operations which are
>> inconsistent with any page's stashed intent can be rejected by the driver.
>>
>> Cc: linux...@kvack.org
>> Cc: Andrew Morton
>> Cc: Matthew Wilcox
>> Acked-by: Jethro Beekman
On Sat, 10 Oct 2020 20:03:51 PDT (-0700), ryanpko...@gmail.com wrote:
Signed-off-by: Ryan Kosta
---
arch/riscv/kernel/ftrace.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/ftrace.c b/arch/riscv/kernel/ftrace.c
index 99e12faa549..765b62434f3 100644
--- a/
On Mon, 05 Oct 2020 17:17:52 PDT (-0700), Atish Patra wrote:
Use the generic numa implementation to add NUMA support for RISC-V.
This is based on Greentime's patch[1] but modified to use generic NUMA
implementation and few more fixes.
[1] https://lkml.org/lkml/2020/1/10/233
Co-developed-by: Gre
On Mon, 05 Oct 2020 17:17:51 PDT (-0700), Atish Patra wrote:
From: Greentime Hu
These two functions are used to distinguish between PROT_NONENUMA
protections and hinting fault protections.
Signed-off-by: Greentime Hu
---
arch/riscv/include/asm/pgtable.h | 20
1 file chan
On Mon, 05 Oct 2020 17:17:50 PDT (-0700), Atish Patra wrote:
Currently, we perform some memory init functions in paging init. But,
that will be an issue for NUMA support where DT needs to be flattened
before numa initialization and memblock_present can only be called
after numa initialization.
M
The CLKSCREW attack [0] exposed security vulnerabilities in energy management
implementations where untrusted software had direct access to clock and
voltage hardware controls. In this attack, the malicious software was able to
place the platform into unsafe overclocked or undervolted configuration
This patch extends irqchip driver for oceleot to be used with an other
vcoreiii base platform: Luton.
Based on a larger patch from Lars Povlsen
Signed-off-by: Gregory CLEMENT
---
drivers/irqchip/irq-mscc-ocelot.c | 145 +-
1 file changed, 123 insertions(+), 22 deleti
idr_init() uses base 0 which is an invalid identifier. The new function
idr_init_base allows IDR to set the ID lookup from base 1. This avoids
all lookups that otherwise starts from 0 since 0 is always unused.
References: commit 6ce711f27500 ("idr: Make 1-based IDRs more efficient")
Signed-off-by
On Mon, 02 Nov 2020 16:06:58 +0100, Uwe Kleine-König wrote:
> Document the new board by Kobol introduced recently in
> rockchip/rk3399-kobol-helios64.dts.
>
> Signed-off-by: Uwe Kleine-König
> ---
> Hello,
>
> Heiko pointed out in irc that I missed this bit when submitting support
> for the heli
On Mon, 02 Nov 2020 16:20:00 +0200, Cristian Pop wrote:
> Optional attribute for better identification of the channels.
>
> Signed-off-by: Cristian Pop
> ---
> Changes in v7:
> - Add this extra commit
> Documentation/devicetree/bindings/iio/adc/adc.txt | 6 ++
> 1 file changed, 6 insertions
On Mon, 02 Nov 2020 17:32:38 +, Cristian Marussi wrote:
> Add devicetree bindings to support regulators based on SCMI Voltage
> Domain Protocol.
>
> Signed-off-by: Cristian Marussi
> ---
> v3 --> v4
> - added list of supported Regulator bindings.
> v2 --> v3
> - avoid awkard examples based on
On Thu, Nov 05, 2020 at 06:29:17PM +0100, Andrey Konovalov wrote:
> On Thu, Nov 5, 2020 at 6:26 PM Catalin Marinas
> wrote:
> >
> > On Thu, Nov 05, 2020 at 12:18:45AM +0100, Andrey Konovalov wrote:
> > > diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c
> > > index 06ba6c923ab7..fcfb
On 11/5/20 3:29 PM, Olivier Moysan wrote:
> - Remove processing related to DMA in irq handler as this
> data transfer is managed directly in DMA callback.
> - Update comment in stm32_adc_set_watermark() function.
>
> Signed-off-by: Olivier Moysan
Hi Olivier,
Reviewed-by: Fabrice Gasnier
Thank
On Thu, Nov 05, 2020 at 12:16:34PM +0100, Daniel Vetter wrote:
> On Thu, Nov 5, 2020 at 11:31 AM Deepak R Varma wrote:
> >
> > On Thu, Nov 05, 2020 at 10:42:15AM +0100, Daniel Vetter wrote:
> > > On Wed, Nov 04, 2020 at 04:53:38PM +0530, Deepak R Varma wrote:
> > > > idr_init() uses base 0 which i
(adding stable and Greg KH for additional review)
On Thu, 2020-11-05 at 17:29 +0530, Dwaipayan Ray wrote:
> checkpatch doesn't report warnings for many common mistakes
> in emails. Some of which are trailing commas and incorrect
> use of email comments.
I presume you've tested this against the git
On Wed, Nov 04, 2020 at 08:30:50PM +0100, Bartosz Golaszewski wrote:
> @@ -119,21 +81,39 @@ static void exar_set_value(struct gpio_chip *chip,
> unsigned int offset,
> unsigned int addr = exar_offset_to_lvl_addr(exar_gpio, offset);
> unsigned int bit = exar_offset_to_bit(exar_gpio, of
On Thu, Nov 05, 2020 at 09:21:13AM -0800, Suren Baghdasaryan wrote:
> On Thu, Nov 5, 2020 at 9:16 AM Michal Hocko wrote:
> >
> > On Thu 05-11-20 08:50:58, Suren Baghdasaryan wrote:
> > > On Thu, Nov 5, 2020 at 4:20 AM Michal Hocko wrote:
> > > >
> > > > On Wed 04-11-20 12:40:51, Minchan Kim wrote
On Thu, Nov 05, 2020 at 12:18:47AM +0100, Andrey Konovalov wrote:
> From: Vincenzo Frascino
>
> When MTE is present, the GCR_EL1 register contains the tags mask that
> allows to exclude tags from the random generation via the IRG instruction.
>
> With the introduction of the new Tag-Based KASAN
On Wed, Nov 04, 2020 at 10:39:13PM +, Ashish Kalra wrote:
> Hello Konrad,
>
> On Wed, Nov 04, 2020 at 05:14:52PM -0500, Konrad Rzeszutek Wilk wrote:
> > On Wed, Nov 04, 2020 at 10:08:04PM +, Ashish Kalra wrote:
> > > From: Ashish Kalra
> > >
> > > For SEV, all DMA to and from guest has t
On Thu, Oct 8, 2020 at 3:08 AM Stanimir Varbanov
wrote:
>
> Hi Rafael,
>
> On 10/7/20 5:37 PM, Rafael J. Wysocki wrote:
> > On Wed, Oct 7, 2020 at 2:20 AM Stanimir Varbanov
> > wrote:
> >>
> >> Calling pm_runtime_put_sync over a device with suppliers with device
> >> link flags PM_RUNTIME | RPM_A
On Thu 05-11-20 09:21:13, Suren Baghdasaryan wrote:
> On Thu, Nov 5, 2020 at 9:16 AM Michal Hocko wrote:
> >
> > On Thu 05-11-20 08:50:58, Suren Baghdasaryan wrote:
> > > On Thu, Nov 5, 2020 at 4:20 AM Michal Hocko wrote:
> > > >
> > > > On Wed 04-11-20 12:40:51, Minchan Kim wrote:
> > > > > On W
On 30/10/2020 12:22, Helen Koike wrote:
> From: Shunqian Zheng
>
> Add the Rockchip ISP1 specific processing parameter format
> V4L2_META_FMT_RK_ISP1_PARAMS and metadata format
> V4L2_META_FMT_RK_ISP1_STAT_3A for 3A.
>
> Signed-off-by: Shunqian Zheng
> Signed-off-by: Jacob Chen
> Signed-off-by
Quoting Michael Roth (2020-11-05 10:24:37)
> Quoting Joerg Roedel (2020-09-07 08:15:02)
> > From: Joerg Roedel
> >
> > Do not allocate a vmcb_control_area and a vmcb_save_area on the stack,
> > as these structures will become larger with future extenstions of
> > SVM and thus the svm_set_nested_s
On 2020-11-05 16:43, Thierry Reding wrote:
On Thu, Sep 24, 2020 at 01:27:25PM +0200, Thierry Reding wrote:
On Tue, Sep 15, 2020 at 02:36:48PM +0200, Thierry Reding wrote:
On Mon, Sep 14, 2020 at 04:08:29PM -0600, Rob Herring wrote:
On Fri, Sep 04, 2020 at 02:59:57PM +0200, Thierry Reding wrote
On Mon, 02 Nov 2020 12:34:58 -0800, Guru Das Srinagesh wrote:
> Add interrupt support for reporting VBUS detection status that can be
> detected via a dedicated PMIC pin.
>
> Signed-off-by: Anirudh Ghayal
> Signed-off-by: Guru Das Srinagesh
> ---
> Documentation/devicetree/bindings/extcon/qcom,
On 30/10/2020 12:22, Helen Koike wrote:
> All the items in the TODO list were addressed, uapi was reviewed,
> documentation written, checkpatch errors fixed, several bugs fixed.
>
> There is no big reason to keep this driver in staging, so move it out.
>
> Signed-off-by: Helen Koike
Mauro held
05.11.2020 19:07, Alan Stern пишет:
> Do you really want to use the same error unwinding for opp_table values
> obtained from dev_pm_opp_set_regulators() as from
> dev_pm_opp_get_opp_table()?
They both are pointing at the same opp_table, which is refcounted.
The dev_pm_opp_set_regulators() is d
On Thu, Nov 5, 2020 at 3:54 AM Lorenz Bauer wrote:
>
> My earlier patch to reject non-zero arguments to flow dissector attach
> broke attaching via bpftool. Instead of 0 it uses -1 for target_fd.
> Fix this by passing a zero argument when attaching the flow dissector.
>
> Fixes: 1b514239e859 ("bpf
On Thu, Nov 05, 2020 at 05:05:59PM +0100, Borislav Petkov wrote:
> On Thu, Nov 05, 2020 at 03:16:15AM +0200, Jarkko Sakkinen wrote:
> > Further, I'd declare this as an inline function given how trivial it
> > turn into.
> >
> ...
>
> So are you sending a new version of only this patch as a reply
On 05/11/2020 17:15, kernel test robot wrote:
> Hi Andre,
>
> I love your patch! Yet something to improve:
>
> [auto build test ERROR on linus/master]
> [also build test ERROR on v5.10-rc2 next-20201105]
> [cannot apply to arm64/for-next/core kvmarm/next arm-perf/for-next/p
idr_init() uses base 0 which is an invalid identifier for this driver.
The new function idr_init_base allows IDR to set the ID lookup from
base 1. This avoids all lookups that otherwise starts from 0 since
0 is always unused.
References: commit 6ce711f27500 ("idr: Make 1-based IDRs more efficient"
This patch fixes NULL pointer dereference due to NULL pcs_config
in pcs_ops.
Reported-by: Nicolas Ferre
Link:
https://lore.kernel.org/netdev/2db854c7-9ffb-328a-f346-f68982723...@microchip.com/
Signed-off-by: Parshuram Thombare
---
drivers/net/ethernet/cadence/macb_main.c | 17 +++--
Add reporting ARM64 CPU cache corrected error count to the ghes_edac.
The error count would be updated in the EDAC CPU cache sysfs
interface.
Signed-off-by: Jonathan Cameron
Signed-off-by: Shiju Jose
---
drivers/acpi/apei/ghes.c | 79 ++--
include/linux/cper.
For the firmware-first error handling on ARM64 hardware platforms,
CPU cache corrected error count is not recorded.
Create an CPU EDAC device and device blocks for the CPU caches
for this purpose. The EDAC device blocks are created based on the
CPU caches information represented in the ACPI PPTT.
Find CPU caches in the ACPI PPTT and add CPU EDAC device
and EDAC device blocks for the caches found.
For the firmware-first error handling, add an interface in the
ghes_edac, enable to report the CPU corrected error count for
a CPU core to the user-space through the CPU EDAC device.
Suggested-by
From: Jonathan Cameron
According to the following sections of the PPTT definition in the
ACPI specification(V6.3), a high level cache node( For example L2 cache)
could be represented simultaneously both in the private resource
of a CPU node and via the next_level_of_cache pointer of a low level
c
Add function acpi_find_cache_info() to find the
information of the caches found in a CPU hierarchy
represented in the PPTT.
Co-developed-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
Signed-off-by: Shiju Jose
---
drivers/acpi/pptt.c | 62 +++
in
05.11.2020 19:07, Alan Stern пишет:
>> +err = devm_tegra_ehci_init_opp_table(&pdev->dev);
>> +if (err)
>> +return dev_err_probe(&pdev->dev, err,
>> + "Failed to initialize OPP\n");
> Why log a second error message? Just return err.
Indeed, thank
On Tue, Nov 03, 2020 at 09:25:48AM +0530, Kishon Vijay Abraham I wrote:
> Add binding for the PLLs within SERDES.
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
> .../bindings/phy/phy-cadence-sierra.yaml | 89 ++-
> 1 file changed, 86 insertions(+), 3 deletions(-)
>
> diff
On Thu, Nov 5, 2020 at 9:44 AM Michal Hocko wrote:
>
> On Thu 05-11-20 09:21:13, Suren Baghdasaryan wrote:
> > On Thu, Nov 5, 2020 at 9:16 AM Michal Hocko wrote:
> > >
> > > On Thu 05-11-20 08:50:58, Suren Baghdasaryan wrote:
> > > > On Thu, Nov 5, 2020 at 4:20 AM Michal Hocko wrote:
> > > > >
>
On Tue 2020-11-03 22:40:23, Matteo Croce wrote:
> From: Matteo Croce
>
> This reverts commit 616feab753972b9751308f3cd2a68fc57eae8edb.
>
> kstrtoint() and simple_strtoul() have a subtle difference which makes
> them non interchangeable: if a non digit character is found amid the
> parsing, the f
On Thursday, November 5, 2020 4:08:30 PM CET Mike Galbraith wrote:
> On Thu, 2020-11-05 at 15:31 +0100, Rafael J. Wysocki wrote:
> > On Monday, November 2, 2020 7:18:41 AM CET Mike Galbraith wrote:
> >
> > > Desktop box did, it gained a working ondemand, while its previously
> > > working powersave
On Wed, 07 Oct 2020 14:51:59 PDT (-0700), Atish Patra wrote:
RISC-V limits the physical memory size by -PAGE_OFFSET. Any memory beyond
that size from DRAM start is unusable. Just remove any memblock pointing
to those memory region without worrying about computing the maximum size.
Signed-off-by:
On Thursday, November 5, 2020 6:14:01 PM CET Srinivas Pandruvada wrote:
> On Thu, 2020-11-05 at 14:53 +1100, Victor Ding wrote:
> > On Wed, Nov 4, 2020 at 1:17 PM Srinivas Pandruvada
> > wrote:
> > > On Wed, 2020-11-04 at 12:43 +1100, Victor Ding wrote:
> > > > On Wed, Nov 4, 2020 at 4:09 AM Srini
On Thu, 05 Nov 2020, Paul Fulghum wrote:
>
> Another candidate for removal is drivers/char/pcmcia/synclink_cs.c
>
> Everything I said about synclink.c/synclinkmp.c is true of that as well: the
> hardware stopped being manufactured decades ago and is not available for
> testing. The possibility
On Mon, 05 Oct 2020 17:17:47 PDT (-0700), Atish Patra wrote:
This series attempts to move the ARM64 numa implementation to common
code so that RISC-V can leverage that as well instead of reimplementing
it again.
RISC-V specific bits are based on initial work done by Greentime Hu [1] but
modified
On Thu, 05 Nov 2020, Tomi Valkeinen wrote:
> On 05/11/2020 16:45, Lee Jones wrote:
> > Fixes the following W=1 kernel build warning(s):
> >
> > drivers/gpu/drm/omapdrm/dss/dsi.c: In function ‘_dsi_print_reset_status’:
> > drivers/gpu/drm/omapdrm/dss/dsi.c:1131:6: warning: variable ‘l’ set but
On Tue 2020-11-03 22:40:24, Matteo Croce wrote:
> From: Matteo Croce
>
> Limit the CPU number to num_possible_cpus(), because setting it
> to a value lower than INT_MAX but higher than NR_CPUS produces the
> following error on reboot and shutdown:
>
> BUG: unable to handle page fault for add
On Thu, Nov 5, 2020 at 6:39 PM Catalin Marinas wrote:
>
> On Thu, Nov 05, 2020 at 06:29:17PM +0100, Andrey Konovalov wrote:
> > On Thu, Nov 5, 2020 at 6:26 PM Catalin Marinas
> > wrote:
> > >
> > > On Thu, Nov 05, 2020 at 12:18:45AM +0100, Andrey Konovalov wrote:
> > > > diff --git a/arch/arm64/
On Tue 2020-11-03 22:40:25, Matteo Croce wrote:
> From: Matteo Croce
>
> Small improvements to the code, without changing the way it works:
> - use a local variable, to avoid a small time lapse where reboot_cpu
> can have an invalid value
> - comment the code which is not easy to understand at
On Thu, Nov 05, 2020 at 07:57:45PM +0200, Jarkko Sakkinen wrote:
> I'll rather send a full patch set if required.
Why if the changes all belong to this patch and why should I take a
patch which clearly needs improving?
Just send the fixed version of this and I can take it now.
Thx.
--
Regards/
On Thu, 05 Nov 2020, Thierry Reding wrote:
> On Thu, Nov 05, 2020 at 02:44:58PM +, Lee Jones wrote:
> > This set is part of a larger effort attempting to clean-up W=1
> > kernel builds, which are currently overwhelmingly riddled with
> > niggly little warnings.
> >
> > There are 5000 warnings
On 2020-11-05 17:43, Hans Verkuil wrote:
On 30/10/2020 12:22, Helen Koike wrote:
From: Shunqian Zheng
Add the Rockchip ISP1 specific processing parameter format
V4L2_META_FMT_RK_ISP1_PARAMS and metadata format
V4L2_META_FMT_RK_ISP1_STAT_3A for 3A.
Signed-off-by: Shunqian Zheng
Signed-off-by:
On Thu, 05 Nov 2020, Sam Ravnborg wrote:
> Hi Lee.
>
> On Thu, Nov 05, 2020 at 02:44:58PM +, Lee Jones wrote:
> > This set is part of a larger effort attempting to clean-up W=1
> > kernel builds, which are currently overwhelmingly riddled with
> > niggly little warnings.
>
> Thanks for looki
Introduce gsi_irq_init() and gsi_irq_exit(), to encapsulate looking
up the GSI IRQ and registering its handler. Call gsi_irq_init() a
little later in gsi_init(), and initialize the completion earlier.
The IRQ handler accesses both the GSI virtual memory pointer and the
completion, and this way the
Most GSI general errors are unrecoverable without a full reset.
Despite that, we want to receive these errors so we can at least
report what happened before whatever undefined behavior ensues.
Explicitly disable all such interrupts in gsi_irq_setup(), then
enable those we want in gsi_irq_enable().
The GSI code is now exposed to IPA version numbers, and we handle
version-specific behavior based on the IPA version.
Modify some comments that talk about GSI versions so they reference
IPA versions instead. Correct version number errors in a couple of
these comments.
The (comment) mapping betwe
Introduce gsi_irq_setup() and gsi_irq_teardown() to disable all
GSI interrupts when first setting up GSI hardware, and to clean
things up when we're done.
Re-enable all GSI interrupt types in gsi_irq_enable(), but do
so only after each of the type-specific interrupt masks has
been configured. Sim
Keep track of the set of GSI interrupt types that are currently
enabled by recording the mask value to write (or last written) to
the TYPE_IRQ_MSK register.
Create a new helper function gsi_irq_type_update() to handle
actually writing the register.
Signed-off-by: Alex Elder
---
drivers/net/ipa/
A GSI channel causes a channel control interrupt to fire whenever
its state changes (between NOT_ALLOCATED, ALLOCATED, STARTED, etc.).
We do not support inter-EE channel commands (initiated by other EEs),
so no channel should ever change state except when we request it to.
Currently, we permit *al
Rename the "event_enable_bitmap" field of the GSI structure to be
"ieob_enabled_bitmap". An upcoming patch will cache the last value
stored for another interrupt mask and this is a more direct naming
convention to follow.
Add a few comments to explain the bitmap fields in the GSI structure.
Sign
It is possible for other execution environments (EEs, like the modem)
to request changes to local (AP) channel or event ring state. We do
not support this feature.
In gsi_irq_setup(), explicitly zero the mask that defines which
channels are permitted to generate inter-EE channel state change
inte
A GSI channel must be started in order to use it to perform a
transfer data (or command) transaction. And the only time we'll see
an IEOB interrupt is if we send a transaction to a started channel.
Therefore we do not need to have the IEOB interrupt type enabled
until at least one channel has been
Now that all of the GSI interrupts are handled uniformly,
change gsi_irq_type_update() so it takes a value. Have the
function assign that value to the cached mask of enabled GSI
IRQ types before writing it to hardware.
Note that gsi_irq_teardown() will only be called after
gsi_irq_disable(), so i
On Thu, Nov 5, 2020 at 7:10 PM Lee Jones wrote:
>
> On Thu, 05 Nov 2020, Thierry Reding wrote:
>
> > On Thu, Nov 05, 2020 at 02:44:58PM +, Lee Jones wrote:
> > > This set is part of a larger effort attempting to clean-up W=1
> > > kernel builds, which are currently overwhelmingly riddled with
701 - 800 of 1657 matches
Mail list logo
