synth_field_size() returns either a positive size or an error (zero or
a negative value). However, the existing code assumes the only error
value is 0. It doesn't handle negative error codes, as it assigns
directly to field->size (a size_t; unsigned), thereby interpreting the
error code as a valid
Hi,
This is v2 of the dynamic string support for synthetic events.
v1 was missing some very important code in the in-kernel API functions
that should have reserved room for dynamic strings. This adds it
along also some additional test code in the synth_event_gen_test
module that tests the dynami
On Wed, Sep 30, 2020 at 10:39 AM Paolo Bonzini wrote:
>
> On 30/09/20 18:57, Sean Christopherson wrote:
> >> +
> >> +static bool __read_mostly tdp_mmu_enabled = true;
> >> +module_param_named(tdp_mmu, tdp_mmu_enabled, bool, 0644);
> > This param should not exist until the TDP MMU is fully function
The variable 'len' has been assigned a value but is not used after that.
So, remove the assignement.
Signed-off-by: Sudip Mukherjee
---
kernel/trace/trace.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index d3c75aab44ad..e13cb3baeff0 100644
---
On Thu, Sep 24, 2020 at 3:13 PM Alessio Balsini wrote:
>
> Add a reference to the FUSE daemon credentials, so that they can be used to
> temporarily raise the user credentials when accessing lower file system
> files in passthrough.
Hmm, I think it would be better to store the creds of the ioctl(
On Tue, Sep 15 2020 at 16:28, Dave Jiang wrote:
> struct idxd_device {
> @@ -170,6 +171,7 @@ struct idxd_device {
>
> int num_groups;
>
> + u32 ims_offset;
> u32 msix_perm_offset;
> u32 wqcfg_offset;
> u32 grpcfg_offset;
> @@ -177,6 +179,7 @@ struct idxd_device {
>
On Wed, Sep 30, 2020 at 01:08:27PM +, Derrick, Jonathan wrote:
> +Megha
>
> On Wed, 2020-09-30 at 09:57 -0300, Jason Gunthorpe wrote:
> > On Wed, Sep 30, 2020 at 12:45:30PM +, Derrick, Jonathan wrote:
> > > Hi Jason
> > >
> > > On Mon, 2020-08-31 at 11:39 -0300, Jason Gunthorpe wrote:
> >
struct at91_cf_data is only used in the driver since all the platforms moved
to device tree, move its definition locally.
Signed-off-by: Alexandre Belloni
---
drivers/pcmcia/at91_cf.c| 11 +++
include/linux/platform_data/atmel.h | 12
2 files changed, 11 insertio
Board file support has been removed for at91rm9200 back in 2014, make the
CF driver DT only.
Signed-off-by: Alexandre Belloni
---
drivers/pcmcia/Kconfig | 1 +
drivers/pcmcia/at91_cf.c | 38 --
2 files changed, 9 insertions(+), 30 deletions(-)
diff --git a
On Wed, Sep 30, 2020 at 2:47 AM Tony Lindgren wrote:
>
> * Trent Piepho [200930 09:34]:
> >
> > Where do these flags go? In pinctrl-single,pins? Like:
> >
> > pinctrl-single,pins = ;
> >
> > But PIN_INPUT_PULLUP is a generic flag? Which is translated into the
> > proper value by??
>
> Yes tha
On Thu, Sep 24, 2020 at 3:13 PM Alessio Balsini wrote:
>
> All the read and write operations performed on fuse_files which have the
> passthrough feature enabled are forwarded to the associated lower file
> system file via VFS.
>
> Sending the request directly to the lower file system avoids the u
On Wed, Sep 30, 2020 at 08:47:00PM +0200, Thomas Gleixner wrote:
> > + pci_read_config_dword(pdev, SIOVCAP(dvsec), &val32);
> > + if ((val32 & 0x1) && idxd->hw.gen_cap.max_ims_mult) {
> > + idxd->ims_size = idxd->hw.gen_cap.max_ims_mult * 256ULL;
> > + dev_dbg(dev, "IMS siz
On Fri, Sep 25, 2020 at 5:22 PM Paolo Bonzini wrote:
>
> On 25/09/20 23:22, Ben Gardon wrote:
> > Move the code to allocate a struct kvm_mmu_page for the TDP MMU out of the
> > root allocation code to support allocating a struct kvm_mmu_page for every
> > page of page table memory used by the TDP
On Thu, Sep 24, 2020 at 3:13 PM Alessio Balsini wrote:
>
> Extend the passthrough feature by handling asynchronous IO both for read
> and write operations.
>
> When an AIO request is received, if the request targets a FUSE file with
> the passthrough functionality enabled, a new identical AIO requ
Make a common helper from the code in tests nvme/012 and nvme/013
to run an fio verify on a XFS file system backed by the
specified block device.
While we are at it, all the output is redirected to $FULL instead of
/dev/null.
Signed-off-by: Logan Gunthorpe
---
common/xfs | 22 ++
Test that we can remove a subsystem that has not been enabled by
passthru or any ns. Do the same for ports while we are at it.
This was an issue in the original passthru patches and is
not commonly tested. So this test will ensure we don't regress this.
Signed-off-by: Logan Gunthorpe
---
tests/
This ensures we find the correct nvme loop device if others exist on a
given system (which is generally not expected on test systems).
Additionally, this will be required in the upcomming test nvme/037 which
will have controllers racing with ones being destroyed.
Signed-off-by: Logan Gunthorpe
-
Similar to test nvme/010 and nvme/011 but for a passthru controller
Signed-off-by: Logan Gunthorpe
---
tests/nvme/034 | 35 +++
tests/nvme/034.out | 3 +++
2 files changed, 38 insertions(+)
create mode 100755 tests/nvme/034
create mode 100644 tests/nvme/034
Add some simple helpers to setup a passthru target that passes through
to a nvme test device.
Signed-off-by: Logan Gunthorpe
---
tests/nvme/rc | 76 +++
1 file changed, 76 insertions(+)
diff --git a/tests/nvme/rc b/tests/nvme/rc
index dfa57a299625
Similar to test nvme/031 except for passthru controllers.
Note: it's normal to get I/O errors in this test as when the controller
disconnects it races with the partition table read.
Signed-off-by: Logan Gunthorpe
---
tests/nvme/037 | 35 +++
tests/nvme/037.ou
This tests creates and connects to a passthru controller backed
by a test NVMe namespace. It then verifies that some common fields
in id-ctrl and id-ns are the same in the target and the orginial
device.
Signed-off-by: Logan Gunthorpe
---
tests/nvme/033 | 67 +
This is a similar test as nvme/012 and nvme/013, except with a
passthru controller.
Signed-off-by: Logan Gunthorpe
---
tests/nvme/035 | 37 +
tests/nvme/035.out | 3 +++
2 files changed, 40 insertions(+)
create mode 100755 tests/nvme/035
create mode 100
Instead of each individual test removing this file, just do it
in the common helper.
Signed-off-by: Logan Gunthorpe
Reviewed-by: Chaitanya Kulkarni
---
common/fio | 1 +
tests/nvme/010 | 1 -
tests/nvme/011 | 1 -
tests/nvme/012 | 1 -
tests/nvme/013 | 1 -
5 files changed, 1 insertion(+),
Similar to test 022 but for passthru controllers.
Signed-off-by: Logan Gunthorpe
---
tests/nvme/036 | 37 +
tests/nvme/036.out | 3 +++
2 files changed, 40 insertions(+)
create mode 100755 tests/nvme/036
create mode 100644 tests/nvme/036.out
diff --git
Two nvme tests create and mount XFS filesystems and check for mkfs.xfs.
They should also check for XFS support in the kernel so create a common
helper for this.
Signed-off-by: Logan Gunthorpe
---
common/rc | 8
common/xfs | 11 +++
tests/nvme/012 | 6 --
tests/nv
Hi,
This series adds blktests for the nvmet passthru feature that was merged
for 5.9. It's been reconciled with Sagi's blktest series that Omar
recently merged.
This series is based off of the current blktests master and a git repo is
available for this here:
https://github.com/Eideticom/blktest
DW APB SSI controller can be used by the two SPI core interfaces:
traditional SPI transfers and SPI memory operations. The controller needs
to be accordingly configured at runtime when the corresponding operations
are executed. In order to do that for the both interfaces from a single
function we i
The Tx and Rx data write/read procedure can be significantly simplified by
using Tx/Rx transfer lengths instead of the end pointers. By having the
Tx/Rx data leftover lengths (in the number of transfer words) we can get
rid of all subtraction and division operations utilized here and there in
the t
The SPI bus speed update functionality will be useful in another parts of
the driver too (like to implement the SPI memory operations and from the
DW SPI glue layers). Let's move it to the update_cr0() method then and
since the later is now updating not only the CTRLR0 register alter its
prototype
Aside from the synchronous Tx-Rx mode, which has been utilized to create
the normal SPI transfers in the framework of the DW SSI driver, DW SPI
controller supports Tx-only and EEPROM-read modes. The former one just
enables the controller to transmit all the data from the Tx FIFO ignoring
anything r
These controllers are based on the DW APB SSI IP-core and embedded into
the SoC, so two of them are equipped with IRQ, DMA, 64 words FIFOs and 4
native CS, while another one as being utilized by the Baikal-T1 System
Boot Controller has got a very limited resources: no IRQ, no DMA, only a
single nat
It's theoretically erroneous to enable IRQ before the chip is turned on.
If IRQ handler gets executed before the chip is enabled, then any data
written to the Tx FIFO will be just ignored.
I say "theoretically" because we haven't noticed any problem with that,
but let's fix it anyway just in case.
Currently DWC SSI core is supported by means of setting up the
core-specific update_cr0() callback. It isn't suitable for multiple
reasons. First of all having exported several methods doing the same thing
but for different chips makes the code harder to maintain. Secondly the
spi-dw-core driver ex
Rx sample delay can be SPI device specific, and should be synchronously
initialized with the rest of the communication and peripheral device
related controller setups. So let's move the Rx-sample delay setup into
the DW APB SSI configuration update method.
Signed-off-by: Serge Semin
---
drivers/
It's pointless to enable the chip back if the DMA setup procedure fails,
since we'll disable it on the next transfer anyway. For the same reason We
don't do that in case of a failure detected in any other methods called
from the transfer_one() method.
While at it consider any non-zero value return
Originally I intended to merge a dedicated Baikal-T1 System Boot SPI
Controller driver into the kernel and leave the DW APB SSI driver
untouched. But after a long discussion (see the link at the bottom of the
letter) Mark and Andy persuaded me to integrate what we developed there
into the DW APB SS
Baikal-T1 is equipped with three DW APB SSI-based MMIO SPI controllers.
Two of them are pretty much normal: with IRQ, DMA, FIFOs of 64 words
depth, 4x CSs, but the third one as being a part of the Baikal-T1 System
Boot Controller has got a very limited resources: no IRQ, no DMA, only a
single nativ
Simplify the dw_spi_add_host() method a bit by replacing the currently
implemented default set_cs callback setting up and later having it
overwritten by a custom function with direct if-else-based callback
assignment.
Signed-off-by: Serge Semin
---
Changelog v2:
- Replace the ternary operator w
On Wed, 2020-09-30 at 18:41 +0200, Sedat Dilek wrote:
> On Tue, Sep 29, 2020 at 9:25 PM 'Nick Desaulniers' via Clang Built
> Linux wrote:
> > The stringification operator, `#`, in the preprocessor escapes strings.
> > For example, `# "foo"` becomes `"\"foo\""`. GCC and Clang differ in how
> > the
The parameter will be needed for another wait-done method being added in
the framework of the SPI memory operation modification in a further
commit.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 5 ++---
drivers/spi/spi-dw.h | 2 ++
2 files changed, 4 insertions(+), 3 deletions(-
By design of the currently available native set_cs callback, the CS
de-assertion will be done only if it's required by the corresponding
controller capability. But in order to pre-fill the Tx FIFO buffer with
data during the SPI memory ops execution the SER register needs to be left
cleared before
In order to make the transfer_one() callback method more readable and
for unification with the DMA-based transfer, let's detach the IRQ setup
procedure into a dedicated function. While at it rename the IRQ-based
transfer handler function to be dw_spi-prefixe and looking more like the
DMA-related on
A functionality of the poll-based transfer has been removed by
commit 1ceb09717e98 ("spi: dw: remove cs_control and poll_mode members
from chip_data") with a justification that "there is no user of one
anymore". It turns out one of our DW APB SSI core is synthesized with no
IRQ line attached and th
In some circumstances the current implementation of the SPI memory
operations may occasionally fail even though they are executed in the
atomic context. This may happen if the system bus is relatively slow in
comparison to the SPI bus frequency, or there is a concurrent access to
it, which makes th
The variable 'env_start' has only been used for the if condition before
this assignment and is never read after this.
So, remove the assignement.
Signed-off-by: Sudip Mukherjee
---
fs/proc/base.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/proc/base.c b/fs/proc/base.c
The DW SSI errors handling method can be generically implemented for all
types of the transfers: IRQ, DMA and poll-based ones. It will be a
function which checks the overflow/underflow error flags and resets the
controller if any of them is set. In the framework of this commit we make
use of the ne
Indeed there is no point in detecting the SPI peripheral device parameters
and initializing the CR0 register fields each time an SPI transfer is
executed. Instead let's define a dedicated CR0 chip-data member, which
will be initialized in accordance with the SPI device settings at the
moment of set
Current IRQ-based SPI transfer execution procedure doesn't work well at
the final stage of the execution. If all the Tx data is sent out (written
to the Tx FIFO) but there is some data left to receive, the Tx FIFO Empty
IRQ will constantly happen until all of the requested inbound data is
received.
SPI memory operations implementation will require to have the CS register
cleared before executing the operation in order not to have the
transmission automatically started prior the Tx FIFO is pre-initialized.
Let's clear the register then on explicit controller reset to fulfil the
requirements in
The code currently responsible for the SPI communication speed setting up
is a bit messy. Most likely for some historical reason the bus frequency
is saved in the peripheral chip private data. It's pointless now since the
custom communication speed is a SPI-transfer-specific thing and only if
there
The following changes since commit d2249bf25c565b6e310453962fef63f8d38677a6:
clk: qcom: lpass: Correct goto target in lpass_core_sc7180_probe()
(2020-09-10 13:42:35 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
tags/clk-fixes-f
Hi,
This series adds support for Octal DTR flashes in the SPI NOR framework,
and then adds hooks for the Cypress Semper and Micron Xcella flashes to
allow running them in Octal DTR mode. This series assumes that the flash
is handed to the kernel in Legacy SPI mode.
Tested on Micron MT35X and S28H
ENOTSUPP is not a SUSV4 error code. Using EOPNOTSUPP is preferred
in its stead.
Reviewed-by: Tudor Ambarus
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi-nor/core.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor
From: Tudor Ambarus
Parse just the 22nd dword and look for the 'DTR Octal Mode Enable
Volatile bit'.
SPI_NOR_IO_MODE_EN_VOLATILE should be set just for the flashes
that don't define the optional SFDP SCCR Map. For the others,
let the SFDP do its job and fill the SNOR_F_IO_MODE_EN_VOLATILE
flag.
Double Transfer Rate (DTR) is SPI protocol in which data is transferred
on each clock edge as opposed to on each clock cycle. Make
framework-level changes to allow supporting flashes in DTR mode.
Right now, mixed DTR modes are not supported. So, for example a mode
like 4S-4D-4D will not work. All
They are thin wrappers around
nor->controller_ops->{read_reg,write_reg,erase}(). In a future commit
DTR support will be added. These ops can not be supported by the
controller_ops hooks and these helpers will make it easier to reject
those calls.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi
Some devices in DTR mode expect an extra command byte called the
extension. The extension can either be same as the opcode, bitwise
inverse of the opcode, or another additional byte forming a 16-byte
opcode. Get the extension type from the BFPT. For now, only flashes with
"repeat" and "inverse" ext
Some controllers, like the cadence qspi controller, have trouble reading
only 1 byte in DTR mode. So, do 2 byte reads for SR and FSR commands in
DTR mode, and then discard the second byte.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi-nor/core.c | 15 +--
1 file changed, 13 inser
This table is indication that the flash is xSPI compliant and hence
supports octal DTR mode. Extract information like the fast read opcode,
dummy cycles, the number of dummy cycles needed for a Read Status
Register command, and the number of address bytes needed for a Read
Status Register command.
Allow flashes to specify a hook to enable octal DTR mode. Use this hook
whenever possible to get optimal transfer speeds.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi-nor/core.c | 35 +++
drivers/mtd/spi-nor/core.h | 2 ++
2 files changed, 37 insertions(+)
The xSPI Profile 1.0 table specifies how many dummy cycles and address
bytes are needed for the Read Status Register command in octal DTR mode.
Use that information to send the correct Read SR command.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi-nor/core.c | 10 ++
1 file changed,
From: Tudor Ambarus
We don't want to enter a stateful mode, where a X-X-X I/O mode
is entered by setting a non-volatile bit, because in case of a
reset or a crash, once in the non-volatile mode, we may not be able
to recover in bootloaders and we may break the SPI NOR boot.
Forbid by default the
The following commit has been merged into the perf/core branch of tip:
Commit-ID: f797f05d917ffef94249ee0aec4c14a5b50517b2
Gitweb:
https://git.kernel.org/tip/f797f05d917ffef94249ee0aec4c14a5b50517b2
Author:Alexander Antonov
AuthorDate:Mon, 28 Sep 2020 13:21:33 +03:00
Commi
The following commit has been merged into the perf/core branch of tip:
Commit-ID: dbfd638889a0396f5fe14ff3cc2263ec1e1cac62
Gitweb:
https://git.kernel.org/tip/dbfd638889a0396f5fe14ff3cc2263ec1e1cac62
Author:Kan Liang
AuthorDate:Mon, 28 Sep 2020 05:30:41 -07:00
Committer:
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 8191016a026b8dfbb14dea64efc8e723ee99fe65
Gitweb:
https://git.kernel.org/tip/8191016a026b8dfbb14dea64efc8e723ee99fe65
Author:Kan Liang
AuthorDate:Mon, 28 Sep 2020 06:32:40 -07:00
Committer:
A Soft Reset sequence will return the flash to Power-on-Reset (POR)
state. It consists of two commands: Soft Reset Enable and Soft Reset.
Find out if the sequence is supported from BFPT DWORD 16.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi-nor/core.h | 1 +
drivers/mtd/spi-nor/sfdp.c | 4 +
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 010cb00265f150bf82b23c02ad1fb87ce5c781e1
Gitweb:
https://git.kernel.org/tip/010cb00265f150bf82b23c02ad1fb87ce5c781e1
Author:Kan Liang
AuthorDate:Mon, 28 Sep 2020 06:47:26 -07:00
Committer:
The following commit has been merged into the perf/core branch of tip:
Commit-ID: c3bb8a9fa31b99f5b7d2e45cd0a10db91349f4c9
Gitweb:
https://git.kernel.org/tip/c3bb8a9fa31b99f5b7d2e45cd0a10db91349f4c9
Author:Kan Liang
AuthorDate:Mon, 28 Sep 2020 05:30:42 -07:00
Committer:
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 8abbcfefb5f7afabab4578bedd7cd400800cb039
Gitweb:
https://git.kernel.org/tip/8abbcfefb5f7afabab4578bedd7cd400800cb039
Author:Kan Liang
AuthorDate:Fri, 25 Sep 2020 06:49:03 -07:00
Committer:
On resume, the init procedure will be run that will re-enable it.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi-nor/core.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 9de811b33125..17b6f833e920 100644
---
Since this flash doesn't have a Profile 1.0 table, the Octal DTR
capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D
fast read settings.
Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency of 200Mhz.
The flash supports the soft reset
The Cypress Semper flash is an xSPI compliant octal DTR flash. Add
support for using it in octal DTR mode.
The flash by default boots in a hybrid sector mode. But the sector map
table on the part I had was programmed incorrectly and the SMPT values
on the flash don't match the public datasheet. Sp
The following commit has been merged into the perf/core branch of tip:
Commit-ID: ee139385432e919f4d1f59b80edbc073cdae1391
Gitweb:
https://git.kernel.org/tip/ee139385432e919f4d1f59b80edbc073cdae1391
Author:Kan Liang
AuthorDate:Fri, 25 Sep 2020 06:49:05 -07:00
Committer:
Perform a Soft Reset on shutdown on flashes that support it so that the
flash can be reset to its initial state and any configurations made by
spi-nor (given that they're only done in volatile registers) will be
reset. This will hand back the flash in pristine state for any further
operations on it
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 8f5d41f3a0f495435c88ebba8fc150c931c10fef
Gitweb:
https://git.kernel.org/tip/8f5d41f3a0f495435c88ebba8fc150c931c10fef
Author:Kan Liang
AuthorDate:Fri, 25 Sep 2020 06:49:04 -07:00
Committer:
Document vendor prefix for MicroSys Electronics GmbH.
Signed-off-by: Krzysztof Kozlowski
---
Changes since v1:
1. New patch
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml
b
Document and adjust the compatibles for i.MX25 and i.MX27 based boards
to fix dtbs_check warnings like:
arch/arm/boot/dts/imx27-apf27dev.dt.yaml: /: compatible:
['armadeus,imx27-apf27dev', 'armadeus,imx27-apf27', 'fsl,imx27'] is not
valid under any of the given schemas
Signed-off-by: Krzys
Document vendor prefix for Revotics (Revolution Robotics, Inc.).
Signed-off-by: Krzysztof Kozlowski
---
Changes since v1:
1. New patch
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefi
Document and adjust the compatibles for i.MX53 based boards.
Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Rob Herring
---
Changes since v1:
1. Add missed: fsl,imx53-qsrb, karo,tx53, kiebackpeter,imx53-ddc,
kiebackpeter,imx53-hsc, aries,imx53-m53evk and denx,imx53-m53evk
2. Add Review (assum
Hi,
Changes since v1:
1. Drop applied vendor-prefix patches.
2. Add Reviews from Rob.
3. Use ABB prefix for Aristainetos boards.
4. Add missed compatibles for i.MX51, i.MX53 and i.MX6DL.
5. Fix typo (VF600 -> VF610) in VF boards.
6. New vendor prefixes (patches): #1 and #2.
Best regards,
Krzyszto
Document and adjust the compatibles for i.MX51 based boards.
Signed-off-by: Krzysztof Kozlowski
Acked-by: Rob Herring
---
Changes since v1:
1. Add missed: zii,imx51-scu2-mezz and zii,imx51-rdu1
2. Add Ack
---
.../devicetree/bindings/arm/fsl.yaml | 26 ---
1 file chang
Document and adjust the compatibles for i.MX6DL based boards.
Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Rob Herring
---
Changes since v1:
1. Add missed: solidrun,cubox-i/dl, solidrun,hummingboard2/dl.
2. Fix Toradex (multiple compatibles).
3. Add Review (assuming changes are not signific
The Aristainetos and Aristainetos2 boards have only SoC compatible.
Cc: Heiko Schocher
Signed-off-by: Krzysztof Kozlowski
---
Changes since v1:
1. Use ABB vendor prefix
---
arch/arm/boot/dts/imx6dl-aristainetos2_4.dts | 2 +-
arch/arm/boot/dts/imx6dl-aristainetos2_7.dts | 2 +-
arch/arm/boot/
Document binding for ABB.
Cc: Heiko Schocher
Signed-off-by: Krzysztof Kozlowski
---
Changes since v1:
1. Use ABB vendor prefix
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yam
Document and adjust the compatibles for i.MX6Q based boards.
The Toradex Boards use multiple compatibles.
Signed-off-by: Krzysztof Kozlowski
---
.../devicetree/bindings/arm/fsl.yaml | 56 +--
1 file changed, 50 insertions(+), 6 deletions(-)
diff --git a/Documentation/de
syzbot has bisected this issue to:
commit 13fcc6837049f1bd76d57e9abc217a91fdbad764
Author: David Howells
Date: Thu Nov 1 23:07:27 2018 +
afs: Add fs_context support
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=13ea9ea790
start commit: 49e7e3e9 Add linux-next spec
There are four flavors of TechNexion PICO-IMX6 boards. They have their
own DTSes, even though in Dwarf, Nymph and Pi are exactly the same.
They also have their own bindings so adjust the compatibles to match the
bindings.
Signed-off-by: Krzysztof Kozlowski
---
Changes since v1:
1. None
---
ar
Document and adjust the compatibles for i.MX6DL based Aristainetos
boards from ABB.
Cc: Heiko Schocher
Signed-off-by: Krzysztof Kozlowski
---
Changes since v1:
1. Use ABB vendor prefix
---
Documentation/devicetree/bindings/arm/fsl.yaml | 4
1 file changed, 4 insertions(+)
diff --git a/D
On Pinebook Pro laptops with an NVMe SSD installed, prevent random
crashes in the NVMe driver by not attempting to use a PCIe link speed
higher than that supported by the RK3399 SoC.
See commit 712fa1777207 ("arm64: dts: rockchip: add max-link-speed for
rk3399").
Fixes: 5a65505a6988 ("arm64: dts:
On Wed, Sep 30, 2020 at 08:18:18PM +0800, Boqun Feng wrote:
> For one thing, I do think that LOCK_READ_USED trace is helpful for
> better reporting, because if there is a read lock in the dependency path
> which causes the deadlock, it's better to have the LOCK_READ_USED trace
> to know at least t
On Wed, Sep 30, 2020 at 09:01:43PM +0200, Krzysztof Kozlowski wrote:
> Document and adjust the compatibles for i.MX6Q based boards.
> The Toradex Boards use multiple compatibles.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> .../devicetree/bindings/arm/fsl.yaml | 56 +--
On Wed, Sep 30, 2020 at 05:47:43PM +0800, Jisheng Zhang wrote:
> Hi,
>
> A GE phy supports pad isolation which can save power in WOL mode. But once the
> isolation is enabled, the MAC can't send/receive pkts to/from the phy because
> the phy is "isolated". To make the PHY work normally, I need to
On Wed, 30 Sep 2020 20:13:23 +0200
Peter Zijlstra wrote:
> diff --git a/include/linux/lockdep.h b/include/linux/lockdep.h
> > index 6a584b3e5c74..3e5bc1dd71c6 100644
> > --- a/include/linux/lockdep.h
> > +++ b/include/linux/lockdep.h
> > @@ -550,7 +550,8 @@ do {
On Wed, Sep 30, 2020 at 10:13 AM Peter Zijlstra wrote:
>
> On Wed, Sep 30, 2020 at 11:10:36AM -0500, Segher Boessenkool wrote:
>
> > Since this variable is a local register asm, on entry to the asm the
> > compiler guarantees that the value lives in the assigned register (the
> > "r8" hardware reg
ction("foo"))) uses to __section("foo")
even if the __attribute__ has multiple list entry forms.
Signed-off-by: Joe Perches
---
This is the current output from the script against next-20200930
attached in this link:
https://lore.kernel.org/lkml/0e582a7f5144a33f465978d97701
On Wed, Sep 30, 2020 at 08:28:17AM -0700, Doug Anderson wrote:
> > The 2nd issue is where do extra properties for a device go. That's
> > nothing new nor special to USB. They go with the device node. We
> > already went thru that with the last attempt.
> >
> > So for this case, we'd have something
On Wed, Sep 30, 2020 at 1:00 PM Doug Anderson wrote:
>
> Hi,
>
> > On Wed, Sep 30, 2020 at 7:44 AM Rob Herring wrote:
> > >
> > > We already have hubs in DT. See [1][2][3][4]. What's new here?
>
> After I sent my response I kept thinking about this and I realized
> that I have prior art I can poi
On Wed, Sep 30, 2020 at 03:10:26PM -0400, Steven Rostedt wrote:
> On Wed, 30 Sep 2020 20:13:23 +0200
> Peter Zijlstra wrote:
>
> > diff --git a/include/linux/lockdep.h b/include/linux/lockdep.h
> > > index 6a584b3e5c74..3e5bc1dd71c6 100644
> > > --- a/include/linux/lockdep.h
> > > +++ b/include/
> yes it shows the bottleneck but it is quite artificial. Read data is
> usually processed and/or written back and that changes the picture a
> lot.
Apologies for reviving an ancient thread (and apologies in advance for my lack
of knowledge on how mailing lists work), but I'd like to offer up anoth
In the function ravb_hwtstamp_get() in ravb_main.c with the existing
values for RAVB_RXTSTAMP_TYPE_V2_L2_EVENT (0x2) and RAVB_RXTSTAMP_TYPE_ALL
(0x6)
if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
else if (priv->tstamp_rx_ctrl
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