On Mon, 2020-09-28 at 15:49 +0530, Srinivasan Raju wrote:
> This introduces the pureLiFi LiFi driver for LiFi-X, LiFi-XC
> and LiFi-XL USB devices, which provide lightweight, highspeed secure and
> fully networked wireless communications via light.
trivial notes:
> diff --git a/drivers/net/wirele
On Mon, Sep 28, 2020 at 01:46:55PM +0200, Paul Cercueil wrote:
>> dma_mmap_attrs can only be used on allocations from dma_mmap_attrs with
>> the same attrs. As there is no allocation using DMA_ATTR_NON_CONSISTENT
>> in the drm core, something looks very fishy here.
>
> Is that a fact? I don't see
On Wed, 02 Sep 2020, Luca Ceresoli wrote:
> Also apply a few smaller improvements:
>
> - document that the only possible I2C slave address is 0x60 as per the
>datasheet and fix the second example accordingly
> - The definition of "xxx-in-supply" was generic, thus define in detail the
>p
On Mon, Sep 28, 2020 at 03:25:48PM +0530, Kanchan Joshi wrote:
> Changes since v1:
> - applied the refactoring suggested by Damien
>
> Kanchan Joshi (1):
> null_blk: synchronization fix for zoned device
>
> drivers/block/null_blk.h | 1 +
> drivers/block/null_blk_zoned.c | 22 ++
On 9/27/2020 10:43 PM, Kuppuswamy, Sathyanarayanan wrote:
>> 2. no bus reset on NON_FATAL error through AER driver path.
>> This already tells me that you need to split your change into
>> multiple patches.
>>
>> Let's talk about this too. bus reset should be triggered via
>> AER driver before info
On Wed, 02 Sep 2020, Luca Ceresoli wrote:
> Add the LP87524-Q1 to the bindings along with an example. This is a variant
> of the LP87565-Q1 and LP87561-Q1 chips which already have bindings.
>
> Signed-off-by: Luca Ceresoli
>
> ---
>
> Changes in v5:
> - describe the "regulators" node too (Rob
On Wed, 02 Sep 2020, Luca Ceresoli wrote:
> Add support for the LP87524B/J/P-Q1 Four 4-MHz Buck Converter. This is a
> variant of the LP87565 having 4 single-phase outputs and up to 10 A of
> total output current.
>
> Signed-off-by: Luca Ceresoli
> Acked-for-MFD-by: Lee Jones
>
> ---
>
> Chan
>From what I can tell from looking at the code:
SPARC's arch_validate_prot() looks up the VMA and peeks at it; that's
not permitted though. do_mprotect_pkey() calls arch_validate_prot()
before taking the mmap lock, so we can hit use-after-free reads if
someone concurrently deletes a VMA we're look
On 2020/9/28 20:05, Wei Xu wrote:
> Hi Zhen Lei,
>
> Thanks!
>
> On 2020/9/27 14:21, Zhen Lei wrote:
>> Convert Hisilicon SoC bindings to DT schema format using json-schema.
>>
>> Signed-off-by: Zhen Lei
>> ---
>> .../bindings/arm/hisilicon/hisilicon.txt | 57
>> .
On Mon, 28 Sep 2020 at 13:57, Leizhen (ThunderTown)
wrote:
>
>
>
> On 2020/9/28 18:14, Ard Biesheuvel wrote:
> > On Mon, 28 Sep 2020 at 11:27, Zhen Lei wrote:
> >>
> >> mov r4, pc
> >> and r4, r4, #0xf800 //truncated to 128MiB boundary
> >> add r4, r4, #TEXT_OFFSET//PA(_st
On Mon, Sep 28, 2020 at 11:36:57AM +0530, Ajay Kaher wrote:
> > @@ -3378,7 +3054,6 @@ static const struct consw fb_con = {
> > .con_font_default = fbcon_set_def_font,
> > .con_font_copy = fbcon_copy_font,
> > .con_set_palette= fbcon_set_palette,
> > - .con_scrol
On 9/28/2020 7:17 AM, Sinan Kaya wrote:
> This should remove/rescan logic should be inside DPC's slot_reset()
> function BTW. Not here.
Correct function name is dpc_handler().
I hope I did not create confusion with slot_reset() that gets called for
each driver post recovery.
Em Thu, Sep 24, 2020 at 09:44:53PM +0900, Namhyung Kim escreveu:
> The metricgroup__copy_metric_events() is to handle metrics events when
> expanding event for cgroups. As the metric events keep pointers to
> evsel, it should be refreshed when events are cloned during the
> operation.
>
> The per
Em Fri, Sep 25, 2020 at 03:01:03PM +0200, Jiri Olsa escreveu:
> On Thu, Sep 24, 2020 at 05:39:03PM -0700, Ian Rogers wrote:
> > perf_event_attr bp_addr is a u64. parse-events.y parses it as a u64, but
> > casts it to a void* and then parse-events.c casts it back to a u64.
> > Rather than all the ca
Em Wed, Sep 23, 2020 at 04:37:08PM -0700, Nick Desaulniers escreveu:
> On Wed, Sep 23, 2020 at 2:07 PM 'Ian Rogers' via Clang Built Linux
> wrote:
> >
> > Ensure 'st' is initialized before an error branch is taken.
> > Fixes test "67: Parse and process metrics" with LLVM msan:
> > ==6757==WARNING:
On Mon, Sep 28, 2020 at 02:29:34PM +0800, Shuo A Liu wrote:
> On Mon 28.Sep'20 at 7:25:16 +0200, Greg Kroah-Hartman wrote:
> > On Mon, Sep 28, 2020 at 11:50:30AM +0800, Shuo A Liu wrote:
> > > > > + write_lock_bh(&acrn_vm_list_lock);
> > > > > + list_add(&vm->list, &acrn_vm_list);
> > > >
Hi Jordan,
On 2020-09-23 20:33, Jordan Crouse wrote:
On Tue, Sep 22, 2020 at 11:48:17AM +0530, Sai Prakash Ranjan wrote:
From: Sharat Masetty
The last level system cache can be partitioned to 32 different
slices of which GPU has two slices preallocated. One slice is
used for caching GPU buffe
On 2020-09-23 20:54, Robin Murphy wrote:
On 2020-09-22 07:18, Sai Prakash Ranjan wrote:
Use table and of_match_node() to match qcom implementation
instead of multiple of_device_compatible() calls for each
QCOM SMMU implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-s
Good day my good friend.
How are you doing today? It has been long i hear from you, what is going on
your side? Today i am very much happy to inform you about my success in
getting those inheritance funds transferred under the co-operation of a new
partner from India Asia. He is a Canadian but bas
Commit 7f3d176f5f7e "tpm: Require that all digests are present in
TCG_PCR_EVENT2 structures" causes a null pointer dereference on all laptops I
have:
[0.00] microcode: microcode updated early to revision 0xd6, date =
2020-04-27
[0.00] Linux version 5.8.0-rc6+ (gcc (Ubuntu 10.2.0
Em Fri, Sep 25, 2020 at 04:26:19PM +0200, Jiri Olsa escreveu:
> On Thu, Sep 24, 2020 at 11:46:32PM +0900, Namhyung Kim wrote:
> > On Thu, Sep 24, 2020 at 03:44:44PM +0200, Jiri Olsa wrote:
> > > On Thu, Sep 24, 2020 at 10:20:51PM +0900, Namhyung Kim wrote:
> > > > On Thu, Sep 24, 2020 at 10:09 PM J
From: Colin Ian King
There is a spelling mistake in a dev_err message. Fix it.
Signed-off-by: Colin Ian King
---
drivers/spi/spi-hisi-sfc-v3xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-hisi-sfc-v3xx.c b/drivers/spi/spi-hisi-sfc-v3xx.c
index 46454dc2d
On 07.09.2020 12:16, Eugen Hristev - M18282 wrote:
> On 31.08.2020 11:50, Sakari Ailus wrote:
>
>> Hi Eugen,
>>
>> Thanks for the update.
>
> Hi Sakari,
>
> Thanks for reviewing, but, could you please help me understand your
> review below ?
>
Gentle ping
Thanks
>>
>> On Wed, Aug 26, 2020 at
Patch change the functions and objects names in reusable code.
The reusable code includes core.c, core.h, drd.c and drd.h files.
It also changes the names of all references to these functions and
objects in other cdns3 files. There are a lot of changes, but all
changes are very trivial.
The reason
Patch splits file core.c into core.c containing the common reusable code
and cnd3-plat.c containing device platform specific code. These changes
are required to make possible reuse DRD part of CDNS3 driver in CDNSP
driver.
Signed-off-by: Pawel Laszczak
---
drivers/usb/cdns3/Makefile | 2 +-
Patch changes the type for gadget_dev pointer in cdns structure from
pointer to cdns3_device structure to void pointer.
This filed is in reusable code and after this change it will be used to
point to both cdns3_device or cdnsp_device objects.
Signed-off-by: Pawel Laszczak
---
drivers/usb/cdns3/
Patch adds the series of tracepoints that can be used for
debugging issues detected in driver.
Signed-off-by: Pawel Laszczak
---
drivers/usb/cdnsp/Makefile | 5 +
drivers/usb/cdnsp/debug.h | 583 +
drivers/usb/cdnsp/ep0.c| 24 +-
drivers/usb/cdnsp/gadget.c | 75 +
Patch adds support for Cadence DRD Super Speed Plus controller(CDNSP).
CDNSP DRD is a part of Cadence CDNSP controller.
The DRD CDNSP controller has a lot of difference on hardware level but on
software level is quite compatible with CDNS3 DRD. For this reason
CDNS3 DRD part of CDNS3 driver was reu
This patch introduce new Cadence USBSS DRD driver to linux kernel.
The Cadence USBSS DRD Controller is a highly configurable IP Core which
can be instantiated as Dual-Role Device (DRD), Peripheral Only and
Host Only (XHCI)configurations.
The current driver has been validated with FPGA burned. We
Patch moves common reusable code used by cdns3 and cdnsp driver
to cdns-usb-common library. This library include core.c, drd.c
and host.c files.
Signed-off-by: Pawel Laszczak
---
drivers/usb/cdns3/Kconfig | 8
drivers/usb/cdns3/Makefile| 8 +---
drivers/usb/cdns3/c
On Sun, Sep 27, 2020 at 02:11:18PM -0400, Sasha Levin wrote:
> This is a note to let you know that I've just added the patch titled
>
> ata: sata_mv, avoid trigerrable BUG_ON
>
> to the 4.4-stable tree which can be found at:
>
> http://www.kernel.org/git/?p=linux/kernel/git/stable/stable
On Mon, Sep 28, 2020 at 08:54:04AM -0300, Arnaldo Carvalho de Melo wrote:
> Em Fri, Sep 25, 2020 at 03:51:33PM +0200, Jiri Olsa escreveu:
> > On Fri, Sep 25, 2020 at 10:44:53PM +0900, Namhyung Kim wrote:
> > > On Fri, Sep 25, 2020 at 10:26 PM Jiri Olsa wrote:
> > > > On Thu, Sep 24, 2020 at 09:44:
> From: Stephen Rothwell
> Date: Mon, 28 Sep 2020 12:42:10 +1000
> Subject: [PATCH] merge fix for "mdio: fix mdio-thunder.c dependency & build
> error"
>
> Signed-off-by: Stephen Rothwell
> ---
> drivers/net/mdio/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/net/mdi
On Mon, Sep 28, 2020 at 01:13:38PM +0300, Joonas Lahtinen wrote:
> I think we have a gap that after splitting the drm-intel-next pull requests
> into
> two the drm-intel/for-linux-next branch is now missing material from
> drm-intel/drm-intel-gt-next.
>
> I think a simple course of action might b
Hi Zhen Lei,
On 2020/9/27 14:21, Zhen Lei wrote:
> Split the devicetree bindings of each Hisilicon controller from
> hisilicon.txt into a separate file, the file name is the compatible name
> attach the .txt file name extension.
>
> All Hi6220 dedicated controllers are grouped into subdirectory
From: Kan Liang
The Jasper Lake processor is also a Tremont microarchitecture. From the
perspective of Intel PMU, there is nothing changed compared with
Elkhart Lake.
Share the perf code with Elkhart Lake.
Signed-off-by: Kan Liang
---
arch/x86/events/intel/core.c | 1 +
1 file changed, 1 inser
From: Vijayanand Jitta
When ever a new iova alloc request comes iova is always searched
from the cached node and the nodes which are previous to cached
node. So, even if there is free iova space available in the nodes
which are next to the cached node iova allocation can still fail
because of thi
From: Vijayanand Jitta
When ever an iova alloc request fails we free the iova
ranges present in the percpu iova rcaches and then retry
but the global iova rcache is not freed as a result we could
still see iova alloc failure even after retry as global
rcache is holding the iova's which can cause
From: Kan Liang
The Jasper Lake processor is also a Tremont microarchitecture. From the
perspective of perf MSR, there is nothing changed compared with
Elkhart Lake.
Share the code path with Elkhart Lake.
Signed-off-by: Kan Liang
---
arch/x86/events/msr.c | 1 +
1 file changed, 1 insertion(+)
On Mon, Sep 28, 2020 at 02:30:57PM +0200, Greg KH wrote:
> On Sun, Sep 27, 2020 at 02:11:18PM -0400, Sasha Levin wrote:
> > This is a note to let you know that I've just added the patch titled
> >
> > ata: sata_mv, avoid trigerrable BUG_ON
> >
> > to the 4.4-stable tree which can be found at:
Hi Peter,
On 9/28/20 6:58 PM, Peter Zijlstra wrote:
On Mon, Sep 28, 2020 at 06:49:52PM +0800, quanyang.w...@windriver.com wrote:
From: Quanyang Wang
Since sched_clock_read_begin is called by notrace function sched_clock,
it shouldn't be traceable either, or else __ftrace_graph_caller will
run
On 9/18/2020 8:11 PM, Robin Murphy wrote:
> On 2020-08-20 13:49, vji...@codeaurora.org wrote:
>> From: Vijayanand Jitta
>>
>> When ever an iova alloc request fails we free the iova
>> ranges present in the percpu iova rcaches and then retry
>> but the global iova rcache is not freed as a result
On Mon, Sep 28, 2020 at 11:41 AM Linus Walleij wrote:
>
> Hi Arnd,
>
> help me out here because I feel vaguely stupid...
>
> On Mon, Sep 7, 2020 at 5:38 PM Arnd Bergmann wrote:
>
> > {
> > + if (IS_ENABLED(CONFIG_OABI_COMPAT))
> > + return task_thread_info(task)->syscall &
>
Commit b6724f118d44 ("prctl: Hook L1D flushing in via prctl") checks the
validity for enable_l1d_flush_for_task() and introduces some superfluous
local variables for that implementation.
make clang-analyzer on x86_64 tinyconfig caught my attention with:
arch/x86/mm/tlb.c:332:2: warning: Value s
On Tue, Aug 18, 2020 at 2:34 PM Barry Song wrote:
>
> Right now, all new ZIP drivers are adapted to crypto_acomp APIs rather
> than legacy crypto_comp APIs. Tradiontal ZIP drivers like lz4,lzo etc
> have been also wrapped into acomp via scomp backend. But zswap.c is still
> using the old APIs. Tha
During testing, I see it is possible that rcu_pending() returns 1 when
offloaded callbacks are ready to execute thus raising the RCU softirq.
However, softirq does not execute offloaded callbacks. They are executed in a
kthread which is awakened independent of the softirq. The softirq ignores the
On Sun, Sep 27, 2020 at 11:45:30AM -0700, Linus Torvalds wrote:
> On Sun, Sep 27, 2020 at 11:16 AM Linus Torvalds
> wrote:
> >
> > Btw, I'm not convinced about the whole "turn the pte read-only and
> > then back". If the fork races with another thread doing a pinning
> > fast-GUP on another CPU, t
On Sat, Sep 26, 2020 at 10:50:52AM -0700, Palmer Dabbelt wrote:
> On Mon, 21 Sep 2020 21:37:52 PDT (-0700), Christoph Hellwig wrote:
>> Given tht we've not made much progress with the common branch,
>> are you fine just picking this up through the riscv tree for 5.10?
>>
>> I'll defer other archite
On Sun, Sep 27, 2020 at 07:05:34PM -0700, psoda...@codeaurora.org wrote:
> On 2020-09-24 11:21, Thomas Gleixner wrote:
> > On Thu, Sep 24 2020 at 08:33, Greg KH wrote:
> > > On Wed, Sep 23, 2020 at 05:08:32PM -0700, Prasad Sodagudi wrote:
> > > > +config CONSOLE_FLUSH_ON_HOTPLUG
> > > > + boo
Ping guys. This is worth fixing.
On Wed, Sep 23, 2020 at 7:44 PM Muchun Song wrote:
>
> We should make sure that async workqueue is canceled on exit, but on
> some corner case, we found that the async workqueue is not canceled
> on exit in the linux-5.4. So we started an in-depth investigation.
>
On 2020/9/28 20:37, Wei Xu wrote:
> Hi Zhen Lei,
>
>
>
> On 2020/9/27 14:21, Zhen Lei wrote:
>> Split the devicetree bindings of each Hisilicon controller from
>> hisilicon.txt into a separate file, the file name is the compatible name
>> attach the .txt file name extension.
>>
>> All Hi6220
On Wed, Sep 09, 2020 at 04:10:28PM +0800, JC Kuo wrote:
> PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
> power sequencers' output to enable/disable PLLE. PLLE hardware power
> sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
> are enabled.
>
> Signed-off
At 2020-09-27T22:05:14+0200, Alejandro Colomar wrote:
> Hi Branden,
>
> * G. Branden Robinson via linux-man:
>
> 1)
>
> > .EX
> > .B int fstat(int \c
> > .IB fd , \~\c
> > .B struct stat *\c
> > .IB statbuf );
> > .EE
>
> 2)
>
> > .EX
> > .BI "int fstat(int " fd ", struct stat *" statbuf );
>
On Wed, Sep 09, 2020 at 04:10:27PM +0800, JC Kuo wrote:
> PLLE has a hardware power sequencer logic which is a state machine
> that can power on/off PLLE without any software intervention. The
> sequencer has two inputs, one from XUSB UPHY PLL and the other from
> SATA UPHY PLL. PLLE provides refer
On Mon, Sep 28, 2020 at 10:36:00AM +0200, David Hildenbrand wrote:
> Hi Oscar!
Hi David :-)
>
> Old code:
>
> set_page_refcounted(): sets the refcount to 1.
> __free_pages()
> -> put_page_testzero(): sets it to 0
> -> free_the_page()->__free_pages_ok()
>
> New code:
>
> set_page_refcounte
> Didn't look at the rest
Thanks for your comments Joe, I will refactor the code for clarity, remove
redundancy and address your comments.
Regards
Srini
It would be very nice to finally merge this support during the next cycle,
so please take a look.
I think we need acks covering x86, ARM and ACPI. Rafael took a look back
in November at v5 and was looking for x86 and ARM acks. Whilst there is
no ARM specific code left we probably still need an A
Generic Initiators are a new ACPI concept that allows for the
description of proximity domains that contain a device which
performs memory access (such as a network card) but neither
host CPU nor Memory.
This patch has the parsing code and provides the infrastructure
for an architecture to associa
This tries to solve a warning reported by the lkp bot:
>> drivers/iio/adc/at91_adc.c:1439:34: warning: unused variable
>> 'at91_adc_dt_ids' [-Wunused-const-variable]
static const struct of_device_id at91_adc_dt_ids[] = {
^
1 warning generated.
This shows
In common with memoryless domains we only register GI domains
if the proximity node is not online. If a domain is already
a memory containing domain, or a memoryless domain there is
nothing to do just because it also contains a Generic Initiator.
Signed-off-by: Jonathan Cameron
---
v11: Improved
Until we tell ACPI that we support generic initiators, it will have
to operate in fall back domain mode and all _PXM entries should
be on existing non GI domains.
This patch sets the relevant OSC bit to make that happen.
Signed-off-by: Jonathan Cameron
---
v11: No change
drivers/acpi/bus.c |
The main intent is to get rid of the cast for the void-pointer returned by
of_device_get_match_data().
This requires const-ifying the 'caps' and 'registers' references on the
at91_adc_state struct.
The caps can be obtained also from the old platform_data (in the
at91_adc_probe_pdata() function),
On Wed, Sep 09, 2020 at 04:10:26PM +0800, JC Kuo wrote:
> Tegra XHCI controler can be placed in ELPG (Engine Level PowerGated)
> state for power saving when all of the connected USB devices are in
> suspended state. This patch series includes clk, phy and pmc changes
> that are required for properl
On Mon, Sep 28, 2020 at 12:41:47PM +0200, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski
>
> There's a common pattern of dynamically allocating an array of char
> pointers and then also dynamically allocating each string in this
> array. Provide a helper for freeing such a string array wi
In ACPI 6.3, the Memory Proximity Domain Attributes Structure
changed substantially. One of those changes was that the flag
for "Memory Proximity Domain field is valid" was deprecated.
This was because the field "Proximity Domain for the Memory"
became a required field and hence having a validity
New access1 class is nearly the same as access0, but always provides
characteristics for CPUs to memory. The existing access0 class
provides characteristics to nearest or direct connnect initiator
which may be a Generic Initiator such as a GPU or network adapter.
This new class allows thread pla
Try to make minimal changes to the document which already describes
access class 0 in a generic fashion (including IO initiatiors that
are not CPUs).
Signed-off-by: Jonathan Cameron
---
v11: No change.
Documentation/admin-guide/mm/numaperf.rst | 8
1 file changed, 8 insertions(+)
dif
On Fri, 25 Sep 2020 23:26:49 +0200, Krzysztof Kozlowski wrote:
> The i.MX 53 and i.MX6Q DTS use two compatibles, i.MX 6SL/6SLL/SX three
> so update the binding to fix dtbs_check warnings like:
>
> serial@21ec000: compatible: ['fsl,imx6q-uart', 'fsl,imx21-uart'] is not
> valid under any of the g
The fr_hard_header function is used to prepend the header to skbs before
transmission. It is used in 3 situations:
1) When a control packet is generated internally in this driver;
2) When a user sends an skb on an Ethernet-emulating PVC device;
3) When a user sends an skb on a normal PVC device.
T
On Sun, Sep 27, 2020 at 11:21:53PM -0700, John Hubbard wrote:
> diff --git a/tools/testing/selftests/vm/Makefile
> b/tools/testing/selftests/vm/Makefile
> index d1ae706d9927..9cc6bc087461 100644
> +++ b/tools/testing/selftests/vm/Makefile
> @@ -130,3 +130,5 @@ endif
> $(OUTPUT)/userfaultfd: LDLIB
Hi Zhen,
On Mon, Sep 28, 2020 at 2:15 PM Ard Biesheuvel wrote:
> On Mon, 28 Sep 2020 at 13:57, Leizhen (ThunderTown)
> wrote:
> > On 2020/9/28 18:14, Ard Biesheuvel wrote:
> > > On Mon, 28 Sep 2020 at 11:27, Zhen Lei wrote:
> > >>
> > >> mov r4, pc
> > >> and r4, r4, #0xf800 //t
On Mon, Sep 28, 2020 at 12:26:58PM +, Aisheng Dong wrote:
> Hi Peter,
>
> We met a cpudile warning on mx6q sabresd board since v5.9-rc3 and also exist
> in latest linux-next (next-20200925).
> After some bisection, I found it’s caused by below patch.
> Any suggestions about this issue?
The w
On Mon, Sep 28, 2020 at 12:41:53PM +0200, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski
>
> While we do check the "chip-name" property in probe(), we never actually
> use it. Let's pass the chip label to the driver using device properties
> as we'll want to allow users to define their ow
On Tue, Sep 22, 2020 at 05:05:10PM -0400, Lyude Paul wrote:
> While I thought I had this correct (since it actually did reject modes
> like I expected during testing), Ville Syrjala from Intel pointed out
> that the logic here isn't correct. max_clock refers to the max symbol
> rate supported by th
Hi Anthony,
On Tue, Sep 22, 2020 at 02:21:53AM -0700, Anthony Steinhauser wrote:
> Support of Spectre v4 PR_SPEC_DISABLE_NOEXEC mitigation mode for on arm64.
>
> PR_SPEC_DISABLE_NOEXEC turns the mitigation on, but it is automatically
> turned off whenever a new program is being execve'ed.
>
> Si
On Mon, Sep 28, 2020 at 12:41:54PM +0200, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski
>
> GPIO line names are currently created by the driver from the chip label.
> We'll want to support custom formats for line names (for instance: to
> name all lines the same) for user-space tests so
On Sun, Sep 27, 2020 at 11:21:59PM -0700, John Hubbard wrote:
> @@ -76,8 +79,6 @@ TEST_FILES := test_vmalloc.sh
> KSFT_KHDR_INSTALL := 1
> include ../lib.mk
>
> -$(OUTPUT)/hmm-tests: LDLIBS += -lhugetlbfs
> -
> ifeq ($(ARCH),x86_64)
> BINARIES_32 := $(patsubst %,$(OUTPUT)/%,$(BINARIES_32))
>
On Wed, Sep 09, 2020 at 04:10:29PM +0800, JC Kuo wrote:
> The programming sequence in tegra210_usb3_port_enable() is required
> for both cold boot and SC7 exit, and must be performed only after
> PEX/SATA UPHY is initialized. Therefore, this commit moves the
> programming sequence to tegra210_usb3_
On Mon, Sep 28, 2020 at 2:55 PM Andy Shevchenko
wrote:
>
> On Mon, Sep 28, 2020 at 12:41:47PM +0200, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski
> >
> > There's a common pattern of dynamically allocating an array of char
> > pointers and then also dynamically allocating each string i
Patch defines macros, registers and structures used by
Device side driver.
Because the size of main patch is very big, I’ve decided to create
separate patch for gadget.h. It should simplify reviewing the code.
Signed-off-by: Pawel Laszczak
---
drivers/usb/cdnsp/gadget.h | 1459 +
From: Andrej Shadura
Add a mapping for my old work email for BelDisplayTech to the personal
email, and make sure the Collabora email has the correct spelling
of the first name.
Signed-off-by: Andrej Shadura
---
.mailmap | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.mailmap b/.mailmap
On Wed, Sep 09, 2020 at 04:10:30PM +0800, JC Kuo wrote:
> Once UPHY PLL hardware power sequencer is enabled, do not assert
> reset to PEX/SATA PLLs, otherwise UPHY PLL operation will be broken.
> This commit removes reset_control_assert(pcie->rst) and
> reset_control_assert(sata->rst) from PEX/SATA
On Wed, Sep 09, 2020 at 04:10:31PM +0800, JC Kuo wrote:
> This commit is a preparation for enabling XUSB SC7 support.
> It rearranges Tegra210 XUSB PADCTL UPHY initialization sequence,
> for the following reasons:
>
> 1. PLLE hardware power sequencer has to be enabled only after both
>PEX UPHY
On Wed, Sep 09, 2020 at 04:10:32PM +0800, JC Kuo wrote:
> As per Tegra210 TRM, before changing lane assignments, driver should
> keep lanes in IDDQ and sleep state; after changing lane assignments,
> driver should bring lanes out of IDDQ.
> This commit implements the required operations.
>
> Signe
On Wed, Sep 09, 2020 at 04:10:33PM +0800, JC Kuo wrote:
> This commit adds sleepwalk/wake and suspend/resume interfaces
> to Tegra XUSB PHY driver.
>
> Tegra XUSB host controller driver makes use of sleepwalk functions
> to enable/disable sleepwalk circuit which is in always-on partition
> and can
This commit adds mmc device node for mt8192
Signed-off-by: Wenbin Mei
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 89 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi| 34
2 files changed, 123 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dt
MT8192 msdc is an independent sub system, we need control more bus
clocks for it.
Add support for the additional subsys clocks to allow it to be
configured appropriately.
Signed-off-by: Wenbin Mei
---
drivers/mmc/host/mtk-sd.c | 77 ++-
1 file changed, 59 inse
Change in v2:
Convert mtk-sd to json-schema
Wenbin Mei (4):
dt-bindings: mmc: Convert mtk-sd to json-schema
mmc: dt-bindings: add support for MT8192 SoC
arm64: dts: mt8192: add mmc device node
mmc: mediatek: Add subsys clock control for MT8192 msdc
---
This patch depends on
[v4,1/3] arm64:
Convert the mtk-sd binding to DT schema format using json-schema.
Signed-off-by: Wenbin Mei
Reviewed-by: Ulf Hansson
---
.../devicetree/bindings/mmc/mtk-sd.txt| 75
.../devicetree/bindings/mmc/mtk-sd.yaml | 165 ++
2 files changed, 165 insertions(+), 75 d
MT8192 mmc host ip is compatible with MT8183.
Add support for this.
Signed-off-by: Wenbin Mei
Reviewed-by: Ulf Hansson
---
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc
On Mon, Sep 28, 2020 at 3:00 PM Andy Shevchenko
wrote:
>
> On Mon, Sep 28, 2020 at 12:41:53PM +0200, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski
> >
> > While we do check the "chip-name" property in probe(), we never actually
> > use it. Let's pass the chip label to the driver using
From: Sergiu Cuciurean
As part of the general cleanup of indio_dev->mlock, this change replaces
it with a local lock on the device's state structure.
This is part of a bigger cleanup.
Link:
https://lore.kernel.org/linux-iio/CA+U=dsoo6yabe5odlp+efnpgfdjk5zeqecegkqjxxcvehlw...@mail.gmail.com/
Si
From: Sergiu Cuciurean
As part of the general cleanup of indio_dev->mlock, this change replaces
it with a local lock on the device's state structure.
This is part of a bigger cleanup.
Link:
https://lore.kernel.org/linux-iio/CA+U=dsoo6yabe5odlp+efnpgfdjk5zeqecegkqjxxcvehlw...@mail.gmail.com/
Si
From: Sergiu Cuciurean
As part of the general cleanup of indio_dev->mlock, this change replaces
it with a local lock on the device's state structure.
This is part of a bigger cleanup.
Link:
https://lore.kernel.org/linux-iio/CA+U=dsoo6yabe5odlp+efnpgfdjk5zeqecegkqjxxcvehlw...@mail.gmail.com/
Si
From: Sergiu Cuciurean
As part of the general cleanup of indio_dev->mlock, this change replaces
it with a local lock on the device's state structure.
This is part of a bigger cleanup.
Link:
https://lore.kernel.org/linux-iio/CA+U=dsoo6yabe5odlp+efnpgfdjk5zeqecegkqjxxcvehlw...@mail.gmail.com/
Si
From: Sergiu Cuciurean
As part of the general cleanup of indio_dev->mlock, this change replaces
it with a local lock on the device's state structure.
This is part of a bigger cleanup.
Link:
https://lore.kernel.org/linux-iio/CA+U=dsoo6yabe5odlp+efnpgfdjk5zeqecegkqjxxcvehlw...@mail.gmail.com/
Si
On Wed, Sep 09, 2020 at 04:10:34PM +0800, JC Kuo wrote:
> This commit implements a register map which grants USB (UTMI and HSIC)
> sleepwalk registers access to USB PHY drivers. The USB sleepwalk logic
> is in PMC hardware block but USB PHY drivers have the best knowledge
> of proper programming se
On Wed, Sep 09, 2020 at 04:10:35PM +0800, JC Kuo wrote:
> PMC driver provides USB sleepwalk registers access to XUSB PADCTL
> driver. This commit adds a "nvidia,pmc" property which points to
> PMC node to XUSB PADCTL device node.
>
> Signed-off-by: JC Kuo
> ---
> v3:
>no change
>
> arch/arm
On Tue, Sep 22, 2020 at 11:12:25AM +0100, Andre Przywara wrote:
> The Scalable Vector Extension (SVE) is an ARMv8 architecture extension
> that introduces very long vector operations (up to 2048 bits).
(8192, in fact, though don't expect to see that on real hardware any
time soon... qemu and the
Le lun. 28 sept. 2020 à 14:10, Christoph Hellwig a écrit
:
On Mon, Sep 28, 2020 at 01:46:55PM +0200, Paul Cercueil wrote:
dma_mmap_attrs can only be used on allocations from dma_mmap_attrs
with
the same attrs. As there is no allocation using
DMA_ATTR_NON_CONSISTENT
in the drm core, so
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