Add VSP support to R8A7742 (RZ/G1H) SoC dtsi.
Signed-off-by: Lad Prabhakar
Reviewed-by: Chris Paterson
---
arch/arm/boot/dts/r8a7742.dtsi | 36 ++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index
On 11.09.20 09:20, Michal Hocko wrote:
> On Thu 10-09-20 22:31:09, David Hildenbrand wrote:
>>
>>
>>> Am 10.09.2020 um 22:01 schrieb Dave Hansen :
>>>
>>> On 9/10/20 3:20 AM, David Hildenbrand wrote:
I was just exploring how /sys/devices/system/memory/memoryX/phys_device
is/was used. It'
On 9/10/20 11:13 PM, Alejandro Colomar wrote:
> Signed-off-by: Alejandro Colomar
Thanks, Alex. Patch Applied.
Cheers,
Michael
> ---
> man2/eventfd.2 | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/man2/eventfd.2 b/man2/eventfd.2
> index 929234ab7..71e9d85b4 10064
On 9/10/20 11:13 PM, Alejandro Colomar wrote:
> Signed-off-by: Alejandro Colomar
Thanks, Alex. Patch Applied.
Cheers,
Michael
> ---
> man2/timerfd_create.2 | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/man2/timerfd_create.2 b/man2/timerfd_create.2
> index 67a1
On 2020/9/11 4:07, Cong Wang wrote:
> On Tue, Sep 8, 2020 at 4:06 AM Yunsheng Lin wrote:
>>
>> Currently there is concurrent reset and enqueue operation for the
>> same lockless qdisc when there is no lock to synchronize the
>> q->enqueue() in __dev_xmit_skb() with the qdisc reset operation in
>>
This patch is adding const qualifier to the mhi controller config
information passed to mhi_register_controller which is exported
API. Currently ath11k MHI controller driver depends on this change
to pass MHI config information.
Hemant Kumar (1):
bus: mhi: core: Add const qualifier to MHI config
MHI channel, event and controller config data needs to be
treated read only information. Add const qualifier to make
sure config information passed by MHI controller is not
modified by MHI core driver.
Suggested-by: Kalle Valo
Signed-off-by: Hemant Kumar
---
drivers/bus/mhi/core/init.c | 12 +++
On Fri, 2020-09-04 at 11:09 -0700, Andrew Morton wrote:
> On Fri, 4 Sep 2020 16:48:07 +0200 Bean Huo
> wrote:
>
> > From: Bean Huo
> >
> > Current generic_file_buffered_read() will break up the larger
> > batches of pages
> > and read data in single page length in case of ra->ra_pages == 0
On Thu, 10 Sep 2020 23:34:47 +0530
Nishant Malpani wrote:
> Introduce DATA_RDY trigger for triggered buffer setup; this enables continuous
> data capture. Additionally, add support for direct register access using the
> debugfs
> iio interface.
>
> The device-tree bindings documentation illus
Enable support of pm_runtime on STM32 SAI driver to allow
SAI power state monitoring.
pm_runtime_put_autosuspend() is called from ASoC framework
on pcm device close.
The pmdown_time delay is available in runtime context, and may be set
in SAI driver to take into account shutdown delay on playback.
On Thu, Sep 10, 2020 at 11:14:18AM -0700, Hyun Kwon wrote:
> Hi Jason,
>
> On Thu, Sep 10, 2020 at 07:06:30AM -0700, Jason Yan wrote:
> > This addresses the following gcc warning with "make W=1":
> >
> > drivers/gpu/drm/xlnx/zynqmp_disp.c:245:18: warning:
> > ‘scaling_factors_666’ defined but not
Hi Bjorn,
On 2020-09-04 21:25, Bjorn Andersson wrote:
Based on previous attempts and discussions this is the latest attempt
at
inheriting stream mappings set up by the bootloader, for e.g. boot
splash or
efifb.
Per Will's request this builds on the work by Jordan and Rob for the
Adreno
SMMU
On Fri, Sep 11, 2020 at 10:06 AM Steffen Klassert
wrote:
>
> On Thu, Sep 10, 2020 at 10:09:50AM +0200, Dmitry Vyukov wrote:
> > On Thu, Sep 10, 2020 at 10:08 AM B K Karthik wrote:
> > >
> > > On Thu, Sep 10, 2020 at 1:32 PM Dmitry Vyukov wrote:
> > > >
> > > > On Thu, Sep 10, 2020 at 9:20 AM Ana
On 2020-09-04 21:25, Bjorn Andersson wrote:
Extract the conditional invocation of the platform defined
alloc_context_bank() to a separate function to keep
arm_smmu_init_domain_context() cleaner.
Instead pass a reference to the arm_smmu_device as parameter to the
call. Also remove the count param
On Thu, Sep 10, 2020 at 10:23 PM Mark Brown wrote:
>
> On Thu, Sep 10, 2020 at 10:10:32PM +0800, Shengjiu Wang wrote:
>
> > ak4458 can't support DSD512 format, but ak4497 can, so add
> > a new variable in ak4458_drvdata to distinguish these two
> > platform.
>
> > In hw_params(), calculate bit clo
> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: Thursday, September 10, 2020 1:44 AM
> To: 吳昊澄 Ricky
> Cc: a...@arndb.de; gre...@linuxfoundation.org; bhelg...@google.com;
> ulf.hans...@linaro.org; rui_f...@realsil.com.cn; linux-kernel@vger.kernel.org;
> puranj
On 11.09.20 04:21, kernel test robot wrote:
> Hi David,
>
> I love your patch! Yet something to improve:
>
> [auto build test ERROR on next-20200909]
> [cannot apply to mmotm/master hnaz-linux-mm/master xen-tip/linux-next
> powerpc/next linus/master v5.9-rc4 v5.9-rc3 v5.9-rc2 v5.9-rc4]
> [If you
On 2020-09-04 21:25, Bjorn Andersson wrote:
Delay modifications to the domain during arm_smmu_init_domain_context()
until we've allocated a context bank. This will allow us to postpone
the
special handling of identity domains until the platform specific
context
bank allocator has been executed
On 2020-09-04 21:25, Bjorn Andersson wrote:
For implementations of the ARM SMMU where stream mappings of bypass
type
are prohibited identity domains can be implemented by using context
banks with translation disabled.
Postpone the decision to skip allocating a context bank until the
implementat
Hello,
Thanks for your prompt feedback.
> -Original Message-
> From: Andrew Jeffery
> Sent: Friday, September 11, 2020 12:46 PM
> To: Joel Stanley ; ChiaWei Wang
>
> Subject: Re: [PATCH 0/4] Remove LPC register partitioning
>
>
> On Fri, 11 Sep 2020, at 13:33, Joel Stanley wrote:
> >
On 2020-09-04 21:25, Bjorn Andersson wrote:
For implementations of the ARM SMMU where stream mappings of bypass
type
are prohibited identity domains can be implemented by using context
banks with translation disabled.
Postpone the decision to skip allocating a context bank until the
implementat
The main target of this patches is to provide flow control support
for ag71xx driver. To be able to validate this functionality, I also
added ethtool support with HW counters. So, this patches was validated
with iperf3 and counters showing Pause frames send or received by this
NIC.
Oleksij Rempel
On 2020-09-04 21:25, Bjorn Andersson wrote:
Some firmware found on various Qualcomm platforms traps writes to S2CR
of type BYPASS and writes FAULT into the register. In particular, this
prevents us from marking the streams for the display controller as
BYPASS to allow continued scanout of the scr
On 2020/9/11 16:13, Yunsheng Lin wrote:
> On 2020/9/11 4:07, Cong Wang wrote:
>> On Tue, Sep 8, 2020 at 4:06 AM Yunsheng Lin wrote:
>>>
>>> Currently there is concurrent reset and enqueue operation for the
>>> same lockless qdisc when there is no lock to synchronize the
>>> q->enqueue() in __dev_x
Add basic ethtool support. The functionality was tested on AR9331 SoC.
Signed-off-by: Oleksij Rempel
---
drivers/net/ethernet/atheros/ag71xx.c | 147 ++
1 file changed, 147 insertions(+)
diff --git a/drivers/net/ethernet/atheros/ag71xx.c
b/drivers/net/ethernet/atheros/a
Add flow control support. The functionality was tested on AR9331 SoC and
confirmed by iperf3 results and HW counters exported over ethtool.
Following test configurations was used:
iMX6S receiver <--- TL-SG1005D switch < AR9331 sender
The switch is supporting symmytric flow control:
Settings f
On 2020-09-04 21:25, Bjorn Andersson wrote:
Firmware that traps writes to S2CR to translate BYPASS into FAULT also
ignores writes of type FAULT. As such booting with "disable_bypass" set
will result in all S2CR registers left as configured by the bootloader.
This has been seen to result in indet
On 2020-09-04 21:25, Bjorn Andersson wrote:
Add a new operation to allow platform implementations to inherit any
stream mappings from the boot loader.
Signed-off-by: Bjorn Andersson
---
Reviewed-by: Sai Prakash Ranjan
Tested-by: Sai Prakash Ranjan
--
QUALCOMM INDIA, on behalf of Qualcomm
On 2020/08/21 20:44, Matthew Wilcox wrote:
On Fri, Aug 21, 2020 at 08:33:06PM +0800, Yu Kuai wrote:
changes from v3: - add IOMAP_STATE_ARRAY_SIZE - replace set_bit /
clear_bit with bitmap_set / bitmap_clear - move
iomap_set_page_dirty() out of 'iop->state_lock' - merge
iomap_set/clear_range_di
On 2020-09-04 21:25, Bjorn Andersson wrote:
Some platform implementations needs to be able to allocate a domain for
emulating identity mappings using a context bank without translation.
Provide a helper function to allocate such a domain.
Signed-off-by: Bjorn Andersson
---
Reviewed-by: Sai P
On 10/09/2020 21.05, Brian Norris wrote:
> On Thu, Sep 10, 2020 at 7:35 AM Masahiro Yamada wrote:
>> On Thu, Sep 10, 2020 at 8:57 PM Rasmus Villemoes
>> wrote:
>>> So in order to avoid `uname -a` output relying on such random details
>>> of the build environment which are rather hard to ensure ar
Currently NXP fspi driver has support of DT only. Adding ACPI
support to the driver so that it can be used by UEFI firmware
booting in ACPI mode. This driver will be probed if any firmware
will expose HID "NXP0009" in DSDT table.
Signed-off-by: kuldip dwivedi
---
Notes:
1. Add ACPI match ta
On 9/4/20 2:55 PM, Neil Armstrong wrote:
> The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency
> higher than 10MHz for the TX Escape Clock, thus make the target rate
> configurable.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c |
On 2020-09-04 21:25, Bjorn Andersson wrote:
With many Qualcomm platforms not having functional S2CR BYPASS a
temporary IOMMU domain, without translation, needs to be allocated in
order to allow these memory transactions.
Unfortunately the boot loader uses the first few context banks, so
rather t
Hello!
On 10.09.2020 14:56, Tang Bin wrote:
Use IS_ERR() and PTR_ERR() instead of PTR_ERR_OR_ZERO() to
simplify code, avoid redundant judgements.
Signed-off-by: Zhang Shengju
Signed-off-by: Tang Bin
---
drivers/usb/phy/phy-tegra-usb.c | 25 ++---
1 file changed, 10 ins
Currently, after generating run_kselftest.sh, there is no way to choose
which test we could run. All the tests are listed together and we have
to run all every time. This patch enhanced the run_kselftest.sh to make
the tests individually selectable. e.g.
$ ./run_kselftest.sh -t "bpf size timers"
Hi Michael,
The indentation in the original code was a bit weird (specifically, the
'do {' part had one more indentation level than the closing '} while'),
so I simply chose something nice. See the original page, and if you
think it's ok keep it, else find something nice :)
Cheers,
Alex
O
On Wed, 9 Sep 2020 16:10:57 +0200
Mauro Carvalho Chehab wrote:
> There's a warning at iio.h kernel-doc markup:
>
> ./include/linux/iio/iio.h:644: WARNING: Unknown target name: "devm".
>
> Because it is using {devm_}foo notation. Well, this is not
> a valid kernel-doc notation. Also, it p
On Fri, Sep 11, 2020 at 10:33:21AM +0800, Chunfeng Yun wrote:
> On Thu, 2020-09-10 at 14:12 +0100, Daniel Thompson wrote:
> > On Thu, Sep 10, 2020 at 04:21:45PM +0800, Chunfeng Yun wrote:
> > > Use readl_poll_timeout_atomic() to simplify code
> > >
> > > Cc: Mathias Nyman
> > > Cc: Yoshihiro Shim
ak4458 can't support DSD512 format, but ak4497 can, so add
a new variable (dsd512) in ak4458_drvdata to distinguish these
two platforms.
Add a new kcontrol for ak4497 codec for ak4497 has a specific
pin selection.
In hw_params(), calculate bit clock according to different DSD
format and configure
Hi Viresh,
On Fri, Aug 28, 2020 at 11:57:28AM +0200, Stephan Gerhold wrote:
> On Fri, Aug 28, 2020 at 12:05:11PM +0530, Viresh Kumar wrote:
> > On 27-08-20, 13:44, Stephan Gerhold wrote:
> > > Hmm. Actually I was using this parameter for initial testing, and forced
> > > on the power domains from
Hi,
Sorry that after copy and paste, the content of the patch somehow
changed and looks strange.
Best regards,
Yu Kuai
On 2020/09/11 16:27, yukuai (C) wrote:
On 2020/08/21 20:44, Matthew Wilcox wrote:
On Fri, Aug 21, 2020 at 08:33:06PM +0800, Yu Kuai wrote:
changes from v3: - add IOMAP_STAT
This patch enables CAN0 interface exposed through connector J4 on the
camera DB.
Signed-off-by: Lad Prabhakar
Reviewed-by: Chris Paterson
---
arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm
The intent of balance_callback() has always been to delay executing
balancing operations until the end of the current rq->lock section.
This is because balance operations must often drop rq->lock, and that
isn't safe in general.
However, as noted by Scott, there were a few holes in that scheme;
ba
In preparation for migrate_disable(), make sure only per-cpu kthreads
are allowed to run on !active CPUs.
This is ran (as one of the very first steps) from the cpu-hotplug
task which is a per-cpu kthread and completion of the hotplug
operation only requires such tasks.
This contraint enables the
Hi!
These two patches are the result of Thomas pestering me with migrate_disable()
patches for upstream. The first one is a cleanup/fix for the existing
balance_callback machinery. The second (ab)uses the context_switch() tail
invocation of balance_callbacks() to push away 'undesirables' during CP
> > @@ -740,12 +755,45 @@ static void netvsc_send_completion(struct
> > net_device *ndev,
> >int budget)
> > {
> > const struct nvsp_message *nvsp_packet = hv_pkt_data(desc);
> > + u32 msglen = hv_pkt_datalen(desc);
> > +
> > + /* Ensure packet is big enough
Hi Michael,
On 2020-09-11 09:54, Michael Kerrisk (man-pages) wrote:
Hi Alex,
On 9/10/20 11:13 PM, Alejandro Colomar wrote:
Signed-off-by: Alejandro Colomar
I'm reluctant to apply this, because MAX() is not a standard
macro. I suppose it may not be present on some other UNIX
systems. You tho
Sorry I missed one comments, see inline.
On Tue, Sep 08, 2020 at 12:01:02PM +0200, Krzysztof Kozlowski wrote:
> On Tue, Sep 08, 2020 at 04:27:25PM +0800, Xu Yilun wrote:
> > This driver is for the EMIF private feature implemented under FPGA
> > Device Feature List (DFL) framework. It is used to ex
Hi,
On (20/08/17 20:03), yezengruan wrote:
> Hi Sergey,
>
> I have a set of patches similar to yours.
>
> https://lore.kernel.org/lkml/20191226135833.1052-1-yezengr...@huawei.com/
I'm sorry for the belated reply.
Right, quite similar, but not exactly, I believe. I deliberately wanted
to untang
This gets iATU register area from reg property that has reg-names "atu".
In Synopsys DWC version 4.80 or later, since iATU register area is
separated from core register area, this area is necessary to get from
DT independently.
Cc: Murali Karicheri
Cc: Jingoo Han
Cc: Gustavo Pimentel
Suggested-
After applying "PCI: dwc: Add common iATU register support",
there is no need to set own iATU in the Keystone driver itself.
Cc: Murali Karicheri
Cc: Jingoo Han
Cc: Gustavo Pimentel
Suggested-by: Rob Herring
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pci-keystone.c | 20 +
This series is split from the previous patches:
https://www.spinics.net/lists/linux-pci/msg97608.html
"[PATCH v6 0/6] PCI: uniphier: Add features for UniPhier PCIe host controller"
This moves iATU register mapping in the Keystone driver to common
framework. And this adds "iatu" property descriptio
In the dt-bindings, "atu" reg-names is required to get the register space
for iATU in Synopsys DWC version 4.80 or later.
Signed-off-by: Kunihiko Hayashi
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/pci/uniphier-pcie.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documen
ATTENZIONE
La cassetta postale non può inviare o ricevere nuova posta fino a quando non si
ri-verifica la casella di posta elettronica, ovvero 5 GB di spazio di
archiviazione, attualmente introdotto dall'amministratore che lavora a 10,9 GB.
Per verificare nuovamente la tua casella di posta, inv
On Thu, Sep 10, 2020 at 10:06:10PM +0800, Jason Yan wrote:
> This function always return '0' and no callers use the return value. So
> make it a void function.
>
> This eliminates the following coccicheck warning:
>
> drivers/gpu/drm/i810/i810_dma.c:860:8-11: Unneeded variable: "ret".
> Return "0
Greeting,
I am Kenneth Johnson working with a business consultant.
There is a transaction of $1.4 billion dollars here that own by Arab
man if you have interest you need to come down to Gambia discuss
percentage with him.
Regards,
Kenneth Johnson
My apologies for the slow reply.
On (20/08/17 13:25), Marc Zyngier wrote:
>
> It really isn't the same thing at all. You are exposing PV spinlocks,
> while Sergey exposes preemption to vcpus.
>
Correct, we see vcpu preemption as a "fundamental" feature, with
consequences that affect scheduling, w
On Fri, 11 Sep 2020 at 10:46, Xu Yilun wrote:
>
> Sorry I missed one comments, see inline.
>
> On Tue, Sep 08, 2020 at 12:01:02PM +0200, Krzysztof Kozlowski wrote:
> > On Tue, Sep 08, 2020 at 04:27:25PM +0800, Xu Yilun wrote:
> > > This driver is for the EMIF private feature implemented under FPGA
Hi Lucas,
almost one month has passed since I sent this little patch series - is
there any update on this?
Am Fr., 14. Aug. 2020 um 11:05 Uhr schrieb Christian Gmeiner
:
>
> This little patch set adds support for the total bandwidth used by HI. The
> basic hi bandwidth read-out is quite simple b
On Mon, Sep 07, 2020 at 09:05:02PM +0800, qianjun.ker...@gmail.com wrote:
> From: jun qian
>
> It is hard to understand what the meaning of the value from
> the return value of wakeup_preempt_entity, so I fix it.
> @@ -6822,9 +6828,9 @@ static unsigned long wakeup_gran(struct sched_entity
> *se
On Fri, 2020-09-11 at 02:16 +, Can Guo wrote:
> > >
> > > So your resolution looks good to me.
> > >
> > > Thanks so much : )
> >
> > You're welcome ... but just remember I have to explain this to
> > Linus
> > when the merge window opens. It would be a lot easier if this
> > hadn't
> > hap
Hello Eddie,
For FSI design is request for two clock source.
one for FSI core, one for FSI bus clock.
In AST2600 FSI core clk is apll, FSI bus clock need apll/4.
So, you should fix for fsi clock input. Not set from fsi-master-driver.
And fsi-master driver
On Fri 11-09-20 10:09:07, David Hildenbrand wrote:
[...]
> Consider two cases:
>
> 1. Hot(un)plugging huge DIMMs: many (not all!) use cases want to
> online/offline the whole thing. HW can effectively only plug/unplug the
> whole thing. It makes sense in some (most?) setups to represent one DIMM
>
Hi Alex,
On 9/10/20 11:13 PM, Alejandro Colomar wrote:
> I added some headers to reduce the number of warnings.
> I found the needed headers by using grep, but maybe some of them
> shouldn't be included directly.
>
> The example still has many problems to compile.
Yes, there are so many problems
Hi Michael,
On 2020-09-11 09:24, Michael Kerrisk (man-pages) wrote:
This may be true on Linux, but is not true on other systems.
For example, on HP-UX, according to one header file I'm
looking at, the return value is 'long'. >
These kinds of casts are intended to improve code portability
across
Hello,
does this logic apply to "Unrecoverable System Reset" as well?
Thanks
Michal
On Tue, Jan 22, 2019 at 02:11:24PM +, Christophe Leroy wrote:
> Looks like book3s/32 doesn't set RI on machine check, so
> checking RI before calling die() will always be fatal
> allthought this is not an is
Hi Eric,
On 9/10/2020 11:20 AM, Auger Eric wrote:
Hi Diana,
On 9/7/20 4:34 PM, Diana Craciun OSS wrote:
Hi Eric,
On 9/4/2020 11:18 AM, Auger Eric wrote:
Hi Diana,
On 8/26/20 11:33 AM, Diana Craciun wrote:
The software uses a memory-mapped I/O command interface (MC portals) to
communicate w
Hi Michael,
On 2020-09-11 09:25, Michael Kerrisk (man-pages) wrote:
See my reply to patch 10/24.
As with 10/24, here's the new version.
Cheers,
Alex
From 911c791f0168851cdfdb30a65b6935011e4a161c Mon Sep 17 00:00:00 2001
From: Alejandr
On 9/10/2020 10:29 PM, Krzysztof Kozlowski wrote:
Fix kerneldoc warnings like:
drivers/crypto/caam/caamalg_qi2.c:73: warning: cannot understand function
prototype: 'struct caam_ctx'
drivers/crypto/caam/caamalg_qi2.c:2962: warning: cannot understand function
prototype: 'struct caam_hash_c
On 9/11/20 11:13 AM, Alejandro Colomar wrote:
> Hi Michael,
>
> On 2020-09-11 09:24, Michael Kerrisk (man-pages) wrote:
>> This may be true on Linux, but is not true on other systems.
>> For example, on HP-UX, according to one header file I'm
>> looking at, the return value is 'long'. >
>> These k
On 9/11/20 11:16 AM, Alejandro Colomar wrote:
> Hi Michael,
>
> On 2020-09-11 09:25, Michael Kerrisk (man-pages) wrote:
>> See my reply to patch 10/24.
>
> As with 10/24, here's the new version.
Thanks, Alex. Applied.
Cheers,
Michael
>
Add master clock provider support to STM32 I2S.
Signed-off-by: Olivier Moysan
---
Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml
b/Documentation/devicetree/bindings/sound
Add master clock generation support in STM32 I2S driver.
The master clock provided by I2S can be used to feed a codec.
Signed-off-by: Olivier Moysan
---
sound/soc/stm/stm32_i2s.c | 310 --
1 file changed, 266 insertions(+), 44 deletions(-)
diff --git a/sound/
Add master clock generation support in STM32 I2S driver.
Olivier Moysan (2):
ASoC: dt-bindings: add mclk provider support to stm32 i2s
ASoC: stm32: i2s: add master clock provider
.../bindings/sound/st,stm32-i2s.yaml | 4 +
sound/soc/stm/stm32_i2s.c | 310 ++
On 10. 09. 20 10:35, Arnd Bergmann wrote:
> On Thu, Sep 10, 2020 at 8:50 AM Michal Simek wrote:
>>> @@ -246,6 +245,23 @@ static int zynqmp_pm_remove(struct platform_device
>>> *pdev)
>>> return 0;
>>> }
>>>
>>> +static int __init do_init_finalize(void)
>>> +{
>>> + struct device_nod
From: Mateusz Nosek
Previously flags check was separated into two separated checks with two
separated branches. In case of presence of any of two mentioned flags,
the same effect on flow occurs. Therefore checks can be merged and one
branch can be avoided.
Signed-off-by: Mateusz Nosek
---
mm/p
On 11-09-20, 10:34, Stephan Gerhold wrote:
> On Fri, Aug 28, 2020 at 11:57:28AM +0200, Stephan Gerhold wrote:
> > It seems to me that there is more work needed to make such a use case
> > really work, but it's hard to speculate without a real example.
> >
>
> So it seems like we have a real examp
On Fri, 2020-09-11 at 09:34 +0100, Daniel Thompson wrote:
> On Fri, Sep 11, 2020 at 10:33:21AM +0800, Chunfeng Yun wrote:
> > On Thu, 2020-09-10 at 14:12 +0100, Daniel Thompson wrote:
> > > On Thu, Sep 10, 2020 at 04:21:45PM +0800, Chunfeng Yun wrote:
> > > > Use readl_poll_timeout_atomic() to simp
On Thu, Sep 10, 2020 at 10:04:02AM -0700, Nathan Chancellor wrote:
> Clang warns 100+ times in the vc4 driver along the lines of:
>
> drivers/gpu/drm/vc4/vc4_hdmi_phy.c:518:13: warning: implicit conversion
> from enumeration type 'enum vc4_hdmi_field' to different enumeration
> type 'enum vc4_hdmi
On Thu, Sep 10, 2020 at 10:18:32AM -0700, Nathan Chancellor wrote:
> Clang warns:
>
> drivers/gpu/drm/vc4/vc4_plane.c:901:27: warning: operator '?:' has lower
> precedence than '|'; '|' will be evaluated first
> [-Wbitwise-conditional-parentheses]
> fb->format->has_
Hi Alex,
On 9/10/20 11:13 PM, Alejandro Colomar wrote:
> Signed-off-by: Alejandro Colomar
> ---
> man3/inet_net_pton.3 | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/man3/inet_net_pton.3 b/man3/inet_net_pton.3
> index 00f94b9d4..d74a33d74 100644
> --- a/man3/inet_net
Even without in-kernel LAPIC we should allow writing '0' to
MSR_KVM_ASYNC_PF_EN as we're not enabling the mechanism. In
particular, QEMU with 'kernel-irqchip=off' fails to start
a guest with
qemu-system-x86_64: error: failed to set MSR 0x4b564d02 to 0x0
Fixes: 9d3c447c72fb2 ("KVM: X86: Fix async
On Fri, Sep 04, 2020 at 04:31:39PM -0400, Gabriel Krisman Bertazi wrote:
> +static inline void __set_tsk_syscall_intercept(struct task_struct *tsk,
> +unsigned int type)
> +{
> + tsk->syscall_intercept |= type;
> +
> + if (tsk->syscall_intercept)
> +
Hi Alex,
On 9/10/20 11:13 PM, Alejandro Colomar wrote:
> Hi Michael,
>
> I have a lot of patches here.
> Some of them are trivial, and some of them are not.
> I have them sorted by their contents more or less,
Yes, thanks for the sorting!
> but if you
> prefer completely unrelated email thread
Hi Michal,
> -Original Message-
> From: Michal Simek
> Sent: Friday, September 11, 2020 2:52 PM
> To: Arnd Bergmann ; Michal Simek
> Cc: Amit Sunil Dhamne ; Ard Biesheuvel
> ; Ingo Molnar ; gregkh
> ; Matt Fleming ;
> Sudeep Holla ; Heiner Kallweit
> ; Kees Cook ; Dmitry
> Torokhov ; Raj
This patch adds misc interrupt handler to detect and invoke PME/AER event.
In UniPhier PCIe controller, PME/AER signals are assigned to the same
signal as MSI by the internal logic. These signals should be detected by
the internal register, however, DWC MSI handler can't handle these signals.
DWC
The original subject up to v6 is
"PCI: uniphier: Add features for UniPhier PCIe host controller".
This adds a new function called by MSI handler in DesignWare PCIe framework,
that invokes PME and AER funcions to detect the factor from SoC-dependent
registers.
The iATU patches is split from this s
Add pcie_port_service_get_irq() that returns the virtual IRQ number
for specified portdrv service.
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/pcie/portdrv.h | 1 +
drivers/pci/pcie/portdrv_core.c | 16
2 files changed, 17 insertions(+)
diff --g
This adds msi_host_isr() callback function support to describe
SoC-dependent service triggered by MSI.
For example, when AER interrupt is triggered by MSI, the callback function
reads SoC-dependent registers and detects that the interrupt is from AER,
and invoke AER interrupts related to MSI.
Cc:
Hi Michael,
On 2020-09-11 11:19, Michael Kerrisk (man-pages) wrote:
On 9/11/20 11:16 AM, Alejandro Colomar wrote:
Hi Michael,
On 2020-09-11 09:25, Michael Kerrisk (man-pages) wrote:
See my reply to patch 10/24.
As with 10/24, here's the new version.
Thanks, Alex. Applied.
Cheers,
Mich
On Fri, Sep 04, 2020 at 04:31:40PM -0400, Gabriel Krisman Bertazi wrote:
> diff --git a/include/linux/entry-common.h b/include/linux/entry-common.h
> index efebbffcd5cc..72ce9ca860c6 100644
> --- a/include/linux/entry-common.h
> +++ b/include/linux/entry-common.h
> @@ -21,10 +21,6 @@
> # define _T
On 9/11/20 11:34 AM, Alejandro Colomar wrote:
>
> Hi Michael,
>
> On 2020-09-11 11:19, Michael Kerrisk (man-pages) wrote:
>> On 9/11/20 11:16 AM, Alejandro Colomar wrote:
>>> Hi Michael,
>>>
>>> On 2020-09-11 09:25, Michael Kerrisk (man-pages) wrote:
See my reply to patch 10/24.
>>>
>>> As w
To use mmio32, we also need to set regshift.
Signed-off-by: Hsin-Yi Wang
---
drivers/tty/serial/8250/8250_mtk.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/tty/serial/8250/8250_mtk.c
b/drivers/tty/serial/8250/8250_mtk.c
index 7b0dec14c8b80..41f4120abdf29 100644
--- a/drivers/tty
Hi Michael,
On 2020-09-11 11:31, Michael Kerrisk (man-pages) wrote:
Hi Alex,
On 9/10/20 11:13 PM, Alejandro Colomar wrote:
Signed-off-by: Alejandro Colomar
---
man3/inet_net_pton.3 | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/man3/inet_net_pton.3 b/man3/inet_net_pt
8250 devices may modify iotype in their own earlycon setup. For example:
8250_mtk and 8250_uniphier force iotype to be MMIO32. Print earlycon info
after match->setup to reflect actual earlycon info.
Signed-off-by: Hsin-Yi Wang
---
drivers/tty/serial/earlycon.c | 9 -
1 file changed, 8 in
In the init loop, if an error occurs in function 'dma_alloc_coherent',
then goto the err_cleanup section,
in the cleanup loop, after run i--,
the struct mtk_ring rising[i] will not be released,
causing a memory leak
Signed-off-by: Xiaoliang Pang
---
drivers/crypto/mediatek/mtk-platform.c | 4 ++-
On Thu, Sep 10, 2020 at 9:40 PM Hsin-Yi Wang wrote:
>
> On Thu, Sep 10, 2020 at 6:25 PM Matthias Brugger
> wrote:
> >
> > Hi,
> >
> > On 10/09/2020 10:43, Hsin-Yi Wang wrote:
> > > Set uart iotype to mmio32 to make earlycon work with stdout-path.
> > >
> > > Signed-off-by: Hsin-Yi Wang
> > > --
On Fri, Sep 04, 2020 at 04:31:43PM -0400, Gabriel Krisman Bertazi wrote:
> +struct syscall_user_dispatch {
> + char __user *selector;
> + unsigned long dispatcher_start;
> + unsigned long dispatcher_end;
> +};
> +int do_syscall_user_dispatch(struct pt_regs *regs)
> +{
> + struct s
On Fri, Sep 11, 2020 at 08:37:54AM +0200, Lukas Bulwahn wrote:
> - ocfs2-devel.oss.oracle.com
This is a normal mailing list, and I subscribed to it normally. It
might howerever be brken in various ways as oss.oracle.com seems
pretty much unmaintained.
> - rds-devel.oss.oracle.com
The same p
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