From: Joerg Roedel
Load the IDT right after switching to virtual addresses in head_64.S
so that the kernel can handle #VC exceptions.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/setup.h | 2 ++
arch/x86/kernel/head64.c | 18 ++
arch/x86/kernel/head_64.S| 28 ++
From: Joerg Roedel
Make sure segments are properly set up before setting up an IDT and
doing anything that might cause a #VC exception. This is later needed
for early exception handling.
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/head_64.S | 52 +++
1 f
From: Joerg Roedel
Move the assembly coded dispatch between page-faults and all other
exceptions to C code to make it easier to maintain and extend.
Also change the return-type of early_make_pgtable() to bool and make it
static.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/pgtable.h |
From: Joerg Roedel
Make sure there is a stack once the kernel runs from virual addresses.
At this stage any secondary CPU which boots will have lost its stack
because the kernel switched to a new page-table which does not map the
real-mode stack anymore.
This is needed for handling early #VC exc
From: Joerg Roedel
The code inserted by the stack protector does not work in the early
boot environment because it uses the GS segment, at least with memory
encryption enabled. Make sure the early code is compiled without this
feature enabled.
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/Ma
From: Joerg Roedel
Install an exception handler for #VC exception that uses a GHCB. Also
add the infrastructure for handling different exit-codes by decoding
the instruction that caused the exception and error handling.
Signed-off-by: Joerg Roedel
---
arch/x86/Kconfig
From: Joerg Roedel
Add the first handler for #VC exceptions. At stage 1 there is no GHCB
yet becaue the kernel might still be running on the EFI page table.
The stage 1 handler is limited to the MSR based protocol to talk to
the hypervisor and can only support CPUID exit-codes, but that is
enoug
From: Joerg Roedel
The functions are needed to map the GHCB for SEV-ES guests. The GHCB is
used for communication with the hypervisor, so its content must not be
encrypted. After the GHCB is not needed anymore it must be mapped
encrypted again so that the running kernel image can safely re-use th
From: Joerg Roedel
The code to setup idt_data is needed for early exception handling, but
set_intr_gate() can't be used that early because it has pv-ops in its
code path, which don't work that early.
Split out the idt_data initialization part from set_intr_gate() so
that it can be used separatly
From: Joerg Roedel
The xgetbv() function is needed in pre-decompression boot code, but
asm/fpu/internal.h can't be included there directly. Doing so opens
the door to include-hell due to various include-magic in
boot/compressed/misc.h.
Avoid that by moving xgetbv()/xsetbv() to a separate header
Dear Sami,
Am 13.07.20 um 01:34 schrieb Sami Tolvanen:
On Sat, Jul 11, 2020 at 9:32 AM Paul Menzel wrote:
Thank you very much for sending these changes.
Do you have a branch, where your current work can be pulled from? Your
branch on GitHub [1] seems 15 months old.
The clang-lto branch is
From: Joerg Roedel
Move these two functions from kernel/idt.c to include/asm/desc.h:
* init_idt_data()
* idt_init_desc()
These functions are needed to setup IDT entries very early and need to
be called from head64.c. To be usable this early these functions need to
be compiled wi
From: Joerg Roedel
With SEV-ES, exception handling is needed very early, even before the
kernel has cleared the bss segment. In order to prevent clearing the
currently used IDT, move the IDT to the data segment.
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/idt.c | 2 +-
1 file changed, 1 in
From: Joerg Roedel
The function can fail to create an identity mapping, check for that
and bail out if it happens.
Signed-off-by: Joerg Roedel
---
arch/x86/boot/compressed/ident_map_64.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/x86/boot/compressed/ident_m
From: Joerg Roedel
With the page-fault handler in place the identity mapping can be built
on-demand. So remove the code which manually creates the mappings and
unexport/remove the functions used for it.
Signed-off-by: Joerg Roedel
---
arch/x86/boot/compressed/ident_map_64.c | 6 ++
arch/x
> -Original Messages-
> From: "Mark Brown"
> Sent Time: 2020-07-14 17:44:06 (Tuesday)
> To: "Qing Zhang"
> Cc: linux-...@vger.kernel.org, linux-kernel@vger.kernel.org, "Xuefeng Li"
, "Tiezhu Yang"
> Subject: Re: [PATCH] spi: Use clk_prepare_enable and clk_disable_unprepare
>
> On Tu
From: Joerg Roedel
When booted through startup_64 the kernel keeps running on the EFI
page-table until the KASLR code sets up its own page-table. Without
KASLR the pre-decompression boot code never switches off the EFI
page-table. Change that by unconditionally switching to a kernel
controlled pa
From: Joerg Roedel
Install a page-fault handler to add an identity mapping to addresses
not yet mapped. Also do some checking whether the error code is sane.
This makes non SEV-ES machines use the exception handling
infrastructure in the pre-decompressions boot code too, making it less
likely to
From: Joerg Roedel
The file contains only code related to identity mapped page-tables.
Rename the file and compile it always in.
Signed-off-by: Joerg Roedel
---
arch/x86/boot/compressed/Makefile | 2 +-
arch/x86/boot/compressed/{kaslr_64.c => ident_map_64.c} | 9 +
From: Joerg Roedel
Call set_sev_encryption_mask() while still on the stage 1 #VC-handler,
because the stage 2 handler needs our own page-tables to be set up, to
which calling set_sev_encryption_mask() is a prerequisite.
Signed-off-by: Joerg Roedel
---
arch/x86/boot/compressed/head_64.S |
From: Joerg Roedel
Add code needed to setup an IDT in the early pre-decompression
boot-code. The IDT is loaded first in startup_64, which is after
EfiExitBootServices() has been called, and later reloaded when the
kernel image has been relocated to the end of the decompression area.
This allows
From: Joerg Roedel
Add a function to check whether an instruction has a REP prefix.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/insn-eval.h | 1 +
arch/x86/lib/insn-eval.c | 24
2 files changed, 25 insertions(+)
diff --git a/arch/x86/include/asm/insn
From: Joerg Roedel
Changing the function to take start and end as parameters instead of
start and size simplifies the callers, which don't need to calculate
the size if they already have start and end.
Signed-off-by: Joerg Roedel
---
arch/x86/boot/compressed/ident_map_64.c | 15 +--
From: Joerg Roedel
Factor out the code to fetch the instruction from user-space to a helper
function.
No functional changes.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/insn-eval.h | 2 ++
arch/x86/kernel/umip.c | 26 +-
arch/x86/lib/insn-eval.c
From: Joerg Roedel
The inat-tables.c file has some arrays in it that contain pointers to
other arrays. These pointers need to be relocated when the kernel
image is moved to a different location.
The pre-decompression boot-code has no support for applying ELF
relocations, so initialize these arra
From: Joerg Roedel
The x86-64 ABI defines a red-zone on the stack:
The 128-byte area beyond the location pointed to by %rsp is considered
to be reserved and shall not be modified by signal or interrupt
handlers. Therefore, functions may use this area for temporary data
that is not needed
From: Joerg Roedel
Hi,
here is the fourth version of the SEV-ES Guest Support patches. I
addressed the review comments sent to me for the previous version and
rebased the code v5.8-rc5.
The biggest change in this version is the IST handling code for the
#VC handler. I adapted the entry code for
From: Joerg Roedel
Move the definition of the x86 page-fault error code bits to the new
header file asm/trap_pf.h. This makes it easier to include them into
pre-decompression boot code. No functional changes.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/trap_pf.h | 24 +
From: Tom Lendacky
Add CPU feature detection for Secure Encrypted Virtualization with
Encrypted State. This feature enhances SEV by also encrypting the
guest register state, making it in-accessible to the hypervisor.
Signed-off-by: Tom Lendacky
Signed-off-by: Joerg Roedel
---
arch/x86/include
From: Joerg Roedel
Building a correct GHCB for the hypervisor requires setting valid bits
in the GHCB. Simplify that process by providing accessor functions to
set values and to update the valid bitmap.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/svm.h | 61 +++
From: Borislav Petkov
Use the shorthand to make it more readable.
No functional changes.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/svm.h | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h
inde
From: Tom Lendacky
Extend the vmcb_safe_area with SEV-ES fields and add a new
'struct ghcb' which will be used for guest-hypervisor communication.
Signed-off-by: Tom Lendacky
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/svm.h | 45 +-
arch/x86/kvm/s
Hi Borislav,
This is certainly a good idea, but I wonder whether we should be more pragmatic
about the printk ratelimiting while we give userspace time to react and update
their methodologies.
As one example, there is a common MSR hack which is verging on essential if
you're doing thermally
Hi Yoshinori and Rich,
can you take a look and possibly pick up the series below that untangles
and sorts out minor issues with the sh ioremap and dma code?
I sent this out a few times, but never got an answer. If you don't
want to pick up the series I can also take it through one of my trees
if
The sh build is full of warnings when building with gcc 9.2.1. While
fixing those would be great, at least avoid failing the build.
Signed-off-by: Christoph Hellwig
---
arch/sh/kernel/Makefile | 2 --
arch/sh/lib/Makefile| 2 --
arch/sh/mm/Makefile | 2 --
3 files changed, 6 deletions(-
On 7/14/2020 3:03 AM, Rob Herring wrote:
> On Sun, Jun 21, 2020 at 05:56:54PM +0300, Horia Geantă wrote:
>> RNGB block is found in some i.MX6 SoCs - 6SL, 6SLL, 6ULL, 6ULZ.
>> Add corresponding compatible strings.
>>
>> Note:
>>
>> Several NXP SoC from QorIQ family (P1010, P1023, P4080, P3041, P5020
On Thu, Jun 25, 2020 at 11:30 AM Vasily Averin wrote:
>
> fuse_writepages_fill uses following construction:
> if (wpa && ap->num_pages &&
> (A || B || C)) {
> action;
> } else if (wpa && D) {
> if (E) {
> the same action;
> }
> }
>
> - ap->num_pages chec
Ensure there is an order for the selects. Also remove a duplicate
one.
Signed-off-by: Christoph Hellwig
---
arch/sh/Kconfig | 95 -
1 file changed, 47 insertions(+), 48 deletions(-)
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 9fc2b010e93
There is no point in having __KERNEL__ ifdefs in headers not exported to
userspace.
Signed-off-by: Christoph Hellwig
---
arch/sh/include/asm/adc.h | 2 --
arch/sh/include/asm/addrspace.h| 3 ---
arch/sh/include/asm/bitops.h | 4
arch/sh/include/asm/cache.h| 2 --
ioremap_fixed is an internal implementation detail and should not be
exposed to drivers.
Signed-off-by: Christoph Hellwig
---
arch/sh/include/asm/io.h | 16
arch/sh/mm/init.c | 1 +
arch/sh/mm/ioremap.c | 1 +
arch/sh/mm/ioremap.h | 23 ++
Close "fd" before the return of map_vdso() and close "out_file"
in main().
Signed-off-by: Peng Fan
---
v2:
- add one missing fclose()
---
arch/mips/vdso/genvdso.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/mips/vdso/genvdso.c b/arch/mips/vdso/genvdso.c
index be57b83
Hi Christoph!
On 7/14/20 2:18 PM, Christoph Hellwig wrote:
> can you take a look and possibly pick up the series below that untangles
> and sorts out minor issues with the sh ioremap and dma code?
>
> I sent this out a few times, but never got an answer. If you don't
> want to pick up the series
Have a single definition that architetures can select.
Signed-off-by: Christoph Hellwig
---
arch/m68k/Kconfig | 4 +---
arch/m68k/Kconfig.machine | 1 +
arch/um/Kconfig | 4 +---
kernel/dma/Kconfig| 3 +++
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/a
Move the internal implementation details of ioremap out of line, no need
to expose any of this to drivers for a slow path API.
Signed-off-by: Christoph Hellwig
---
arch/sh/include/asm/io.h | 101 ++-
arch/sh/mm/ioremap.c | 53
2 files
The code handling non-coherent DMA depends on being able to remap code
as non-cached. But that can't be done without an MMU, so using this
option on NOMMU builds is broken.
Signed-off-by: Christoph Hellwig
---
arch/sh/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a
Both functions are only used by compiled in core code.
Signed-off-by: Christoph Hellwig
---
arch/sh/kernel/io_trapped.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/sh/kernel/io_trapped.c b/arch/sh/kernel/io_trapped.c
index 037aab2708b7ac..004ad0130b1038 100644
--- a/arch/sh/kernel/
Hi Marek,
On 7/14/2020 12:48 PM, Marek Szyprowski wrote:
> When gadget registration fails, one should not call usb_del_gadget_udc().
> Ensure this by setting gadget->udc to NULL. Also in case of a failure
I was able to reproduce issue. I'm Ok with this fix.
> there is no need to disable low-level
This switches to using common code for the DMA allocations, including
potential use of the CMA allocator if configured.
Switching to the generic code enables DMA allocations from atomic
context, which is required by the DMA API documentation, and also
adds various other minor features drivers star
No need to expose the details of trapped I/O to drivers.
Signed-off-by: Christoph Hellwig
---
arch/sh/include/asm/io.h | 1 -
arch/sh/kernel/ioport.c | 1 +
arch/sh/mm/ioremap.c | 1 +
3 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/a
Fine tune the HBP and HFP to avoid the dot noise on the left and right edges.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
b/drivers/gpu/drm/pa
Beacon EmbeddedWorks in introducing a development kit based on the
Renesas RZ/G2M platform. This patch adds the entry to the bindings
list.
Signed-off-by: Adam Ford
---
V2: New to series
diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml
b/Documentation/devicetree/bindings/arm
Beacon EmebeddedWorks, formerly Logic PD is introducing a new
SOM and development kit based on the RZ/G2M SoC from Renesas.
The SOM supports eMMC, WiFi and Bluetooth, along with a Cat-M1
cellular radio.
The Baseboard has Ethernet, USB, HDMI, stereo audio in and out,
along with a variety of push b
On Tue, Jul 14, 2020 at 2:16 PM Paul Menzel wrote:
>
> Dear Sami,
>
>
> Am 13.07.20 um 01:34 schrieb Sami Tolvanen:
> > On Sat, Jul 11, 2020 at 9:32 AM Paul Menzel wrote:
> >> Thank you very much for sending these changes.
> >>
> >> Do you have a branch, where your current work can be pulled from
On 7/14/20 5:10 AM, Petr Mladek wrote:
With procfs v3.3.16, the sysctl command doesn't print the set key and
value on error. This change breaks livepatch selftest test-ftrace.sh,
that tests the interaction of sysctl ftrace_enabled:
Make it work with all sysctl versions using '-q' option.
Expli
On Mon 13-07-20 11:30:44, Jonathan Corbet wrote:
> On Wed, 8 Jul 2020 19:19:05 +0200
> "Alexander A. Klimov" wrote:
>
> > The interface uses generic netlink framework (see
> > -http://lwn.net/Articles/208755/ and http://people.suug.ch/~tgr/libnl/ for
> > more
> > +https://lwn.net/Articles/2087
On 2020/7/14 2:11, Jaegeuk Kim wrote:
> Hi Daeho,
>
> Please take a look at this.
>
> https://git.kernel.org/pub/scm/linux/kernel/git/jaegeuk/f2fs.git/commit/?h=dev&id=35245180459aebf6d70fde88a538f0400a794aa6
I'm curious about what will happen if we call
sec_trim_file(F2FS_TRIM_FILE_ZEROOUT) on
On Mon 13-07-20 22:07:38, Alexander A. Klimov wrote:
> Rationale:
> Reduces attack surface on kernel devs opening the links for MITM
> as HTTPS traffic is much harder to manipulate.
>
> Deterministic algorithm:
> For each file:
> If not .svg:
> For each line:
> If doesn't contain `\bxm
Add node for the RNGB block.
Signed-off-by: Horia Geantă
---
arch/arm/boot/dts/imx6sll.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index fb5d3bc50c6b..0b622201a1f3 100644
--- a/arch/arm/boot/dts/imx6sll.dtsi
+++
Add node for the RNGB block.
Signed-off-by: Horia Geantă
Reviewed-by: Marco Felsch
---
arch/arm/boot/dts/imx6ull.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index fcde7f77ae42..9bf67490ac49 100644
--- a/arch/arm
Add support for RNGB found in some i.MX6 SoCs (6SL, 6SLL, 6ULL, 6ULZ),
based on RNGC driver (drivers/char/hw_random/imx-rngc.c).
This driver claims support also for RNGB (besides RNGC),
and is currently used only by i.MX25.
Note:
Several NXP SoC from QorIQ family (P1010, P1023, P4080, P3041, P50
Vladimir Oltean writes:
> On Mon, Jul 13, 2020 at 01:32:09AM +0300, Sergey Organov wrote:
[...]
>> > From the perspective of the mainline kernel, that can never happen.
>>
>> Yet in happened to me, and in some way because of the UAPI deficiencies
>> I've mentioned, as ethtool has entirely separ
Hi Shimoda-san,
On Tue, Jul 14, 2020 at 1:42 PM Yoshihiro Shimoda
wrote:
> > From: Geert Uytterhoeven, Sent: Tuesday, July 14, 2020 5:42 PM
> > On Tue, Jul 14, 2020 at 10:30 AM Lad, Prabhakar
> > wrote:
> > > On Tue, Jul 14, 2020 at 9:09 AM Geert Uytterhoeven
> > > wrote:
> > > > On Mon, Jul 1
RNGB block is found in some i.MX6 SoCs - 6SL, 6SLL, 6ULL, 6ULZ.
Add corresponding compatible strings.
Note:
Several NXP SoC from QorIQ family (P1010, P1023, P4080, P3041, P5020)
also have a RNGB, however it's part of the CAAM
(Cryptograhic Accelerator and Assurance Module) crypto accelerator.
In
This is my attempt at fixing one of the regressions we've seen[1] after
the introduction of per-zone atomic pools.
This combined with "dma-pool: Do not allocate pool memory from CMA"[2]
should fix the boot issues on Jeremy's RPi4 setup.
[1] https://lkml.org/lkml/2020/7/2/974
[2] https://lkml.org/
rng DT node was added without a compatible string.
i.MX driver for RNGC (drivers/char/hw_random/imx-rngc.c) also claims
support for RNGB, and is currently used for i.MX25.
Let's use this driver also for RNGB block in i.MX6SL.
Fixes: e29fe21cff96 ("ARM: dts: add device tree source for imx6sl SoC"
The function is only used once and can be simplified to a one-liner.
Signed-off-by: Nicolas Saenz Julienne
---
kernel/dma/pool.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/kernel/dma/pool.c b/kernel/dma/pool.c
index 39ca26fa41b5..318035e093fb 100644
--- a/ker
dma_coherent_ok() checks if a physical memory area fits a device's DMA
constraints.
Signed-off-by: Nicolas Saenz Julienne
---
include/linux/dma-direct.h | 1 +
kernel/dma/direct.c| 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/linux/dma-direct.h b/include/li
When allocating DMA memory from a pool, the core can only guess which
atomic pool will fit a device's constraints. If it doesn't, get a safer
atomic pool and try again.
Fixes: c84dc6e68a1d ("dma-pool: add additional coherent pools to map to gfp
mask")
Reported-by: Jeremy Linton
Suggested-by: Rob
dma-pool's dev_to_pool() creates the false impression that there is a
way to grantee a mapping between a device's DMA constraints and an
atomic pool. It tuns out it's just a guess, and the device might need to
use an atomic pool containing memory from a 'safer' (or lower) memory
zone.
To help miti
i.MX6 SL, SLL, ULL, ULZ SoCs have an RNGB block.
Since imx-rngc driver supports also rngb,
let's enable it for these SoCs too.
Signed-off-by: Horia Geantă
Reviewed-by: Martin Kaiser
Reviewed-by: Marco Felsch
---
drivers/char/hw_random/Kconfig| 2 +-
drivers/char/hw_random/imx-rngc.c | 3 +
Fix ip_defrag.sh when CONFIG_NF_DEFRAG_IPV6=m:
$ sudo ./ip_defrag.sh
+ set -e
+ mktemp -u XX
+ readonly NETNS=ns-rGlXcw
+ trap cleanup EXIT
+ setup
+ ip netns add ns-rGlXcw
+ ip -netns ns-rGlXcw link set lo up
+ ip netns exec ns-rGlXcw sysctl -w net.ipv4.ipfrag_high_thresh=900
+ ip netns e
On Wed, Jul 8, 2020 at 7:50 PM Daniele Alessandrelli
wrote:
>
> Hi,
>
> This patch-set adds initial support for a new Intel Movidius SoC code-named
> Keem Bay. The SoC couples an ARM Cortex A53 CPU with an Intel Movidius VPU.
>
> This initial patch-set enables only the minimal set of components re
On Mon, Jul 13, 2020 at 6:16 PM Miklos Szeredi wrote:
>
> On Mon, Jul 13, 2020 at 10:02 AM Vasily Averin wrote:
> >
> > On 7/11/20 7:01 AM, Miklos Szeredi wrote:
> > > On Thu, Jun 25, 2020 at 11:02 AM Vasily Averin wrote:
> > >>
> > >> In current implementation fuse_writepages_fill() tries to sh
Commit 7b668c064ec3 ("serial: 8250: Fix max baud limit in generic 8250
port") fixed limits of a baud rate setting for a generic 8250 port.
In other words since that commit the baud rate has been permitted to be
within [uartclk / 16 / UART_DIV_MAX; uartclk / 16], which is absolutely
normal for a sta
On 2020/7/13 21:09, Alexander A. Klimov wrote:
> Rationale:
> Reduces attack surface on kernel devs opening the links for MITM
> as HTTPS traffic is much harder to manipulate.
>
> Deterministic algorithm:
> For each file:
> If not .svg:
> For each line:
> If doesn't contain `\bxmlns\b`
Gcc report the following warning without CONFIG_MEMCG_KMEM:
mm/percpu-internal.h:145:29: warning: ‘pcpu_chunk_type’ defined
but not used [-Wunused-function]
static enum pcpu_chunk_type pcpu_chunk_type(struct pcpu_chunk *chunk)
^~~
Mark pcpu_chunk_type() a
On Thu, Jun 25, 2020 at 11:39 AM Vasily Averin wrote:
>
> fuse_writepages() ignores some errors taken from fuse_writepages_fill()
> I believe it is a bug: if .writepages is called with WB_SYNC_ALL
> it should either guarantee that all data was successfully saved
> or return error.
>
> Fixes: 26d61
If there is no valid MAC address in the device tree,
use a random MAC address.
Signed-off-by: Maxim Kochetkov
---
drivers/net/ethernet/freescale/gianfar.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/freescale/gianfar.c
b/drivers/net/ethernet/fre
Commit c8ff5841a90b ("rtc: pl031: switch to rtc_time64_to_tm/rtc_tm_to_time64")
seemed to have accidentally removed the call to pl031_alarm_irq_enable
from pl031_set_alarm while switching to 64-bit apis.
Let us add back the same to get the set alarm functionality back.
Fixes: c8ff5841a90b ("rtc:
> On Jul 13, 2020, at 11:31 PM, Nicholas Piggin wrote:
>
> Excerpts from Nicholas Piggin's message of July 14, 2020 3:04 pm:
>> Excerpts from Andy Lutomirski's message of July 14, 2020 4:18 am:
>>>
On Jul 13, 2020, at 9:48 AM, Nicholas Piggin wrote:
Excerpts from Andy Lutom
The race condition may happen if the UART reference clock is shared with
some other device (on Baikal-T1 SoC it's another DW UART port). In this
case if that device changes the clock rate while serial console is using
it the DW 8250 UART port might not only end up with an invalid uartclk
value save
Indeed according to the clk API if clk_round_rate() has successfully
accepted a rate, then in order setup the clock with value returned by the
clk_round_rate() the clk_set_rate() method must be called with the
original rate value.
Suggested-by: Russell King
Signed-off-by: Serge Semin
---
Chang
Some platforms can be designed in a way so the UART port reference clock
might be asynchronously changed at some point. In Baikal-T1 SoC this may
happen due to the reference clock being shared between two UART ports, on
the Allwinner SoC the reference clock is derived from the CPU clock, so
any CPU
On Tue, Jul 14, 2020 at 2:39 PM Horia Geantă wrote:
> diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
> index 8478eb757f3c..98f95a09ce55 100644
> --- a/drivers/char/hw_random/Kconfig
> +++ b/drivers/char/hw_random/Kconfig
> @@ -255,7 +255,7 @@ config HW_RANDOM_MXC_RNGA
Greg, Jiri. We've missed the last merge window. It would be pity to miss
the next one. Please review/merge in the series.
Regarding the patchset. It might be dangerous if an UART port reference
clock rate is suddenly changed. In particular the 8250 port drivers
(and AFAICS most of the tty drivers
On Tue, Jul 14, 2020 at 9:39 AM Horia Geantă wrote:
> static const struct of_device_id imx_rngc_dt_ids[] = {
> { .compatible = "fsl,imx25-rngb", .data = NULL, },
> + { .compatible = "fsl,imx6sl-rngb", .data = NULL, },
> + { .compatible = "fsl,imx6sll-rngb", .data = NULL, },
>
Really instead of twice checking the clk_round_rate() return value
we could do it once, and if it isn't error the clock rate can be changed.
By doing so we decrease a number of ret-value tests and remove a weird
goto-based construction implemented in the dw8250_set_termios() method.
Signed-off-by:
- On Jul 14, 2020, at 5:58 AM, Florian Weimer fwei...@redhat.com wrote:
> * Mathieu Desnoyers:
>
>> +/*
>> + * Very last field of the structure, to calculate size excluding padding
>> + * with offsetof().
>> + */
>> +char end[];
>> } __attribute__((aligned(4 * sizeof(__u6
On Tue, Jul 14, 2020 at 8:37 AM Viresh Kumar wrote:
>
> There is nothing schedutil specific in schedutil_cpu_util() and is used
> by fair.c as well. Allow it to be used by other parts of the kernel as
> well.
>
> Move it to core.c and rename it to effective_cpu_util(). While at it,
> rename "enum
On Tue, Jul 14, 2020 at 2:40 PM Sedat Dilek wrote:
> Did you sent out a new version of your patch?
> If yes, where can I get it from?
Just pushed a bunch of fixes including this one to
git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/fuse.git#for-next
Thanks,
Miklos
Hi Bixuan,
On Tue, 14 Jul 2020 13:41:01 + Bixuan Cui wrote:
>
> Gcc report the following warning without CONFIG_MEMCG_KMEM:
>
> mm/percpu-internal.h:145:29: warning: ‘pcpu_chunk_type’ defined
> but not used [-Wunused-function]
> static enum pcpu_chunk_type pcpu_chunk_type(struct pcpu_chunk
add support to update firmware by the devlink flashing API
Signed-off-by: Luo bin
---
V1~V2: create separate devlink priv data structure and remove boot_flag
V0~V1: remove the implementation from ethtool to devlink
drivers/net/ethernet/huawei/hinic/Makefile| 2 +-
drivers/net/ethernet/hua
The rename of generic_pm_domain.slave_links to
generic_pm_domain.child_links accidentally dropped the TAB to align the
member's comment. Re-add the lost TAB to restore indentation.
Fixes: 8d87ae48ced2dffd ("PM: domains: Fix up terminology with parent/child")
Signed-off-by: Geert Uytterhoeven
---
On Tue, Jul 14, 2020 at 2:53 PM Miklos Szeredi wrote:
>
> On Tue, Jul 14, 2020 at 2:40 PM Sedat Dilek wrote:
>
> > Did you sent out a new version of your patch?
> > If yes, where can I get it from?
>
> Just pushed a bunch of fixes including this one to
>
> git://git.kernel.org/pub/scm/linux/kerne
It's a Cluster Power Controller embedded into the MIPS IP cores.
Currently the corresponding dts node is supposed to have compatible
and reg properties.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
Cc: Alexey Malahov
---
Changelog prev:
- Reword the changelog summary - use shorter vers
It's a Common Device Memory Map controller embedded into the MIPS IP
cores, which dts node is supposed to have compatible and reg properties.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
---
Changelog prev:
- Lowercase the example hex'es.
Changelog v5:
- Consider address and size cells
Daniel, Rafael, Thomas (Gleixner), could you specifically take a look at
the last patch in this series? If you are ok with that, please explicitly
ack. We need at least one of your blessing to merge the series in, since
the code and DT-related patches here have been mostly reviewed. We've
missed th
Since having and mapping the CDMM block is platform specific, then
instead of just returning a zero-address, lets make the default CDMM
base address search method (mips_cdmm_phys_base()) to do something
useful. For instance to find the address in a dedicated dtb-node in
order to support of-based pl
Modern device tree bindings are supposed to be created as YAML-files
in accordance with DT schema. This commit replaces MIPS GIC legacy bare
text binding with YAML file. As before the binding file states that the
corresponding dts node is supposed to be compatible with MIPS Global
Interrupt Control
CDMM may be available not only on MIPS R2 architectures, but also on
newer MIPS R5 chips. For instance our P5600 chip has one. Let's mark
the CDMM bus being supported for that MIPS arch too.
Signed-off-by: Serge Semin
Reviewed-by: Thomas Bogendoerfer
---
drivers/bus/Kconfig | 2 +-
1 file chang
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