The pull request you sent on Fri, 3 Jul 2020 22:44:08 -0500:
> git://git.samba.org/sfrench/cifs-2.6.git tags/5.8-rc3-smb3-fixes
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/b8e516b36748fd87943e54596a8a6f04ec05f1a5
Thank you!
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The pull request you sent on Sat, 4 Jul 2020 06:07:01 +0100:
> git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs.git fixes
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/8b082a41dae7d420db649bffe86cf5af62121f11
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The pull request you sent on Sat, 4 Jul 2020 08:57:02 +0200:
> git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git
> for-linus-5.8b-rc4-tag
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/35e884f89df4c48566d745dc5a97a0d058d04263
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Remove unnecessary local variable 'ret' in blk_mq_dispatch_hctx_list().
Signed-off-by: Baolin Wang
---
block/blk-mq-sched.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/block/blk-mq-sched.c b/block/blk-mq-sched.c
index 1c52e56a19b1..b8db72cf1043 100644
--- a/block/blk-m
We've already validated the 'q->elevator' before calling
->ops.completed_request()
in blk_mq_sched_completed_request(), thus no need to validate rq->internal_tag
again,
and remove it.
Signed-off-by: Baolin Wang
---
block/blk-mq.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --
When sending mailbox in the work of aeq event, another aeq event
will be triggered. because the last aeq work is not exited and only
one work can be excuted simultaneously in the same workqueue, mailbox
sending function will return failure of timeout. We create and use
another workqueue to fix this
On 7/4/20 12:41 AM, Randy Dunlap wrote:
> Drop the doubled words "the" and "of".
>
> Signed-off-by: Randy Dunlap
> Cc: Jonathan Corbet
> Cc: linux-...@vger.kernel.org
> Cc: "David S. Miller"
> Cc: Jakub Kicinski
> Cc: net...@vger.kernel.org
> Cc: Wolfgang Grandegger
> Cc: Marc Kleine-Budde
>
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 959f53bd90c3ac70e5481199c6159f6314f9f910
Gitweb:
https://git.kernel.org/tip/959f53bd90c3ac70e5481199c6159f6314f9f910
Author:Valentin Schneider
AuthorDate:Fri, 03 Jul 2020 16:56:44 +01:00
Commi
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 8fa88a88d573093868565a1afba43b5ae5b3a316
Gitweb:
https://git.kernel.org/tip/8fa88a88d573093868565a1afba43b5ae5b3a316
Author:Valentin Schneider
AuthorDate:Fri, 03 Jul 2020 16:56:45 +01:00
Commi
On 02/07/2020 18:24, Alexander Graf wrote:
On 22.06.20 22:03, Andra Paraschiv wrote:
The Nitro Enclaves driver handles the enclave lifetime management. This
includes enclave creation, termination and setting up its resources such
as memory and CPU.
An enclave runs alongside the VM that spa
On 02/07/2020 18:24, Alexander Graf wrote:
On 22.06.20 22:03, Andra Paraschiv wrote:
The Nitro Enclaves (NE) driver communicates with a new PCI device, that
is exposed to a virtual machine (VM) and handles commands meant for
handling enclaves lifetime e.g. creation, termination, setting mem
On 02/07/2020 18:24, Alexander Graf wrote:
On 22.06.20 22:03, Andra Paraschiv wrote:
The Nitro Enclaves driver keeps an internal info per each enclave.
This is needed to be able to manage enclave resources state, enclave
notifications and have a reference of the PCI device that handles
com
For statically linked UML build it is important to take into account the
standard C-library implementation. Some implementations, notably glibc have
caveats: even when linked statically, the final program might require some
runtime dependencies, if certain functions are used within the code.
Consi
It is possible to produce a statically linked UML binary with UML_NET_VECTOR,
UML_NET_VDE and UML_NET_PCAP options enabled using alternative libc
implementations, which do not rely on NSS, such as musl.
Allow static linking in this case.
Signed-off-by: Ignat Korchagin
---
arch/um/Kconfig
musl toolchain and headers are a bit more strict. These fixes enable building
UML with musl as well as seem not to break on glibc.
Signed-off-by: Ignat Korchagin
---
arch/um/drivers/daemon_user.c | 1 +
arch/um/drivers/pcap_user.c | 12 ++--
arch/um/drivers/slip_user.c | 2 +-
arch
This is a continuation of [1]. Since I was able to produce a working UML binary
with UML_NET_VECTOR linked with musl with the changes included in the patches
here. I was compiling on Arch Linux, so hopefully all the latest versions of
the compiler, libraries and binutils.
I also tested allyesconfi
On Fri, Jul 3, 2020 at 9:19 PM Heiko Stuebner wrote:
>
> From: Heiko Stuebner
>
> Commit 1627f683636d ("clk: rockchip: Handle clock tree for rk3288w variant")
> added the check for rk3288w-specific clock-tree changes but in turn would
> require a double-compatible due to re-using the main rockchi
- converted from .txt to .yaml
- dual-link lvds port added and implemented
- dsi data-lanes property removed, it will be picked
from dsi0 ports
- VESA/JEIDA formats picked from panel-lvds dts
- proper indentation
- single-link and dual-link lvds description and
examples are added
- license modi
This driver is tested with two panels individually with Apq8016-IFC6309 board
https://www.inforcecomputing.com/products/single-board-computers-sbc/qualcomm-snapdragon-410-inforce-6309-micro-sbc
1. 1366x768@60 auo,b101xtn01 data-mapping = "jeida-24"
2. 800x480@60 innolux,at070tn92 data-mapping = "v
On 06/18/20 at 04:55pm, John Ogness wrote:
> The existing macro VMCOREINFO_OFFSET() can't be used for structures
> declared via typedef because "struct" is not part of type definition.
>
> Create another macro for this purpose.
>
> Signed-off-by: John Ogness
> ---
> include/linux/crash_core.h |
On 2020-07-03 15:28, Grzegorz Jaszczyk wrote:
On Thu, 2 Jul 2020 at 19:24, Marc Zyngier wrote:
On 2020-07-02 15:17, Grzegorz Jaszczyk wrote:
> From: Suman Anna
>
> The Programmable Real-Time Unit Subsystem (PRUSS) contains a local
> interrupt controller (INTC) that can handle various system i
Hi Valentin,
On 2020-07-03 16:56, Valentin Schneider wrote:
Hi,
while strolling around the different flow handlers, I tried to make
sense of
what preflow_handler() was about. Turns out no one uses those anymore,
but the
genirq support has remained in place.
If we needed to reintroduce some
rk3288 and rk3288w have a usb host0 ohci controller.
Although rk3288 ohci doesn't actually work on hardware, but
rk3288w ohci can work well.
So add usb host0 ohci node in rk3288 dtsi and the quirk in
ohci platform driver will disable ohci on rk3288.
Cc: William Wu
Signed-off-by: Jagan Teki
---
On 02/07/2020 18:09, Alexander Graf wrote:
On 22.06.20 22:03, Andra Paraschiv wrote:
The Nitro Enclaves PCI device is used by the kernel driver as a means of
communication with the hypervisor on the host where the primary VM and
the enclaves run. It handles requests with regard to enclave l
On Thu, Jul 02, 2020 at 12:41:39PM +0300, Vladimir Oltean wrote:
> On Thu, 2 Jul 2020 at 11:41, Russell King - ARM Linux admin
> wrote:
> >
> > On Thu, Jul 02, 2020 at 01:04:02AM +0300, Vladimir Oltean wrote:
> > > On Thu, 2 Jul 2020 at 00:53, Russell King - ARM Linux admin
> > > wrote:
> > > >
>
On Fri, Jul 3, 2020 at 3:13 AM Sungbo Eo wrote:
> On 2020-07-02 21:36, Andy Shevchenko wrote:
> >> + gpio->chip.ngpio = i2c_match_id(pca9570_id_table,
> >> client)->driver_data;
> >
> > Oh, avoid direct access to the table like this. And you may simply use
> > device_get_match_data().
>
> I
On Sat, Jul 04, 2020 at 12:19:40AM +0530, Alim Akhtar wrote:
> Adding Krzysztof's correct email address.
> Sorry about noise.
>
> > -Original Message-
> > From: Alim Akhtar
> > Sent: 03 July 2020 23:56
> > To: r...@kernel.org
> > Cc: devicet...@vger.kernel.org; linux-arm-ker...@lists.infr
Hi,
This serie cleans and adds regulator support to Panfrost devfreq.
This is mostly based on comment for the freshly introduced lima
devfreq.
We need to add regulator support because on Allwinner the GPU OPP
table defines both frequencies and voltages.
First patches [01-07] should not change th
This use devfreq variable that will be lock with spinlock in future
patches. We should either introduce a function to access this one
but as devfreq is optional let's just remove it.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_job.c | 4
1 f
We will later introduce regulators managed by OPP.
Only alloc regulators when it's needed. This also help use
to release the regulators only when they are allocated.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_device.c | 14 +-
drive
Devfreq cooling device framework is used in Panfrost
to throttle GPU in order to regulate its temperature.
Enable this driver for ARM64 SoC.
Signed-off-by: Clément Péron
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm6
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 3f7ceeb1a767..14257f7476b8 100644
-
This declaration can be avoided so change it.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 38 ++---
1 file changed, 18 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers
Some OPP tables specify voltage for each frequency. Devfreq can
handle these regulators but they should be get only 1 time to avoid
issue and know who is in charge.
If OPP table is probe don't init regulator.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/p
Introduce a boolean to know if opp table has been added.
With this, we can call panfrost_devfreq_fini() in case of error
and release what has been initialised.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 25 -
dri
Rename goto labels in device_init it will be easier to maintain.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_device.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c
b/drivers/gpu/drm/
Don't include not required headers and sort them.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/pan
Convert busy_count to a simple int protected by spinlock.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 43 +++--
drivers/gpu/drm/panfrost/panfrost_devfreq.h | 9 -
2 files changed, 40 insertions(+), 12 deletions(-)
Introduce a proper panfrost_devfreq to deal with devfreq variables.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 76 -
drivers/gpu/drm/panfrost/panfrost_devfreq.h | 20 +-
drivers/gpu/drm/panfrost/panfrost_devic
Add an Operating Performance Points table for the GPU to
enable Dynamic Voltage & Frequency Scaling on the H6.
The voltage range is set with minival voltage set to the target
and the maximal voltage set to 1.2V. This allow DVFS framework to
work properly on board with fixed regulator.
Signed-off-
Later we will introduce devfreq probing regulator if they
are present. As regulator should be probe only one time we
need to get this logic in the device_init().
panfrost_device is already taking care of devfreq_resume()
and devfreq_suspend(), so it's not totally illogic to move
the devfreq_init()
Add a simple cooling map for the GPU.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 22
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 78b1361
Hi,
On Sat, 4 Jul 2020 at 12:25, Clément Péron wrote:
>
> Hi,
>
> This serie cleans and adds regulator support to Panfrost devfreq.
> This is mostly based on comment for the freshly introduced lima
> devfreq.
>
> We need to add regulator support because on Allwinner the GPU OPP
> table defines bo
Hi,
On Sat, 4 Jul 2020 at 12:25, Clément Péron wrote:
>
> Signed-off-by: Clément Péron
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> b/arch/arm64/boot/dts/allwin
On 20-07-03 13:46:27, Ruslan Bilovol wrote:
> On Tue, Jun 30, 2020 at 4:58 AM Peter Chen wrote:
> >
> > On 20-06-29 23:18:45, Ruslan Bilovol wrote:
> > > UDC hardware may have endpoints with different maxpacket
> > > size. Current endpoint matching code takes first matching
> > > endpoint from the
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git
dev.2020.06.29b
branch HEAD: 1cd0309d69031e82ed876acbc696a5a71be65c7e fixup! torture: Add
scftorture to the rcutorture scripting
i386-tinyconfig vmlinux size:
==
From: Eric Auger
The VFIO API was enhanced to support nested stage control: a bunch of
new iotcls and usage guideline.
Let's document the process to follow to set up nested mode.
Cc: Kevin Tian
CC: Jacob Pan
Cc: Alex Williamson
Cc: Eric Auger
Cc: Jean-Philippe Brucker
Cc: Joerg Roedel
Cc:
Cc: Kevin Tian
CC: Jacob Pan
Cc: Alex Williamson
Cc: Eric Auger
Cc: Jean-Philippe Brucker
Cc: Joerg Roedel
Cc: Lu Baolu
Signed-off-by: Liu Yi L
Signed-off-by: Jacob Pan
---
v2 -> v3:
*) remove cap/ecap_mask in iommu_nesting_info.
---
drivers/iommu/intel/iommu.c | 81 ++
Shared Virtual Addressing (SVA), a.k.a, Shared Virtual Memory (SVM) on
Intel platforms allows address space sharing between device DMA and
applications. SVA can reduce programming complexity and enhance security.
This VFIO series is intended to expose SVA usage to VMs. i.e. Sharing
guest applicati
This patch exports iommu nesting capability info to user space through
VFIO. User space is expected to check this info for supported uAPIs (e.g.
PASID alloc/free, bind page table, and cache invalidation) and the vendor
specific format information for first level/stage page table that will be
bound
Recent years, mediated device pass-through framework (e.g. vfio-mdev)
is used to achieve flexible device sharing across domains (e.g. VMs).
Also there are hardware assisted mediated pass-through solutions from
platform vendors. e.g. Intel VT-d scalable mode which supports Intel
Scalable I/O Virtual
This patch refactors the vfio_iommu_type1_ioctl() to use switch instead of
if-else, and each cmd got a helper function.
Cc: Kevin Tian
CC: Jacob Pan
Cc: Alex Williamson
Cc: Eric Auger
Cc: Jean-Philippe Brucker
Cc: Joerg Roedel
Cc: Lu Baolu
Suggested-by: Christoph Hellwig
Signed-off-by: Liu
>From IOMMU p.o.v., PASIDs allocated and managed by external components
(e.g. VFIO) will be passed in for gpasid_bind/unbind operation. IOMMU
needs some knowledge to check the PASID ownership, hence add an interface
for those components to tell the PASID owner.
In latest kernel design, PASID owner
Nesting translation allows two-levels/stages page tables, with 1st level
for guest translations (e.g. GVA->GPA), 2nd level for host translations
(e.g. GPA->HPA). This patch adds interface for binding guest page tables
to a PASID. This PASID must have been allocated to user space before the
binding
This patch exposes PCIe PASID capability to guest for assigned devices.
Existing vfio_pci driver hides it from guest by setting the capability
length as 0 in pci_ext_cap_length[].
And this patch only exposes PASID capability for devices which has PCIe
PASID extended struture in its configuration s
This patch allows user space to request PASID allocation/free, e.g. when
serving the request from the guest.
PASIDs that are not freed by userspace are automatically freed when the
IOASID set is destroyed when process exits.
Cc: Kevin Tian
CC: Jacob Pan
Cc: Alex Williamson
Cc: Eric Auger
Cc:
From: Yi Sun
Current interface is good enough for SVA virtualization on an assigned
physical PCI device, but when it comes to mediated devices, a physical
device may attached with multiple aux-domains. Also, for guest unbind,
the PASID to be unbind should be allocated to the VM. This check requir
This patch provides an interface allowing the userspace to invalidate
IOMMU cache for first-level page table. It is required when the first
level IOMMU page table is not managed by the host kernel in the nested
translation setup.
Cc: Kevin Tian
CC: Jacob Pan
Cc: Alex Williamson
Cc: Eric Auger
Shared Virtual Addressing (a.k.a Shared Virtual Memory) allows sharing
multiple process virtual address spaces with the device for simplified
programming model. PASID is used to tag an virtual address space in DMA
requests and to identify the related translation structure in IOMMU. When
a PASID-cap
When an IOMMU domain with nesting attribute is used for guest SVA, a
system-wide PASID is allocated for binding with the device and the domain.
For security reason, we need to check the PASID passsed from user-space.
e.g. page table bind/unbind and PASID related cache invalidation.
Cc: Kevin Tian
Cc: Will Deacon
Cc: Robin Murphy
Cc: Eric Auger
Cc: Jean-Philippe Brucker
Suggested-by: Jean-Philippe Brucker
Signed-off-by: Liu Yi L
Signed-off-by: Jacob Pan
---
drivers/iommu/arm-smmu-v3.c | 29 +++--
drivers/iommu/arm-smmu.c| 29 +++--
IOMMUs that support nesting translation needs report the capability info
to userspace, e.g. the format of first level/stage paging structures.
This patch reports nesting info by DOMAIN_ATTR_NESTING. Caller can get
nesting info after setting DOMAIN_ATTR_NESTING.
Cc: Kevin Tian
CC: Jacob Pan
Cc:
On Fri, Jul 3, 2020 at 5:53 PM Uwe Kleine-König
wrote:
> On Sun, May 03, 2020 at 12:54:53PM +0200, Miquel Raynal wrote:
...
> > + ret = regmap_read(pca_chip->regmap, reg, &val);
> > + mutex_unlock(&pca_chip->i2c_lock);
> > + if (ret < 0) {
> > + dev_err(dev, "Cannot retri
On Fri, 3 Jul 2020 at 17:43, Emil Renner Berthing wrote:
>
> On Thu, 2 Jul 2020 at 22:07, Emil Renner Berthing wrote:
> >
> > Add basic jump-label implementation heavily based
> > on the ARM64 version.
> >
> > Tested on the HiFive Unleashed.
> >
> > Signed-off-by: Emil Renner Berthing
> > ---
>
Guenter Roeck 於 2020年7月4日 週六 上午3:28寫道：
>
> On Fri, Jul 3, 2020 at 12:11 PM Yu-Hsuan Hsu wrote:
> >
> > Guenter Roeck 於 2020年7月3日 週五 下午11:58寫道：
> > >
> > > On Fri, Jul 3, 2020 at 3:56 AM Enric Balletbo i Serra
> > > wrote:
> > > >
> > > > Hi Yu-Hsuan,
> > > >
> > > > On 3/7/20 11:40, Yu-Hsuan Hs
On Sat, 4 Jul 2020 at 13:23, Björn Töpel wrote:
> On Fri, 3 Jul 2020 at 17:43, Emil Renner Berthing wrote:
> > On Thu, 2 Jul 2020 at 22:07, Emil Renner Berthing wrote:
> > >
> > > Add basic jump-label implementation heavily based
> > > on the ARM64 version.
> > >
> > > Tested on the HiFive Unlea
在 2020/7/3 下午5:13, Konstantin Khlebnikov 写道:
>> @@ -976,7 +983,7 @@ static void __pagevec_lru_add_fn(struct page *page,
>> struct lruvec *lruvec)
>> */
>> void __pagevec_lru_add(struct pagevec *pvec)
>> {
>> - pagevec_lru_move_fn(pvec, __pagevec_lru_add_fn);
>> + pagevec_lru_mov
On Fri, Jul 3, 2020 at 1:32 PM Sergey Senozhatsky
wrote:
>
> On (20/07/02 09:05), Tony Lindgren wrote:
> > * Sergey Senozhatsky [200702 05:13]:
> > > On (20/06/30 11:02), Tony Lindgren wrote:
> > > > This conditional disable for irq_shared does not look nice to me
> > > > from the other device po
On Fri, Jul 3, 2020 at 1:53 PM Sergey Senozhatsky
wrote:
>
> On (20/07/02 11:20), Andy Shevchenko wrote:
> >
> > I didn't look into this deeply, but my understanding that this is something
> > for
> > special case when you have several UART ports sharing the IRQ (multi-port
> > card)
> > and IRQ
From: Marcus Cooper
Enable HDMI audio on the Orange Pi 2.
Signed-off-by: Marcus Cooper
Signed-off-by: Clément Péron
---
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
b/arch/arm/boot/dts/sun8i-h3
From: Marcus Cooper
Add the new DAI block for I2S2 which is used for HDMI audio.
Signed-off-by: Marcus Cooper
Signed-off-by: Clément Péron
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/b
From: Marcus Cooper
Enable HDMI audio on Pine64.
Signed-off-by: Marcus Cooper
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
b/arch/arm64/boot
From: Marcus Cooper
Enable HDMI audio on the Beelink X2.
Signed-off-by: Marcus Cooper
Signed-off-by: Clément Péron
---
arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
b/arch/arm/boot/dts/sun8i-h3-
Hi,
This a merge of serie:
- Add Add H6 I2S support https://patchwork.kernel.org/cover/11497007/
- Add Allwinner H3/H5/A64 HDMI audio
https://patchwork.kernel.org/cover/11510511/
I merge both serie because there is a similar issue regarding the I2S polarity.
This need to be investigated under a
From: Jernej Skrabec
H6 I2S is very similar to that in H3, except it supports up to 16
channels.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 227
1 file changed, 227 insertions(
From: Marcus Cooper
On the newer SoCs such as the H3 and A64 this is set by default
to transfer a 0 after each sample in each slot. However the A10
and A20 SoCs that this driver was developed on had a default
setting where it padded the audio gain with zeros.
This isn't a problem while we have o
From: Marcus Cooper
Add a simple-soundcard to link audio between HDMI and I2S.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 21 +++
1 file changed, 21 insertions(+)
diff --git a/ar
From: Marcus Cooper
Bypass the regmap cache when flushing or reading the i2s FIFOs.
Signed-off-by: Marcus Cooper
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index
Now that HDMI sound node is available in the SoC dtsi.
Enable it for this board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
b/arch/ar
From: Jernej Skrabec
Add a simple-soundcard to link audio between HDMI and I2S.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 33
1 file changed, 33 insertions(+)
diff --git a/a
From: Marcus Cooper
Extend the functionality of the driver to include support of 20 and
24 bits per sample.
Signed-off-by: Marcus Cooper
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi
From: Marcus Cooper
Add the new DAI block for I2S2 which is used for HDMI audio.
Signed-off-by: Marcus Cooper
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i
From: Marcus Cooper
Add a simple-soundcard to link audio between HDMI and I2S.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Signed-off-by: Clément Péron
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boo
From: Marcus Cooper
Some codecs such as i2s based HDMI audio and the Pine64 DAC require
a different amount of bit clocks per frame than what is calculated
by the sample width. Use the values obtained by the tdm slot bindings
to adjust the LRCLK width accordingly.
Signed-off-by: Marcus Cooper
Si
From: Jernej Skrabec
H6 I2S is very similar to H3, except that it supports up to 16 channels
and thus few registers have fields on different position.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Signed-off-by: Clément Péron
Acked-by: Maxime Ripard
Acked-by: Rob Herring
---
.
The FIFO TX reg is volatile and sun8i i2s register
mapping is different from sun4i.
Even if in this case it's doesn't create an issue,
Avoid setting some regs that are undefined in sun8i.
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 15 +++
1 file changed, 11 inser
On Fri, Jul 3, 2020 at 2:36 PM Calvin Johnson
wrote:
> On Wed, Jul 01, 2020 at 01:27:43PM +0300, Andy Shevchenko wrote:
> > On Wed, Jul 1, 2020 at 9:13 AM Calvin Johnson
> > wrote:
...
> > > +Package (2) {"mdio-handle", Package (){\_SB.MDI0}}
> >
> > Reference as a package?
On Sat, Jul 04, 2020 at 07:34:59PM +0800, Alex Shi wrote:
> That's a great idea! Guess what the new struct we need would be like this?
> I like to try this. :)
>
>
> diff --git a/include/linux/pagevec.h b/include/linux/pagevec.h
> index 081d934eda64..d62778c8c184 100644
> --- a/include/linux/page
Hi!
> * The first 3 patches tighten the PCI security using ACS, and take care
> of a border case.
> * The 4th patch takes care of PCI bug.
> * 5th and 6th patches expose a device's location into the sysfs to allow
> admin to make decision based on that.
I see no patch for Documentation -- new
Hi!
> > Sent: 02 July 2020 22:17
> > > > during a FLASH write or erase can cause from weakened cells, to much
> > > > larger damage. It is possible to harden the chip or the design against
> > > > this, but it is *expensive*. And even if warded off by hardening and no
> > > > FLASH damage happen
Hi David,
I love your patch! Yet something to improve:
[auto build test ERROR on s390/features]
[also build test ERROR on next-20200703]
[cannot apply to linux/master kvms390/next linus/master v5.8-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting pa
On Fri 2020-07-03 15:23:38, Kars Mulder wrote:
> > There ought to be one that returns a pointer to the first character
> > that isn't converted - but I'm no expert on the full range of these
> > functions.
>
> I've searched for a function that parses an int from a string and
> stores a pointer to
On Sat, Jul 04, 2020 at 02:35:46PM +0300, Andy Shevchenko wrote:
> On Fri, Jul 3, 2020 at 1:32 PM Sergey Senozhatsky
> wrote:
> > On (20/07/02 09:05), Tony Lindgren wrote:
> > > * Sergey Senozhatsky [200702 05:13]:
> > > > On (20/06/30 11:02), Tony Lindgren wrote:
...
> > This is, basically, an
Hi!
> Add support for registering per-LED device trigger.
>
> Names of private triggers need to be globally unique, but may clash
> with other private triggers. This is enforced during trigger
Globally unique name is going to be a problem, no? If you have two
keyboards with automatical backlight
On Fri, Jul 03, 2020 at 05:47:24PM -0700, Saravana Kannan wrote:
> On Thu, Jul 2, 2020 at 8:30 AM Ard Biesheuvel wrote:
> > On Tue, 23 Jun 2020 at 03:27, Saravana Kannan wrote:
> > > diff --git a/arch/arm64/kernel/module-plts.c
> > > b/arch/arm64/kernel/module-plts.c
> > > index 65b08a74aec6..0c
On Sat, 4 Jul 2020 at 13:35, Emil Renner Berthing wrote:
>
> On Sat, 4 Jul 2020 at 13:23, Björn Töpel wrote:
[...]
> > Indeed. And nice work! Can you respin the patch with the 32b fix
> > above, and also without the RFC tag?
>
> Yes, of course. If you don't mind I'll wait a bit and let this colle
Hi,
On Sat, Jul 04, 2020 at 12:25:34PM +0200, Clément Péron wrote:
> Add an Operating Performance Points table for the GPU to
> enable Dynamic Voltage & Frequency Scaling on the H6.
>
> The voltage range is set with minival voltage set to the target
> and the maximal voltage set to 1.2V. This all
On Sat, Jun 27, 2020 at 10:09:40PM +0200, Helge Deller wrote:
> On 27.06.20 15:43, Oscar Carter wrote:
> > In an effort to enable -Wcast-function-type in the top-level Makefile to
> > support Control Flow Integrity builds, remove all the function callback
> > casts.
> >
> > To do this remove the ca
Hello,
On Sat, Jul 04, 2020 at 02:04:59PM +0200, Pavel Machek wrote:
> Hi!
>
> > Add support for registering per-LED device trigger.
> >
> > Names of private triggers need to be globally unique, but may clash
> > with other private triggers. This is enforced during trigger
>
> Globally unique n
Hi!
> Are there some potentially serious problems that I should be aware of
> if I totally disable the CONFIG_ACPI option on the X86_64 platform?
>
> Would it do harm to the hardware?
>
> Thank you for your attention to this matter.
These machines are still mostly IBM-PC compatible, so it is li
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