Quoting Christophe JAILLET (2020-06-21 01:33:15)
> 'cpu_pm_init()' is only called via 'core_initcall'.
> It can be marked as __init to save a few bytes of memory.
>
> Signed-off-by: Christophe JAILLET
> ---
Reviewed-by: Stephen Boyd
Quoting patrick.rudo...@9elements.com (2020-04-07 01:29:06)
> From: Patrick Rudolph
>
> Make all CBMEM buffers available to userland. This is useful for tools
> that are currently using /dev/mem.
>
> Make the id, size and address available, as well as the raw table data.
>
> Tools can easily sc
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git master
branch HEAD: 360f28f385350da97cd144df62b875e875200e42 Merge branch 'WIP.fixes'
elapsed time: 722m
configs tested: 100
configs skipped: 4
The following configs have been built successfully.
More configs may be teste
On 2020/6/25 1:07, Jacob Pan wrote:
On Wed, 24 Jun 2020 14:54:49 +0800
Lu Baolu wrote:
Hi Jacob,
On 2020/6/24 1:03, Jacob Pan wrote:
IOMMU UAPI data has a user filled argsz field which indicates the
data length comes with the API call. User data is not trusted,
argsz must be validated based
In case the userspace daemon dies, then when is restarted it doesn't
know if there are any MRP instances in the kernel. Therefore extend the
netlink interface to allow the daemon to clear all MRP instances when is
started.
Signed-off-by: Horatiu Vultur
---
v2:
- use list_for_each_entry_safe in
Greetings,
I wonder why you continue neglecting my emails. Please, acknowledge
the receipt of this message in reference to the subject above as I
intend to send to you the details of the mail. Sometimes, try to check
your spam box because most of these correspondences fall out sometimes
in SPAM fo
Hi
On Thu, 25 Jun 2020 at 00:09, David Korth wrote:
> I've been manually setting the player IDs on Wii controllers when running
> multiplayer games by writing to the /sys/class/leds/ directory. Having the
> hid-wiimote driver do this itself significantly reduces setup time.
What do you mean with
On Thu, 25 Jun 2020, Greg KH wrote:
> On Thu, Jun 25, 2020 at 07:46:10AM +0100, Lee Jones wrote:
> > Kerneldoc syntax is used, but not complete. Descriptions required.
> >
> > Prevents warnings like:
> >
> > drivers/mfd/wm8350-core.c:136: warning: Function parameter or member
> > 'wm8350' not
On 2020/6/23 23:43, Jacob Pan wrote:
From: Liu Yi L
Set proper masks to avoid invalid input spillover to reserved bits.
Acked-by: Lu Baolu
Best regards,
baolu
Signed-off-by: Liu Yi L
Signed-off-by: Jacob Pan
---
include/linux/intel-iommu.h | 4 ++--
1 file changed, 2 insertions(+),
On 2020/6/23 23:43, Jacob Pan wrote:
Global pages support is removed from VT-d spec 3.0 for dev TLB
invalidation. This patch is to remove the bits for vSVA. Similar change
already made for the native SVA. See the link below.
Acked-by: Lu Baolu
Best regards,
baolu
Link: https://lkml.org/lkm
Hello,
syzbot found the following crash on:
HEAD commit:7ae77150 Merge tag 'powerpc-5.8-1' of git://git.kernel.org..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=15ddb42910
kernel config: https://syzkaller.appspot.com/x/.config?x=d195fe572fb15312
das
Quoting patrick.rudo...@9elements.com (2020-04-07 01:29:07)
> From: Patrick Rudolph
>
> Make all coreboot table entries available to userland. This is useful for
> tools that are currently using /dev/mem.
>
> Besides the tag and size also expose the raw table data itself.
>
> Update the ABI doc
Hi John,
On 06/18/20 at 04:55pm, John Ogness wrote:
> Hello,
>
> Here is a v3 for the first series to rework the printk
> subsystem. The v2 and history are here [0]. This first series
> only replaces the existing ringbuffer implementation. No locking
> is removed. No semantics/behavior of printk a
Hi,
I recently tried to connect my TV and WX4100 via two different DP->HDMI dongles.
One of them makes my main monitor to go dark, and system to lockup (I haven't
yet debugged this futher), and the other one seems to work,
most of the time, but sometimes causes a kernel panic on 5.8.0-rc1:
[ +
On 2020/6/23 23:43, Jacob Pan wrote:
DevTLB flush can be used for both DMA request with and without PASIDs.
The former uses PASID#0 (RID2PASID), latter uses non-zero PASID for SVA
usage.
This patch adds a check for PASID value such that devTLB flush with
PASID is used for SVA case. This is more
On 2020-06-25 01:55, Rob Clark wrote:
On Wed, Jun 24, 2020 at 4:57 AM Kalyan Thota
wrote:
This change enables dither block for primary interface
in display.
Enabled for 6bpc in the current version.
Signed-off-by: Kalyan Thota
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 45
++
Hi Uwe,
Thanks for your valuable feedback.
On 19/6/2020 2:02 pm, Uwe Kleine-König wrote:
> Hello Rahul,
>
> On Thu, Jun 18, 2020 at 08:05:13PM +0800, Rahul Tanwar wrote:
>> Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
>> This PWM controller does not have any other consumer,
Hello,
syzbot found the following crash on:
HEAD commit:7ae77150 Merge tag 'powerpc-5.8-1' of git://git.kernel.org..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=123db42910
kernel config: https://syzkaller.appspot.com/x/.config?x=be4578b3f1083656
das
Hello,
syzbot found the following crash on:
HEAD commit:7ae77150 Merge tag 'powerpc-5.8-1' of git://git.kernel.org..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=14a3bcf910
kernel config: https://syzkaller.appspot.com/x/.config?x=d195fe572fb15312
das
On Wed, Jun 24, 2020 at 07:53:20PM +0200, Peter Zijlstra wrote:
> On Tue, Jun 23, 2020 at 10:02:57AM +0100, Will Deacon wrote:
> > On Tue, Jun 23, 2020 at 10:36:51AM +0200, Peter Zijlstra wrote:
> > > In order to use in irqflags.h, we need to make sure
> > > asm/percpu.h does not itself depend on
Corr and eras_pos are updated to actual correction pattern and erasure
positions, but no_eras is not.
When this library is used to recover lost bytes, we normally memset the
lost trunk of bytes to zero as a placeholder. Unfortunately, if the lost
byte is zero, b[i] is zero too. Without correct no_
Add a new binding of the i2c-stm32f7 driver to enable the handling
of the SMBUS-Alert.
The I2C/SMBUS framework already provides a mechanism to enable SMBus-Alert
by naming an IRQ line "smbus_alert". However, on stm32, the SMBus-Alert is
part of the i2c IRQ. Using the smbus_alert naming here would
This serie adds SMBus Alert and SMBus Host-Notify features for the i2c-stm32f7.
This serie v2 rework comments from the 1st serie and replace the very generic
reg_client / unreg_client callback with HOST_NOTIFY only reg_hnotify_cli
and unreg_hnotify_cli callbacks.
Alain Volmat (4):
i2c: smbus: a
This patch adds the support for SMBus Host notify and SMBus Alert
extensions protocols
This patch introduces the st,smbus-alert binding in order to enable
SMBus-Alert handling. Indeed, while the I2C/SMBUS framework already
provide a mechanism to enable SMBus-Alert by naming an IRQ line
"smbus_aler
Addition of two callbacks reg_hnotify_cli and unreg_hnotify_cli
that can be implemented by adapter drivers in order to take action
whenever a client with HOST_NOTIFY flag is being registered to it.
Signed-off-by: Alain Volmat
---
v2: replace generic client reg/unreg callbacks with host-notify
SMBus Host-Notify protocol, from the adapter point of view
consist of receiving a message from a client, including the
client address and some other data.
It can be simply handled by creating a new slave device
and registering a callback performing the parsing of the
message received from the clie
On 2020-06-24 22:01, Andy Shevchenko wrote:
On Tue, Jun 23, 2020 at 9:06 AM Sungbo Eo wrote:
This patch adds support for the PCA9570 I2C GPO expander.
Tested in kernel 5.4 on an ipq40xx platform.
This is my first time submitting a whole driver patch, and I'm not really
familiar with this
Right now, smmu is using dma_alloc_coherent() to get memory to save queues
and tables. Typically, on ARM64 server, there is a default CMA located at
node0, which could be far away from node2, node3 etc.
with this patch, smmu will get memory from local numa node to save command
queues and page table
This is useful for at least two scenarios:
1. ARM64 smmu will get memory from local numa node, it can save its
command queues and page tables locally. Tests show it can decrease
dma_unmap latency at lot. For example, without this patch, smmu on
node2 will get memory from node0 by calling dma_alloc_
Ganapatrao Kulkarni has put some effort on making arm-smmu-v3 use local
memory to save command queues[1]. I also did similar job in patch
"iommu/arm-smmu-v3: allocate the memory of queues in local numa node"
[2] while not realizing Ganapatrao did that before.
But it seems it is much better to make
On Wed, Jun 24, 2020 at 01:09:24AM -0700, Prashant Malani wrote:
> Add mux control support for Thunderbolt compatibility mode.
>
> Suggested-by: Heikki Krogerus
> Co-developed-by: Azhar Shaikh
> Co-developed-by: Casey Bowman
> Signed-off-by: Prashant Malani
Reviewed-by: Heikki Krogerus
> --
On Wed, Jun 24, 2020 at 02:45:30PM -0700, Sami Tolvanen wrote:
> On Wed, Jun 24, 2020 at 11:27:37PM +0200, Peter Zijlstra wrote:
> > On Wed, Jun 24, 2020 at 01:31:42PM -0700, Sami Tolvanen wrote:
> > > With LTO, LLVM bitcode won't be compiled into native code until
> > > modpost_link. This change p
On Wed, Jun 24, 2020 at 02:49:25PM -0700, Sami Tolvanen wrote:
> On Wed, Jun 24, 2020 at 11:19:08PM +0200, Peter Zijlstra wrote:
> > On Wed, Jun 24, 2020 at 01:31:43PM -0700, Sami Tolvanen wrote:
> > > diff --git a/include/linux/compiler.h b/include/linux/compiler.h
> > > index 30827f82ad62..12b115
On 6/16/20 3:35 PM, Miklos Szeredi wrote:
> On Mon, Jun 15, 2020 at 7:59 AM Vasily Averin wrote:
>>
>> On 6/15/20 3:50 AM, kernel test robot wrote:
>>> FYI, we noticed the following commit (built with gcc-9):
>>>
>>> commit: 6b2fb79963fbed7db3ef850926d913518fd5c62f ("fuse: optimize
>>> writepages
On Thu, 2020-06-25 at 08:49 +0200, Julia Lawall wrote:
>
> On Wed, 24 Jun 2020, j...@perches.com wrote:
>
> > https://lore.kernel.org/patchwork/patch/649705/
> >
> > Any particular reason this wasn't applied?
> >
> > I ask because I added something similar recently to checkpatch.
>
> It probab
On 23/06/2020 20:28, Ezequiel Garcia wrote:
> The H264 interface is now ready to be part of the official
> public API.
>
> In addition, sanitize header includes.
>
> Signed-off-by: Ezequiel Garcia
> ---
> drivers/staging/media/hantro/hantro_hw.h | 5 ++---
> include/media/v4l2-
On Wed, Jun 24, 2020 at 03:08:22PM +, Yannick FERTRE wrote:
> Hello Angelo,
> thank for patch.
>
> Reviewed-by: Yannick Fertre
Patch applied, thanks.
-Daniel
>
>
>
> On 4/3/20 3:30 PM, Angelo Ribeiro wrote:
> > dw-mipi-dsi does not use any definition from drm_probe_helper.
> >
> > Cover
On Wed 24-06-20 20:14:17, Chris Wilson wrote:
> A general rule of thumb is that shrinkers should be fast and effective.
> They are called from direct reclaim at the most incovenient of times when
> the caller is waiting for a page. If we attempt to reclaim a page being
> pinned for active dma [pin_
NXP PCA9570 is 4-bit I2C GPO expander without interrupt functionality.
Its ports are controlled only by a data byte without register address.
As there is no other driver similar enough to be adapted for it, a new
driver is introduced here.
Signed-off-by: Sungbo Eo
---
v2:
* move the direction fu
This patch adds device tree bindings for the NXP PCA9570,
a 4-bit I2C GPO expander.
Signed-off-by: Sungbo Eo
---
I don't feel I can really maintain this driver, but it seems all yaml docs
have a maintainers field so I just added it...
---
.../bindings/gpio/gpio-pca9570.yaml | 42 ++
This patch uses the cleared_* in struct mmu_gather to set the
TTL field in flush_tlb_range().
Signed-off-by: Zhenyu Ye
Reviewed-by: Catalin Marinas
---
arch/arm64/include/asm/tlb.h | 29 -
arch/arm64/include/asm/tlbflush.h | 14 --
2 files changed, 3
This patch implement flush_{pmd|pud}_tlb_range() in arm64 by
calling __flush_tlb_range() with the corresponding stride and
tlb_level values.
Signed-off-by: Zhenyu Ye
---
arch/arm64/include/asm/pgtable.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/include/asm/pgtabl
On Wed, 24 Jun 2020, Sam Ravnborg wrote:
> Hi Lee.
>
> On Wed, Jun 24, 2020 at 04:43:21PM +0100, Lee Jones wrote:
> > On Wed, 24 Jun 2020, Sam Ravnborg wrote:
> >
> > > Hi Lee.
> > >
> > > On Wed, Jun 24, 2020 at 03:57:13PM +0100, Lee Jones wrote:
> > > > Attempting to clean-up W=1 kernel build
From: Joerg Roedel
Match the naming with other nested svm functions.
No functional changes.
Signed-off-by: Joerg Roedel
---
arch/x86/kvm/svm/svm.c | 6 +++---
arch/x86/kvm/svm/svm.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/sv
On Wed, Jun 24, 2020 at 02:31:36PM -0700, Nick Desaulniers wrote:
> On Wed, Jun 24, 2020 at 2:15 PM Peter Zijlstra wrote:
> >
> > On Wed, Jun 24, 2020 at 01:31:38PM -0700, Sami Tolvanen wrote:
> > > This patch series adds support for building x86_64 and arm64 kernels
> > > with Clang's Link Time O
Add a level-hinted parameter to __tlbi_user, which only gets used
if ARMv8.4-TTL gets detected.
ARMv8.4-TTL provides the TTL field in tlbi instruction to indicate
the level of translation table walk holding the leaf entry for the
address that is being invalidated.
This patch set the default level
In order to reduce the cost of TLB invalidation, ARMv8.4 provides
the TTL field in TLBI instruction. The TTL field indicates the
level of page table walk holding the leaf entry for the address
being invalidated. This series provide support for this feature.
When ARMv8.4-TTL is implemented, the o
From: Marc Zyngier
Add a level-hinted TLB invalidation helper that only gets used if
ARMv8.4-TTL gets detected.
Signed-off-by: Marc Zyngier
Signed-off-by: Zhenyu Ye
Reviewed-by: Catalin Marinas
---
arch/arm64/include/asm/tlbflush.h | 29 +
1 file changed, 29 inser
From: "Peter Zijlstra (Intel)"
tlb_flush_{pte|pmd|pud|p4d}_range() adjust the tlb->start and
tlb->end, then set corresponding cleared_*.
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Zhenyu Ye
Acked-by: Catalin Marinas
---
include/asm-generic/tlb.h | 55 ---
From: Joerg Roedel
Renaming is only needed in the svm.h header file.
No functional changes.
Signed-off-by: Joerg Roedel
---
arch/x86/kvm/svm/svm.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h
index 6ac4c00a5d82..6a1864
From: Joerg Roedel
Hi,
here is small series to follow-up on the review comments for moving
the kvm-amd module code to its own sub-directory. The comments were
only about renaming structs and symbols, so there are no functional
changes in these patches.
The comments addressed here are all from [
From: Joerg Roedel
Make it more clear what data structure these functions operate on.
No functional changes.
Signed-off-by: Joerg Roedel
---
arch/x86/kvm/svm/avic.c | 2 +-
arch/x86/kvm/svm/nested.c | 6 +++---
arch/x86/kvm/svm/sev.c| 2 +-
arch/x86/kvm/svm/svm.c| 44
From: Joerg Roedel
Make clear the symbols belong to the SVM code when they are built-in.
No functional changes.
Signed-off-by: Joerg Roedel
---
arch/x86/kvm/svm/nested.c | 2 +-
arch/x86/kvm/svm/svm.c| 88 +++
arch/x86/kvm/svm/svm.h| 6 +--
3 file
From: Marc Zyngier
In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL
feature allows TLBs to be issued with a level allowing for quicker
invalidation.
Let's detect the feature for now. Further patches will implement
its actual usage.
Signed-off-by: Marc Zyngier
Signed-off-by: Zhe
On 25/06/20 08:15, Sean Christopherson wrote:
> IMO, kvm_cpuid() is simply buggy. If KVM attempts to access a non-existent
> MSR then it darn well should warn.
>
> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> index 8a294f9747aa..7ef7283011d6 100644
> --- a/arch/x86/kvm/cpuid.c
> +++
> On 25 June 2020 at 02:42 Dave Jiang wrote:
>
>
>
>
> On 6/21/2020 12:24 AM, Vinod Koul wrote:
> > On 19-06-20, 16:31, Dave Jiang wrote:
> >>
> >>
> >> On 6/19/2020 3:47 PM, Federico Vaga wrote:
> >>> Hello,
> >>>
> >>> is there the possibility of using a DMA engine channel from userspace?
Hi David,
On 2020-06-22 11:20, David Brazdil wrote:
Hi Marc,
> - void *dst = lm_alias(__bp_harden_hyp_vecs + slot * SZ_2K);
> + char *vec = has_vhe() ? __bp_harden_hyp_vecs
> +: kvm_nvhe_sym(__bp_harden_hyp_vecs);
If we get this construct often, then something that a
On Thu, Jun 25, 2020 at 2:27 AM Anson Huang wrote:
>
> The i.MX SCU soc driver depends on SCU firmware driver, so it has to
> use platform driver model for proper defer probe operation, since
> it has no device binding in DT file, a simple platform device is
> created together inside the platform
On Tue, 2020-06-23 at 19:13 -0400, Tejun Heo wrote:
> Hello, Rick.
>
> On Mon, Jun 22, 2020 at 02:22:34PM -0700, Rick Lindsley wrote:
> > > I don't know. The above highlights the absurdity of the approach
> > > itself to
> > > me. You seem to be aware of it too in writing: 250,000 "devices".
> >
On 2020-06-25 06:03, kernel test robot wrote:
Hi David,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.8-rc2 next-20200624]
[cannot apply to kvmarm/next arm64/for-next/core
arm-perf/for-next/perf]
[If your patch
On Mon, 2020-06-15 at 10:41 +0200, Maxime Ripard wrote:
> Now that we have a clock driver for the clocks exposed by the firmware,
> let's add the device tree nodes for it.
>
> Tested-by: Nicolas Saenz Julienne
> Signed-off-by: Maxime Ripard
> ---
Applied for-next.
Thanks!
Nicolas
signature.
On 24.06.20 15:33, Bart Van Assche wrote:
> On 2020-06-23 04:10, Martin Kepplinger wrote:
>> This add a very conservative but simple implementation for runtime PM
>> to the sd scsi driver:
>> Resume when opened (mounted) and suspend when released (unmounted).
>>
>> Improvements that allow suspendin
On Thu 2020-06-18 16:55:19, John Ogness wrote:
> Replace the existing ringbuffer usage and implementation with
> lockless ringbuffer usage. Even though the new ringbuffer does not
> require locking, all existing locking is left in place. Therefore,
> this change is purely replacing the underlining
> diff --git a/drivers/staging/vc04_services/vchiq-mmal/Makefile
> b/drivers/staging/vc04_services/vchiq-mmal/Makefile
> index f8164c33aec3..b2a830f48acc 100644
> --- a/drivers/staging/vc04_services/vchiq-mmal/Makefile
> +++ b/drivers/staging/vc04_services/vchiq-mmal/Makefile
> @@ -5,4 +5,5 @@ obj-
On Thu, Jun 25, 2020 at 10:03:13AM +0200, Peter Zijlstra wrote:
> On Wed, Jun 24, 2020 at 02:31:36PM -0700, Nick Desaulniers wrote:
> > On Wed, Jun 24, 2020 at 2:15 PM Peter Zijlstra wrote:
> > >
> > > On Wed, Jun 24, 2020 at 01:31:38PM -0700, Sami Tolvanen wrote:
> > > > This patch series adds su
On Wed, Jun 24, 2020 at 05:18:01PM +0200, Christian Brauner wrote:
> On Wed, Jun 24, 2020 at 01:33:17AM -0700, Andrei Vagin wrote:
> > The order of vvar pages depends on whether a task belongs to the root
> > time namespace or not. In the root time namespace, a task doesn't have a
> > per-namespace
Hi Qiushi,
Thank you for your patch.
On 23/5/20 5:16, wu000...@umn.edu wrote:
> From: Qiushi Wu
>
> In function cros_ec_ishtp_probe(), "up_write" is already called
> before function "cros_ec_dev_init". But "up_write" will be called
> again after the calling of the function "cros_ec_dev_init" fa
On Wed, Jun 24, 2020 at 02:30:14PM -0700, Sami Tolvanen wrote:
> On Wed, Jun 24, 2020 at 11:15:40PM +0200, Peter Zijlstra wrote:
> > On Wed, Jun 24, 2020 at 01:31:38PM -0700, Sami Tolvanen wrote:
> > > This patch series adds support for building x86_64 and arm64 kernels
> > > with Clang's Link Time
On Thu 2020-06-18 16:55:19, John Ogness wrote:
> Replace the existing ringbuffer usage and implementation with
> lockless ringbuffer usage. Even though the new ringbuffer does not
> require locking, all existing locking is left in place. Therefore,
> this change is purely replacing the underlining
On Tue, Jun 23, 2020 at 06:19:45PM -0300, João H. Spies wrote:
> Previously marked as active high, but is in reality active low.
>
> Cc: sta...@vger.kernel.org
> Fixes: b1bfdb660516 ("MIPS: ingenic: DTS: Update GCW0 support")
> Signed-off-by: João H. Spies
> ---
> arch/mips/boot/dts/ingenic/gcw0
On Fri, Jun 19, 2020 at 12:05:23PM -0400, Peter Xu wrote:
> Use the general page fault accounting by passing regs into handle_mm_fault().
> It naturally solve the issue of multiple page fault accounting when page fault
> retry happened.
>
> Fix PERF_COUNT_SW_PAGE_FAULTS perf event manually for pag
On 24/06/2020 18:24, Jan Kiszka wrote:
On 24.06.20 13:45, Tero Kristo wrote:
If the RTI watchdog has been started by someone (like bootloader) when
the driver probes, we must adjust the initial ping timeout to match the
currently running watchdog window to avoid generating watchdog reset.
Signe
On Thu, Jun 25, 2020 at 09:16:03AM +0100, Marc Zyngier wrote:
> On 2020-06-25 06:03, kernel test robot wrote:
> > Hi David,
> >
> > Thank you for the patch! Perhaps something to improve:
> >
> > [auto build test WARNING on linus/master]
> > [also build test WARNING on v5.8-rc2 next-20200624]
> >
v3
Some edits for the description as suggested by Doug
v2
Remove raw value support for EPB
Srinivas Pandruvada (2):
cpufreq: intel_pstate: Allow enable/disable energy efficiency
cpufreq: intel_pstate: Allow raw energy performance preference value
Documentation/admin-guide/pm/intel_pstate.rs
By default intel_pstate driver disables energy efficiency by setting
MSR_IA32_POWER_CTL bit 19 for Kaby Lake desktop CPU model in HWP mode.
This CPU model is also shared by Coffee Lake desktop CPUs. This allows
these systems to reach maximum possible frequency. But this adds power
penalty, which so
On Wed, Jun 24, 2020 at 10:51:40PM -0700, Sean Christopherson wrote:
> Maybe s/unrecognized/unauthorized? Unrecognized implies the kernel doesn't
> know anything about the MSR being written, which may not hold true.
"unrecognized" in the sense that it is not on the whitelist above. It
contains on
Currently using attribute "energy_performance_preference", user space can
write one of the four per-defined preference string. These preference
strings gets mapped to a hard-coded Energy-Performance Preference (EPP) or
Energy-Performance Bias (EPB) knob.
These four values are supposed to cover bro
Hi,
Status update.
On 6/20/20 3:46 PM, Johan Jonker wrote:
> status: EXPERIMENTAL
> What works:
> uart2
> mmc
> emmc
> sd card
> usb2
///
USB2:
The usb2 port only works reliable with:
dr_mode = "host";
Question for Heiko:
Should we change that in rk3328.
Hi Matthias,
Thank you for you review.
On 22/6/20 12:14, Matthias Brugger wrote:
>
>
> On 19/06/2020 12:27, Enric Balletbo i Serra wrote:
>> Remove the unit address from the DT nodes that doesn't have a reg
>> property. This fixes the following unit name warnings:
>>
>> Warning (unit_address_
On Fri, 19 Jun 2020 at 11:02, Michael Ellerman wrote:
>
> Nathan Chancellor writes:
> >> It's kind of nuts that the zImage points to some arbitrary image
> >> depending on what's configured and the order of things in the Makefile.
> >> But I'm not sure how we make it less nuts without risking bre
Hi Matthias,
Thank you for your review.
On 22/6/20 12:33, Matthias Brugger wrote:
>
>
> On 19/06/2020 12:27, Enric Balletbo i Serra wrote:
>> Also known as the Lenovo IdeaPad Duet Chromebook.
>>
>> There are different krane boards with shared resources, hence a
>> mt8183-kukui-krane.dtsi was cr
On Wed, Jun 24, 2020 at 10:40 PM Andrzej Hajda wrote:
> On 24.06.2020 17:16, Robin Murphy wrote:
...
> I have proposed such thing in my previous iteration[1], except it was
> macro because of variadic arguments.
You may have a function with variadic arguments. Macros are beasts and
make in some
On Tue, Jun 23, 2020 at 01:55:21PM +0200, Christian Brauner wrote:
> On Fri, Jun 19, 2020 at 05:35:59PM +0200, Christian Brauner wrote:
> > So far setns() was missing time namespace support. This was partially due
> > to it simply not being implemented but also because vdso_join_timens()
> > could
On Thu, Jun 25, 2020 at 1:58 AM Kent Gibson wrote:
> On Wed, Jun 24, 2020 at 11:57:14PM +0800, Kent Gibson wrote:
> > On Wed, Jun 24, 2020 at 05:46:33PM +0300, Andy Shevchenko wrote:
> > > On Tue, Jun 23, 2020 at 7:03 AM Kent Gibson wrote:
...
> > > I stumbled over this myself, but...
> > >
> >
The following commit has been merged into the x86/misc branch of tip:
Commit-ID: a7e1f67ed29f0c339e2aa7483d13b085127566ab
Gitweb:
https://git.kernel.org/tip/a7e1f67ed29f0c339e2aa7483d13b085127566ab
Author:Borislav Petkov
AuthorDate:Wed, 10 Jun 2020 21:37:49 +02:00
Committe
On 24-06-20, 16:32, Quentin Perret wrote:
> Right, but I must admit that, looking at this more, I'm getting a bit
> confused with the overall locking for governors :/
>
> When in cpufreq_init_policy() we find a governor using
> find_governor(policy->last_governor), what guarantees this governor is
strsep() is neither standard C nor POSIX and used outside
the kernel code here. Using it here requires that the
build host supports it out of the box which is e.g.
not true for a Darwin build host and using a cross-compiler.
This leads to:
scripts/mod/modpost.c:145:2: warning: implicit declaration
Hi Saravana,
Thanks for your patch!
On Thu, Jun 25, 2020 at 5:24 AM Saravana Kannan wrote:
> Under the following conditions:
> - driver A is built in and can probe device-A
> - driver B is a module and can probe device-B
I think this is not correct: in my case driver B is builtin, too.
> - dev
On Thu, Jun 25, 2020 at 10:24:33AM +0200, Peter Zijlstra wrote:
> On Thu, Jun 25, 2020 at 10:03:13AM +0200, Peter Zijlstra wrote:
> > I'm sure Will will respond, but the basic issue is the trainwreck C11
> > made of dependent loads.
> >
> > Anyway, here's a link to the last time this came up:
> >
On 25/6/2020 1:58 pm, Uwe Kleine-König wrote:
> On Thu, Jun 25, 2020 at 12:23:54PM +0800, Tanwar, Rahul wrote:
>> Hi Philipp,
>>
>> On 18/6/2020 8:25 pm, Philipp Zabel wrote:
>>> Hi Rahul,
>>>
>>> On Thu, 2020-06-18 at 20:05 +0800, Rahul Tanwar wrote:
Intel Lightning Mountain(LGM) SoC conta
On Thu, Jun 25, 2020 at 10:59 AM Sungbo Eo wrote:
>
> NXP PCA9570 is 4-bit I2C GPO expander without interrupt functionality.
> Its ports are controlled only by a data byte without register address.
>
> As there is no other driver similar enough to be adapted for it, a new
> driver is introduced he
On Thu, Jun 18, 2020 at 01:08:25AM +0300, Jarkko Sakkinen wrote:
> From: Sean Christopherson
>
> Include SGX bit to the PF error codes and throw SIGSEGV with PF_SGX when
> a #PF with SGX set happens.
>
> CPU throws a #PF with the SGX bit in the event of Enclave Page Cache Map
In current implementation fuse_writepages_fill() tries to share the code:
for new wpa it calls tree_insert() with num_pages = 0
then switches to common code used non-modified num_pages
and increments it at the very end.
Though it triggers WARN_ON(!wpa->ia.ap.num_pages) in tree_insert()
WARNING: C
On Wed, Jun 24, 2020 at 03:41:05PM +0200, Rafael J. Wysocki wrote:
> On Wed, Jun 24, 2020 at 3:19 PM Dan Carpenter
> wrote:
> >
> > The "tick" variable isn't initialized if "lapic_timer_always_reliable"
> > is true.
>
> If lapic_timer_always_reliable is true, then
> static_cpu_has(X86_FEATURE_AR
On Fri, Jun 19, 2020 at 05:35:59PM +0200, Christian Brauner wrote:
> So far setns() was missing time namespace support. This was partially due
> to it simply not being implemented but also because vdso_join_timens()
> could still fail which made switching to multiple namespaces atomically
> problem
On Thu, Jun 25, 2020 at 11:44:21AM +0300, Andy Shevchenko wrote:
> On Thu, Jun 25, 2020 at 1:58 AM Kent Gibson wrote:
> > On Wed, Jun 24, 2020 at 11:57:14PM +0800, Kent Gibson wrote:
> > > On Wed, Jun 24, 2020 at 05:46:33PM +0300, Andy Shevchenko wrote:
> > > > On Tue, Jun 23, 2020 at 7:03 AM Kent
On Tue, Jun 23, 2020 at 1:55 AM Florian Fainelli wrote:
>
> On 6/22/20 3:00 AM, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski
> >
> > Functions should only be static inline if they're very short. This
> > devres helper is already over 10 lines and it will grow soon as we'll
> > be impr
Hi Sam,
On 24/6/20 9:07, Sam Ravnborg wrote:
> Hi Enric.
>
> On Tue, Jun 23, 2020 at 05:16:43PM +0200, Enric Balletbo i Serra wrote:
>> Hi Sam,
>>
>> Many thanks for your feedback. See my answers below.
>>
>> On 20/6/20 23:42, Sam Ravnborg wrote:
>>> Hi Enric.
>>>
>>> On Mon, Jun 15, 2020 at 10:5
On Thu, Jun 25, 2020 at 12:13 PM Kent Gibson wrote:
> On Thu, Jun 25, 2020 at 11:44:21AM +0300, Andy Shevchenko wrote:
> > On Thu, Jun 25, 2020 at 1:58 AM Kent Gibson wrote:
> > > On Wed, Jun 24, 2020 at 11:57:14PM +0800, Kent Gibson wrote:
...
> > > Perhaps you are referring to the case where
On 2020-06-24 17:44, Vincent Guittot wrote:
Some performance regression on reaim benchmark have been raised with
commit 070f5e860ee2 ("sched/fair: Take into account runnable_avg to classify
group")
The problem comes from the init value of runnable_avg which is initialized
with max value. Thi
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