Re: [PATCH stable-4.19.y] net: phy: reschedule state machine if AN has not completed in PHY_AN state

On Mon, Jun 01, 2020 at 12:00:16AM +0300, Vladimir Oltean wrote: > On Sun, 31 May 2020 at 03:19, Russell King - ARM Linux admin > wrote: > > > > On Sun, May 31, 2020 at 12:43:15AM +0300, Vladimir Oltean wrote: > > > From: Vladimir Oltean > > > > > > In kernel 4.19 (and probably earlier too) there

Re: [PATCH v7 1/4] bitops: Introduce the the for_each_set_clump macro

On Mon, Jun 1, 2020 at 4:07 AM Rikard Falkeborn wrote: > > + Emil who was working on a patch for this > > On Sun, May 31, 2020 at 02:00:45PM +0300, Andy Shevchenko wrote: > > On Sun, May 31, 2020 at 4:11 AM Syed Nayyar Waris > > wrote: > > > On Sat, May 30, 2020 at 2:50 PM Andy Shevchenko > > >

Re: [PATCH ghak124 v2] audit: log nftables configuration change events

note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Richard-Guy-Briggs/audit-log-nftables-configuration-change-event

Linux 5.7

So we had a fairly calm last week, with nothing really screaming "let's delay one more rc". Knock wood - let's hope we don't have anything silly lurking this time, like the last-minute wifi regression we had in 5.6.. But embarrassing regressions last time notwithstanding, it all looks fine. And mo

Writeback fixes for NFS

Hi Andrew, could you please queue these two patches (following). I think they have sufficient review and no remaining complaints. Thanks, NeilBrown signature.asc Description: PGP signature

[PATCH 1/2] iommu/vt-d: Make Intel SVM code 64-bit only

Current Intel SVM is designed by setting the pgd_t of the processor page table to FLPTR field of the PASID entry. The first level translation only supports 4 and 5 level paging structures, hence it's infeasible for the IOMMU to share a processor's page table when it's running in 32-bit mode. Let's

[PATCH 2/2] iommu/vt-d: Set U/S bit in first level page table by default

When using first-level translation for IOVA, currently the U/S bit in the page table is cleared which implies DMA requests with user privilege are blocked. As the result, following error messages might be observed when passing through a device to user level: DMAR: DRHD: handling fault status reg 3

[PATCH 0/2] iommu/vt-d: Two fixes for v5.8

Hi Joerg, This encloses two fixes for v5.8. - Make Intel SVM code 64-bit only - Set U/S bit to make IOVA over first level compatible with 2nd level translations. Best regards, baolu Lu Baolu (2): iommu/vt-d: Make Intel SVM code 64-bit only iommu/vt-d: Set U/S bit in first level page table

[PATCH 1/2] MM: replace PF_LESS_THROTTLE with PF_LOCAL_THROTTLE

PF_LESS_THROTTLE exists for loop-back nfsd (and a similar need in the loop block driver and callers of prctl(PR_SET_IO_FLUSHER)), where a daemon needs to write to one bdi (the final bdi) in order to free up writes queued to another bdi (the client bdi). The daemon sets PF_LESS_THROTTLE and gets a

[PATCH 2/2] MM: Discard NR_UNSTABLE_NFS, use NR_WRITEBACK instead.

After an NFS page has been written it is considered "unstable" until a COMMIT request succeeds. If the COMMIT fails, the page will be re-written. These "unstable" pages are currently accounted as "reclaimable", either in WB_RECLAIMABLE, or in NR_UNSTABLE_NFS which is included in a 'reclaimable'

[PATCH] staging: gasket: replace symbolic permissions

WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. + .attr = __ATTR(_name, S_IRUGO, _show_function, NULL), \ warning detected by checkpatch.pl Signed-off-by: Rodolfo C. Villordo --- drivers/staging/gasket/gasket_sysfs.h | 2

[PATCH] zswap: docs/vm: Fix typo accept_threshold_percent in zswap.rst

Recently, I switched over from swap-file to zramswap. When reading the Documentation/vm/zswap.rst file I fell over this typo. The parameter is called accept_threshold_percent not accept_threhsold_percent in /sys/module/zswap/parameters/ directory. Fixes: 45190f01dd402 ("mm/zswap.c: add allocatio

Re: [PATCH RESEND v8 1/2] ACPI / APEI: Add support to notify the vendor specific HW errors

Hi Shiju, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on pci/next] [also build test WARNING on linus/master v5.7-rc7] [cannot apply to pm/linux-next next-20200529] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system

Re: [PATCH v5 03/14] PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses

Hi Rob, On 5/28/2020 3:36 AM, Kishon Vijay Abraham I wrote: > Hi Rob, > > On 5/27/2020 10:07 PM, Rob Herring wrote: >> On Wed, May 27, 2020 at 4:49 AM Kishon Vijay Abraham I wrote: >>> >>> Hi Rob, >>> >>> On 5/26/2020 8:42 PM, Rob Herring wrote: On Sun, May 24, 2020 at 9:30 PM Kishon Vijay

[PATCH v31 03/21] x86/mm: x86/sgx: Signal SIGSEGV with PF_SGX

From: Sean Christopherson Include SGX bit to the PF error codes and throw SIGSEGV with PF_SGX when a #PF with SGX set happens. CPU throws a #PF with the SGX bit in the event of Enclave Page Cache Map (EPCM) conflict. The EPCM is a CPU-internal table, which describes the properties for a enclave

[PATCH v31 00/21] Intel SGX foundations

Intel(R) SGX is a set of CPU instructions that can be used by applications to set aside private regions of code and data. The code outside the enclave is disallowed to access the memory inside the enclave by the CPU access control. There is a new hardware unit in the processor called Memory Encryp

[PATCH v31 02/21] x86/cpufeatures: x86/msr: Add Intel SGX Launch Control hardware bits

From: Sean Christopherson Add X86_FEATURE_SGX_LC, which informs whether or not the CPU supports SGX Launch Control. Add MSR_IA32_SGXLEPUBKEYHASH{0, 1, 2, 3}, which when combined contain a SHA256 hash of a 3072-bit RSA public key. SGX backed software packages, so called enclaves, are always signe

[PATCH v31 01/21] x86/cpufeatures: x86/msr: Add Intel SGX hardware bits

From: Sean Christopherson Add X86_FEATURE_SGX from CPUID.(EAX=7, ECX=1), which informs whether the CPU has SGX. Add X86_FEATURE_SGX1 and X86_FEATURE_SGX2 from CPUID.(EAX=12H, ECX=0), which describe the level of SGX support available [1]. Add IA32_FEATURE_CONTROL_SGX_ENABLE. BIOS can use this bi

[PATCH v31 04/21] x86/sgx: Add SGX microarchitectural data structures

Define the SGX microarchitectural data structures used by various SGX opcodes. This is not an exhaustive representation of all SGX data structures but only those needed by the kernel. The data structures are described in: Intel SDM: 37.6 INTEL® SGX DATA STRUCTURES OVERVIEW Acked-by: Jethro Bee

[PATCH v31 07/21] x86/cpu/intel: Add nosgx kernel parameter

Add kernel parameter to disable Intel SGX kernel support. Tested-by: Sean Christopherson Reviewed-by: Sean Christopherson Signed-off-by: Jarkko Sakkinen --- Documentation/admin-guide/kernel-parameters.txt | 2 ++ arch/x86/kernel/cpu/feat_ctl.c | 9 + 2 files changed, 1

[PATCH v31 08/21] x86/sgx: Initialize metadata for Enclave Page Cache (EPC) sections

From: Sean Christopherson Enumerate Enclave Page Cache (EPC) sections via CPUID and add the data structures necessary to track EPC pages so that they can be easily borrowed for different uses. Embed section index to the first eight bits of the EPC page descriptor. Existing client hardware suppor

[PATCH v31 05/21] x86/sgx: Add wrappers for ENCLS leaf functions

ENCLS is a ring 0 instruction, which contains a set of leaf functions for managing an enclave. Enclaves are measured and signed software entities, which are protected by asserting the outside memory accesses and memory encryption. Add a two-layer macro system along with an encoding scheme to allow

[PATCH v31 09/21] x86/sgx: Add __sgx_alloc_epc_page() and sgx_free_epc_page()

Add __sgx_alloc_epc_page(), which iterates through EPC sections and borrows a page structure that is not used by anyone else. When a page is no longer needed it must be released with sgx_free_epc_page(). This function implicitly calls ENCLS[EREMOVE], which will return the page to the uninitialized

[PATCH v31 06/21] x86/cpu/intel: Detect SGX support

From: Sean Christopherson Configure SGX as part of feature control MSR initialization and update the associated X86_FEATURE flags accordingly. Because the kernel will require the LE hash MSRs to be writable when running native enclaves, disable X86_FEATURE_SGX (and all derivatives) if SGX Launch

[PATCH v31 12/21] x86/sgx: Add provisioning

In order to provide a mechanism for devilering provisoning rights: 1. Add a new device file /dev/sgx/provision that works as a token for allowing an enclave to have the provisioning privileges. 2. Add a new ioctl called SGX_IOC_ENCLAVE_SET_ATTRIBUTE that accepts the following data structure:

[PATCH v31 10/21] mm: Introduce vm_ops->may_mprotect()

From: Sean Christopherson Add vm_ops()->may_mprotect() to check additional constraints. SGX uses this callback to add two constraints: 1. Verify that the address range does not have holes: for each page address, there is an actual enclave page created. 2. Mapped permissions do not surpass th

[PATCH v31 17/21] x86/traps: Attempt to fixup exceptions in vDSO before signaling

From: Sean Christopherson vDSO functions can now leverage an exception fixup mechanism similar to kernel exception fixup. For vDSO exception fixup, the initial user is Intel's Software Guard Extensions (SGX), which will wrap the low-level transitions to/from the enclave, i.e. EENTER and ERESUME

[PATCH v31 16/21] x86/fault: Add helper function to sanitize error code

From: Sean Christopherson Add helper function to sanitize error code to prepare for vDSO exception fixup, which will expose the error code to userspace and runs before set_signal_archinfo(), i.e. suppresses the signal when fixup is successful. Acked-by: Jethro Beekman Signed-off-by: Sean Christ

[PATCH v31 15/21] x86/vdso: Add support for exception fixup in vDSO functions

From: Sean Christopherson The basic concept and implementation is very similar to the kernel's exception fixup mechanism. The key differences are that the kernel handler is hardcoded and the fixup entry addresses are relative to the overall table as opposed to individual entries. Hardcoding the

[PATCH v31 18/21] x86/vdso: Implement a vDSO for Intel SGX enclave call

From: Sean Christopherson An SGX runtime must be aware of the exceptions, which happen inside an enclave. Introduce a vDSO call that wraps EENTER/ERESUME cycle and returns the CPU exception back to the caller exactly when it happens. Kernel fixups the exception information to RDI, RSI and RDX. T

[PATCH v31 14/21] x86/sgx: ptrace() support for the SGX driver

Add VMA callbacks for ptrace() that can be used with debug enclaves. With debug enclaves data can be read and write the memory word at a time by using ENCLS(EDBGRD) and ENCLS(EDBGWR) leaf instructions. Acked-by: Jethro Beekman Signed-off-by: Jarkko Sakkinen --- arch/x86/kernel/cpu/sgx/encl.c |

[PATCH v31 21/21] x86/sgx: Update MAINTAINERS

Add the maintainer information for the SGX subsystem. Cc: Thomas Gleixner Cc: Borislav Petkov Signed-off-by: Jarkko Sakkinen --- MAINTAINERS | 11 +++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 091ec22c1a23..cdebc57f9901 100644 --- a/MAINTAINERS +++

[PATCH v31 20/21] docs: x86/sgx: Document SGX micro architecture and kernel internals

Document the Intel SGX kernel architecture. The fine-grained micro architecture details can be looked up from Intel SDM Volume 3D. Cc: linux-...@vger.kernel.org Acked-by: Randy Dunlap Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson Signed-off-by: Jarkko Sakkinen --- Do

[PATCH v31 19/21] selftests/x86: Add a selftest for SGX

Add a selftest for SGX. It is a trivial test where a simple enclave copies one 64-bit word of memory between two memory locations. Cc: linux-kselft...@vger.kernel.org Signed-off-by: Jarkko Sakkinen --- tools/testing/selftests/Makefile | 1 + tools/testing/selftests/sgx/.gitignore

Re: [V6 PATCH 2/2] ASoC: max98390: Added Amplifier Driver

On Fri, May 29, 2020 at 6:35 PM Mark Brown wrote: > > On Fri, May 29, 2020 at 05:04:36PM +0900, Steve Lee wrote: > > On Thu, May 28, 2020 at 8:54 PM Mark Brown wrote: > > > > > Reported-by: kbuild test robot > > > > Don't think the lkp bot asked for this driver! :P > > > Thanks, I will send sp

[PATCH 1/2] nbd: append module param and description following corresponding variables

A lot of drivers append the module parameter and its description following the corresponding variables (e.g., 'g_submit_queues' in null or 'admin_timeout' in nvme). This patch would do the same for 'nbds_max' and 'max_part' in nbd driver. This makes it much more friendly to cscope when reading the

[PATCH 2/2] nbd: remove unused 'NBD_MAGIC'

Remove 'NBD_MAGIC' as it is not used since commit 5ea8d10802ec ("nbd: separate out the config information"). Signed-off-by: Dongli Zhang --- drivers/block/nbd.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/block/nbd.c b/drivers/block/nbd.c index 74c1363702f5..83435ce141a8 100644

[PATCH 0/2] nbd: two cleanup

This is just cleanup without functional change. Thank you very much! Dongli Zhang

RE: [PATCH v10 10/10] arm64: dts: Add node for ufs exynos7

> -Original Message- > From: Krzysztof Kozlowski > Sent: 29 May 2020 13:36 > To: Alim Akhtar > Cc: r...@kernel.org; devicet...@vger.kernel.org; linux-s...@vger.kernel.org; > avri.alt...@wdc.com; martin.peter...@oracle.com; > kwmad@samsung.com; stanley@mediatek.com; > c...@codea

[PATCH v31 13/21] x86/sgx: Add a page reclaimer

There is a limited amount of EPC available. Therefore, some of it must be copied to the regular memory, and only subset kept in the SGX reserved memory. While kernel cannot directly access enclave memory, SGX provides a set of ENCLS leaf functions to perform reclaiming. This commits implements a p

RE: [PATCH v10 00/10] exynos-ufs: Add support for UFS HCI

> -Original Message- > From: Alim Akhtar > Sent: 28 May 2020 06:47 > To: r...@kernel.org > Cc: devicet...@vger.kernel.org; linux-s...@vger.kernel.org; k...@kernel.org; > avri.alt...@wdc.com; martin.peter...@oracle.com; > kwmad@samsung.com; stanley@mediatek.com; > c...@codeaurora

[PATCH net-next v4] hinic: add set_channels ethtool_ops support

add support to change TX/RX queue number with ethtool -L ethx combined Signed-off-by: Luo bin --- .../net/ethernet/huawei/hinic/hinic_ethtool.c | 40 +++ .../net/ethernet/huawei/hinic/hinic_main.c| 2 +- drivers/net/ethernet/huawei/hinic/hinic_tx.c | 5 +++ 3 files changed

[PATCH v31 11/21] x86/sgx: Linux Enclave Driver

Intel Software Guard eXtensions (SGX) is a set of CPU instructions that can be used by applications to set aside private regions of code and data. The code outside the SGX hosted software entity is disallowed to access the memory inside the enclave enforced by the CPU. We call these entities as enc

Re: [PATCH] staging: kpc2000: kpc_dma: Convert get_user_pages() --> pin_user_pages()

On 2020-05-31 10:51, Souptick Joarder wrote: In 2019, we introduced pin_user_pages*() and now we are converting get_user_pages*() to the new API as appropriate. [1] & [2] could be referred for more information. When pin_user_pages() returns numbers of partially mapped pages, those pages were not

Re: [PATCH] tpm_tis_spi: Don't send anything during flow control

On Thu, May 28, 2020 at 03:19:30PM -0700, Douglas Anderson wrote: > During flow control we are just reading from the TPM, yet our spi_xfer > has the tx_buf and rx_buf both non-NULL which means we're requesting a > full duplex transfer. > > SPI is always somewhat of a full duplex protocol anyway an

Re: [PATCHv5 1/3] optee: do drivers initialization before and after tee-supplicant run

On Fri, May 29, 2020 at 11:26:59AM +0300, Maxim Uvarov wrote: > Some drivers (like ftpm) can operate only after tee-supplicant > runs because of tee-supplicant provides things like storage > services.  This patch splits probe of non tee-supplicant dependable > drivers to the early stage, and after

My Dear in the lord

My Dear in the lord My name is Mrs. Mina A. Brunel I am a Norway Citizen who is living in Burkina Faso, I am married to Mr. Brunel Patrice, a politician who owns a small gold company in Burkina Faso; He died of Leprosy and Radesyge, in the year February 2010, During his lifetime he deposite

Re: [PATCH RFC] seccomp: Implement syscall isolation based on memory areas

> On May 31, 2020, at 4:50 PM, Brendan Shanks wrote: > >  >> On May 31, 2020, at 11:57 AM, Andy Lutomirski wrote: >> >> Using SECCOMP_RET_USER_NOTIF is likely to be considerably more >> expensive than my scheme. On a non-PTI system, my approach will add a >> few tens of ns to each syscall.

Re: [PATCH v4 1/4] KEYS: trusted: Add generic trusted keys framework

On Wed, May 06, 2020 at 03:10:14PM +0530, Sumit Garg wrote: > Current trusted keys framework is tightly coupled to use TPM device as > an underlying implementation which makes it difficult for implementations > like Trusted Execution Environment (TEE) etc. to provide trusked keys > support in case

[GIT PULL] hwmon updates for v5.8

Hi Linus, Please pull hwmon updates for Linux v5.8 from signed tag: git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git hwmon-for-v5.8 Thanks, Guenter -- The following changes since commit b9bbe6ed63b2b9f2c9ee5cbd0f2c946a2723f4ce: Linux 5.7-rc6 (2020-05-17 16:48:3

Re: [PATCH] input: tablet: aiptek: fix possible buffer overflow caused by bad DMA value in aiptek_irq()

Hi Jia-Ju, Thank you for the patch! Yet something to improve: [auto build test ERROR on input/next] [also build test ERROR on v5.7 next-20200529] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to speci

Re: [PATCH v4 1/4] KEYS: trusted: Add generic trusted keys framework

On Wed, May 06, 2020 at 03:10:14PM +0530, Sumit Garg wrote: > Current trusted keys framework is tightly coupled to use TPM device as > an underlying implementation which makes it difficult for implementations > like Trusted Execution Environment (TEE) etc. to provide trusked keys > support in case

[PATCH 1/3] arm64: dts: imx8qxp: add alias for lsio MU

From: Peng Fan Add lsio mu alias for all lsio MUs that could communicate with SCU, imx_scu_enable_general_irq_channel will parse the alias to get the mu resource id, if using other MU, not MU1, the `mu_resource_id` is not what we expect, so add alias to fix this issue. Signed-off-by: Peng Fan -

[PATCH 0/3] arm64: dts: imx8qxp: dtb aliases fix/update

From: Peng Fan Minor patchset to fix and update alias for i.MX8QXP Peng Fan (3): arm64: dts: imx8qxp: add alias for lsio MU arm64: dts: imx8qxp: add i2c aliases arm64: dts: imx8qxp: Add ethernet alias arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 10 ++ 1 file changed, 10 insertio

[PATCH 3/3] arm64: dts: imx8qxp: Add ethernet alias

From: Peng Fan Add ethernet alias, so bootloader code can use this to find the primary ethernet device, and set the MAC address. Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dt

[PATCH 2/3] arm64: dts: imx8qxp: add i2c aliases

From: Peng Fan The devices could be enumerated properly with aliases. Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 33

Re: [PATCH] crypto: hisilicon/qm - allow smaller reads in debugfs

Hi Dan & Zhou, On 2020/5/28 20:37, Dan Carpenter wrote: > Originally this code rejected any read less than 256 bytes. There > is no need for this artificial limit. > > Also I have changed the snprintf() functions to scnprintf(). The > difference is that snprintf() returns the number of bytes wh

Re: [PATCH v9 1/8] tpm: tpm_tis: Make implementation of read16, read32 and write32 optional

Plese, write the short summary as tpm: Make read{16, 32}() and write32() in tpm_tis_phy_ops optional On Tue, May 26, 2020 at 05:16:51PM +0300, amirmi...@gmail.com wrote: > From: Amir Mizinski > > Only tpm_tis can use memory-mapped I/O, which is truly mapped into > the kernel's memory space. The

Re: [PATCH 25/30] KVM: nSVM: leave guest mode when clearing EFER.SVME

On 5/29/20 8:39 AM, Paolo Bonzini wrote: According to the AMD manual, the effect of turning off EFER.SVME while a guest is running is undefined. We make it leave guest mode immediately, similar to the effect of clearing the VMX bit in MSR_IA32_FEAT_CTL. I see that svm_set_efer() is called i

Re: [PATCH v9 2/8] tpm: tpm_tis: Fix expected bit handling and send all bytes in one shot without last byte in exception

On Tue, May 26, 2020 at 05:16:52PM +0300, amirmi...@gmail.com wrote: > From: Amir Mizinski > > Incorrect implementation of send message was detected. We polled only > TPM_STS.stsValid bit and then we single-checked the TPM_STS.expect bit > value. > TPM_STS.expected bit should be checked at the sa

Re: [PATCH v6] support gce on mt6779 platform

Hi Jassi, Thanks for your comment On Sat, 2020-05-30 at 15:34 -0500, Jassi Brar wrote: > On Thu, May 28, 2020 at 12:05 PM Dennis YC Hsieh > wrote: > > > > This patch support gce on mt6779 platform. > > > > Change since v5: > > - spearate address shift code in client helper and mailbox controller

Re: [PATCH] irqchip/gic-v3-its: Don't try to move a disabled irq

On Sun, 2020-05-31 at 12:09 +0100, Marc Zyngier wrote: > > > > Not great indeed. But this is not, as far as I can tell, a GIC > > driver problem. > > > > The semantic of activate/deactivate (which maps to started/shutdown > > in the IRQ code) is that the HW resources for a given interrupt are >

[GIT PULL] Crypto Update for 5.8

Hi Linus: API: - Introduce crypto_shash_tfm_digest() and use it wherever possible. - Fix use-after-free and race in crypto_spawn_alg. - Add support for parallel and batch requests to crypto_engine. Algorithms: - Update jitter RNG for SP800-90B compliance. - Always use jitter RNG as seed in drbg

Re: [PATCH v3 07/18] nitro_enclaves: Init misc device providing the ioctl interface

On Tue, 2020-05-26 at 08:51 +0200, Greg KH wrote: > > And get them to sign off on it too, showing they agree with the design > decisions here :) Isn't it generally frowned upon to publish a patch with internal sign- off's on it already ? Or do you mean for us to publicly sign off once we have rev

Re: [PATCH] iommu/amd: Fix event counter availability check

Dear Alexander, Thank you very much for the patch. Am 31.05.20 um 09:22 schrieb Alexander Monakov: Adding Shuah Khan to Cc: I've noticed you've seen this issue on Ryzen 2400GE; can you have a look at the patch? Would be nice to know if it fixes the problem for you too. On Fri, 29 May 2020

Re: [PATCH v3 07/18] nitro_enclaves: Init misc device providing the ioctl interface

On Tue, 2020-05-26 at 14:44 +0200, Alexander Graf wrote: > So I really don't think an ioctl would be a great user experience. Same > for a sysfs file - although that's probably slightly better than the ioctl. What would be wrong with a sysfs file ? Another way to approach that makes sense from a

Re: [PATCH v3 02/18] nitro_enclaves: Define the PCI device interface

On Tue, 2020-05-26 at 20:01 +0300, Paraschiv, Andra-Irina wrote: > > On 26/05/2020 09:44, Greg KH wrote: > > On Tue, May 26, 2020 at 01:13:18AM +0300, Andra Paraschiv wrote: > > > +struct enclave_get_slot_req { > > > + /* Context ID (CID) for the enclave vsock device. */ > > > + u64 enclave_cid; >

Re: [GIT PULL] sh: remove sh5 support

On Sun, May 31, 2020 at 10:03:13AM +0200, John Paul Adrian Glaubitz wrote: > On 5/31/20 5:20 AM, Rob Landley wrote: > > On 5/30/20 3:08 AM, John Paul Adrian Glaubitz wrote: > >> On 5/29/20 7:53 PM, Rich Felker wrote: > >>> Frustratingly, I _still_ don't have an official tree on kernel.org for > >>>

Re: [PATCH v3 04/18] nitro_enclaves: Init PCI device driver

On Tue, 2020-05-26 at 21:35 +0300, Paraschiv, Andra-Irina wrote: > This was needed to have an identifier for the overall NE logic - PCI > dev, ioctl and misc dev. > > The ioctl and misc dev logic has pr_* logs, but I can update them to > dev_* with misc dev, then remove this prefix. Or #define

[GIT PULL] pstore updates for v5.8-rc1

Hi Linus, Please pull these pstore updates for v5.8-rc1. This is a pretty big set of changes (relative to past pstore pulls), but they've lived in -next for a while. The biggest change here is the ability to support a block device as a pstore backend, which has been desired for a while. A lot of a

Re: [PATCH v3 02/18] nitro_enclaves: Define the PCI device interface

On Wed, 2020-05-27 at 00:21 +0200, Greg KH wrote: > > There are a couple of data structures with more than one member and multiple > > field sizes. And for the ones that are not, gathered as feedback from > > previous rounds of review that should consider adding a "flags" field in > > there for fur

Re: [PATCH v3 07/18] nitro_enclaves: Init misc device providing the ioctl interface

On Wed, 2020-05-27 at 00:24 +0200, Greg KH wrote: > > Would you want random users to get the ability to hot unplug CPUs from your > > system? At unlimited quantity? I don't :). > > A random user, no, but one with admin rights, why not? They can do that > already today on your system, this isn't n

Re: [PATCH v3 01/18] nitro_enclaves: Add ioctl interface definition

On Wed, 2020-05-27 at 09:49 +0100, Stefan Hajnoczi wrote: > > What about feature bits or a API version number field? If you add > features to the NE driver, how will userspace detect them? > > Even if you intend to always compile userspace against the exact kernel > headers that the program will

[PATCH] f2fs: protect new segment allocation in expand_inode_data

From: Daeho Jeong Found a new segemnt allocation without f2fs_lock_op() in expand_inode_data(). So, when we do fallocate() for a pinned file and trigger checkpoint very frequently and simultaneously. F2FS gets stuck in the below code of do_checkpoint() forever. f2fs_sync_meta_pages(sbi, META,

Re: [PATCH] sh: Implement __get_user_u64() required for 64-bit get_user()

On Sun, May 31, 2020 at 12:43:11PM +0200, Geert Uytterhoeven wrote: > Hi Adrian, > > On Sun, May 31, 2020 at 11:59 AM John Paul Adrian Glaubitz > wrote: > > On 5/31/20 11:54 AM, John Paul Adrian Glaubitz wrote: > > > On 5/31/20 11:52 AM, Geert Uytterhoeven wrote: > > >> As this is the 64-bit vari

Re: [PATCH v3 07/18] nitro_enclaves: Init misc device providing the ioctl interface

On Thu, 2020-05-28 at 15:12 +0200, Greg KH wrote: > So at runtime, after all is booted and up and going, you just ripped > cores out from under someone's feet? :) > > And the code really handles writing to that value while the module is > already loaded and up and running? At a quick glance, it

Re: [PATCH V2] mm, memory_failure: don't send BUS_MCEERR_AO for action required error

On Sat, May 30, 2020 at 09:08:43AM +0200, Pankaj Gupta wrote: > > Some processes dont't want to be killed early, but in "Action Required" > > case, those also may be killed by BUS_MCEERR_AO when sharing memory > > with other which is accessing the fail memory. > > And sending SIGBUS with BUS_MCEERR

[PATCH] soundwire: bus: clock_stop: don't deal with UNATTACHED Slave devices

We don't need to do anything for the slave if it is unattached during clock stop prepare and exit sequences. Signed-off-by: Bard Liao --- drivers/soundwire/bus.c | 23 +-- 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/soundwire/bus.c b/drivers/soundwi

[PATCH RESEND] mm, swap: delete meaningless __add_to_swap_cache() declaration

From: Miaohe Lin Since commit 8d93b41c09d1 ("mm: Convert add_to_swap_cache to XArray"), __add_to_swap_cache and add_to_swap_cache are combined into one function. There is no __add_to_swap_cache() anymore. CC: Matthew Wilcox Reviewed-by: "Huang, Ying" Signed-off-by: Miaohe Lin --- include/lin

[PATCH] shmem, memcg: enable memcg aware shrinker

Since v4.19 commit b0dedc49a2da ("mm/vmscan.c: iterate only over charged shrinkers during memcg shrink_slab()") a memcg aware shrinker is only called when the per-memcg per-node shrinker_map indicates that the shrinker may have objects to release to the memcg and node. shmem_unused_huge_count and

Re: [PATCH RFC] KVM: arm64: Sidestep stage2_unmap_vm() on vcpu reset when S2FWB is supported

Hi Alex, On 2020/5/30 18:46, Alexandru Elisei wrote: Hi, On 4/20/20 5:10 PM, Alexandru Elisei wrote: [ For some unknown reasons, I had missed your reply one month ago. Sorry, I'm going to fix my email settings ... ] Hi, On 4/15/20 8:28 AM, Zenghui Yu wrote: stage2_unmap_vm() was introdu

Re: Re: [PATCH] drm/nouveau/clk/gm20b: Fix memory leak in gm20b_clk_new

Hi Ben, > > When gk20a_clk_ctor() returns an error code, pointer "clk" > > should be released. It's the same when gm20b_clk_new() > > returns from elsewhere following this call. > This shouldn't be necessary. If a subdev constructor fails, and > returns a pointer, the core will call the destruct

Re: [PATCH] opp: avoid uninitialized-variable use

On 30-05-20, 14:40, Arnd Bergmann wrote: > On Sat, May 30, 2020 at 11:21 AM Viresh Kumar wrote: > > On 29-05-20, 22:17, Arnd Bergmann wrote: > > > An uninitialized pointer is passed into another function but > > > --- a/drivers/opp/core.c > > > +++ b/drivers/opp/core.c > > > @@ -872,7 +872,7 @@ in

Re: Re: [PATCH] drm/nouveau/clk/gm20b: Fix memory leak in gm20b_clk_new

On Mon, 1 Jun 2020 at 13:27, wrote: > > > Hi Ben, > > > > When gk20a_clk_ctor() returns an error code, pointer "clk" > > > should be released. It's the same when gm20b_clk_new() > > > returns from elsewhere following this call. > > This shouldn't be necessary. If a subdev constructor fails, and >

Re: Re: [PATCH] drm/nouveau/clk/gm20b: Fix memory leak in gm20b_clk_new

On Mon, 1 Jun 2020 at 13:37, Ben Skeggs wrote: > > On Mon, 1 Jun 2020 at 13:27, wrote: > > > > > > Hi Ben, > > > > > > When gk20a_clk_ctor() returns an error code, pointer "clk" > > > > should be released. It's the same when gm20b_clk_new() > > > > returns from elsewhere following this call. > >

[PATCH V2] dt-bindings: thermal: Convert qoriq to json-schema

Convert the qoriq thermal binding to DT schema format using json-schema Signed-off-by: Anson Huang --- Changes since V1: - add 'maxItems' for 'fsl,tmu-range' property; - add 'minItems'/'maxItems' and items descriptions for 'fsl,tmu-calibration' property; - remove descript

[PATCH] misc: atmel-ssc: lock with mutex instead of spinlock

Uninterruptible context is not needed in the driver and causes lockdep warning because of mutex taken in of_alias_get_id(). Convert the lock to mutex to avoid the issue. Cc: sta...@vger.kernel.org Signed-off-by: Michał Mirosław --- drivers/misc/atmel-ssc.c | 24 1 file c

[PATCH V2 1/3] dt-bindings: mailbox: imx-mu: support i.MX8M

From: Peng Fan Add i.MX8MQ/M/N/P compatible string to support i.MX8M SoCs Signed-off-by: Peng Fan --- Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation

[PATCH V2 0/3] imx8m: add mu support

From: Peng Fan V2: Add dt-bindings Merge dts changes into one patch, since all is to add mu node Add mu dt bindings Add mu node Add i.MX8MP mu root clk Peng Fan (3): dt-bindings: mailbox: imx-mu: support i.MX8M arm64: dts: imx8m: add mu node clk: imx8mp: add mu root clk Documentation/

Re: [PATCH] usb: gadget: f_acm: don't disable disabled EP

On 20-05-30 19:15:52, Michał Mirosław wrote: > On Sat, May 30, 2020 at 01:03:17AM +, Peter Chen wrote: > > > > > > > @@ -425,9 +425,11 @@ static int acm_set_alt(struct usb_function *f, > > > > > unsigned > > > intf, unsigned alt) > > > > > /* we know alt == 0, so this is an activation

[PATCH V2 3/3] clk: imx8mp: add mu root clk

From: Peng Fan Add mu root clk for mu mailbox usage. Signed-off-by: Peng Fan Reviewed-by: Dong Aisheng --- drivers/clk/imx/clk-imx8mp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index b4d9db9d5bf1..ca747712400f 100644 --- a

[PATCH V2 2/3] arm64: dts: imx8m: add mu node

From: Peng Fan Add mu node to let A53 could communicate with M Core. Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 9 + arch/arm64/boot/dts/freescale/imx8mn.dtsi | 9 + arch/arm64/boot/dts/freescale/imx8mp.dtsi | 9 + arch/arm64/boot/dts/freesc

[PATCH] riscv: fix build warning of missing prototypes

Add the missing header in file, it was losed in original implementation. The warning message as follows: - no previous prototype for 'patch_text_nosync' [-Wmissing-prototypes] - no previous prototype for 'patch_text' [-Wmissing-prototypes] Signed-off-by: Zong Li Reported-by: kbuild test robot

WARNING in snd_usbmidi_submit_urb/usb_submit_urb

Hello, syzbot found the following crash on: HEAD commit:bdc48fa1 checkpatch/coding-style: deprecate 80-column warn.. git tree: upstream console output: https://syzkaller.appspot.com/x/log.txt?x=15d6458610 kernel config: https://syzkaller.appspot.com/x/.config?x=129ea1e5950835e5 das

[PATCH V2] mailbox: imx: Add context save/restore for suspend/resume

From: Dong Aisheng For "mem" mode suspend on i.MX8 SoCs, MU settings could be lost because its power is off, so save/restore is needed for MU settings during suspend/resume. However, the restore can ONLY be done when MU settings are actually lost, for the scenario of settings NOT lost in "freeze"

Re: [PATCH] i2c: sh_mobile: Fix compilation warning

On 29-05-20, 14:12, Wolfram Sang wrote: > On Thu, May 09, 2019 at 10:13:46AM +0530, Viresh Kumar wrote: > > This currently generates a warning: > > > > drivers/i2c/busses/i2c-sh_mobile.c: In function 'sh_mobile_i2c_isr': > > drivers/i2c/busses/i2c-sh_mobile.c:399:26: warning: 'data' may be used >

Re: [PATCH] input: tablet: aiptek: fix possible buffer overflow caused by bad DMA value in aiptek_irq()

rg/pub/scm/linux/kernel/git/dtor/input.git next config: mips-randconfig-r032-20200531 (attached as .config) compiler: mipsel-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmo

Re: [RFC][PATCH 0/2] Add support for using reserved memory for ima buffer pass

On 5/22/20 9:08 PM, Thiago Jung Bauermann wrote: Hello Prakhar, Prakhar Srivastava writes: On 5/12/20 4:05 PM, Rob Herring wrote: On Wed, May 06, 2020 at 10:50:04PM -0700, Prakhar Srivastava wrote: Hi Mark, Please don't top post. This patch set currently only address the Pure DT impl

Re: [PATCH] OPP: Check for bandwidth values before creating icc paths

On 29-05-20, 19:47, Sibi Sankar wrote: > opp_np needs to be subjected > to NULL check as well. No, it isn't. It should already be valid and is set by the OPP core. Actually we don't need to do of_node_get(opp_table->np) and just use np, I did that to not have a special case while putting the resou

Re: [PATCH v6 3/6] irqchip: RISC-V per-HART local interrupt controller driver

On Sun, May 31, 2020 at 4:23 PM Marc Zyngier wrote: > > On 2020-05-31 11:06, Anup Patel wrote: > > On Sun, May 31, 2020 at 3:03 PM Marc Zyngier wrote: > >> > >> On 2020-05-31 06:36, Anup Patel wrote: > >> > On Sat, May 30, 2020 at 5:31 PM Marc Zyngier wrote: > >> > >> [...] > >> > >> >> >

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