From: Ira Weiny
When preventing DAX and journaling on an inode. Use the effective DAX
check rather than the mount option.
This will be required to support per inode DAX flags.
Reviewed-by: Jan Kara
Signed-off-by: Ira Weiny
---
fs/ext4/ioctl.c | 4 ++--
1 file changed, 2 insertions(+), 2 del
From: Ira Weiny
Verity and DAX are incompatible. Changing the DAX mode due to a verity
flag change is wrong without a corresponding address_space_operations
update.
Make the 2 options mutually exclusive by returning an error if DAX was
set first.
(Setting DAX is already disabled if Verity is s
From: Ira Weiny
We add 'always', 'never', and 'inode' (default). '-o dax' continues to
operate the same which is equivalent to 'always'. This new
functionality is limited to ext4 only.
Specifically we introduce a 2nd DAX mount flag EXT4_MOUNT2_DAX_NEVER and set
it and EXT4_MOUNT_DAX_ALWAYS app
Minor comment style edits.
Signed-off-by: Jonathan Albrieux
Reviewed-by: Andy Shevchenko
---
drivers/iio/magnetometer/ak8975.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/magnetometer/ak8975.c
b/drivers/iio/magnetometer/ak8975.c
index 3c881541ae72..fd368
From: Ira Weiny
Changes from V4:
Fix up DAX mutual exclusion with other flags.
Add clean up patch (remove jflags)
Changes from V3:
Change EXT4_DAX_FL to bit24
Cache device DAX support in the super block and use that is
ext4_should_use_dax()
Change
From: Ira Weiny
S_DAX should only be enabled when the underlying block device supports
dax.
Cache the underlying support for DAX in the super block and modify
ext4_should_use_dax() to check for device support prior to the over
riding mount option.
While we are at it change the function to ext4_
On Thu, May 28, 2020 at 3:49 PM Qian Cai wrote:
>
> On Tue, May 12, 2020 at 05:33:20PM +0200, 'Andrey Konovalov' via kasan-dev
> wrote:
> > The kasan_report() functions belongs to report.c, as it's a common
> > functions that does error reporting.
> >
> > Reported-by: Leon Romanovsky
> > Signed-
According to AK09911 datasheet, if reset gpio is provided then
deassert reset on ak8975_power_on() and assert reset on ak8975_power_off().
Without reset's deassertion during ak8975_power_on(), driver's probe fails
on ak8975_who_i_am() while checking for device identity for AK09911 chip.
AK09911 h
From: Ira Weiny
The jflag variable serves almost no purpose. Remove it.
Signed-off-by: Ira Weiny
---
Changes from V4:
New for this series.
---
fs/ext4/ioctl.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/fs/ext4/ioctl.c b/fs/ext4/ioctl.c
index 7ccf2
From: Ira Weiny
In prep for the new tri-state mount option which then introduces
EXT4_MOUNT_DAX_NEVER.
Reviewed-by: Jan Kara
Signed-off-by: Ira Weiny
---
Changes:
New patch
---
fs/ext4/ext4.h | 4 ++--
fs/ext4/inode.c | 2 +-
fs/ext4/super.c | 12 ++--
3 files changed, 9 i
> I'm also confused why they have been debating about the changelog
> after the patch was queued.
I suggest to take another look at the provided patch review comments.
> My statement was about "the patch is a correct cleanup,
> but the changelog is totally misleading".
The commit message was ac
> I'm also confused why they have been debating about the changelog
> after the patch was queued.
I suggest to take another look at the provided patch review comments.
> My statement was about "the patch is a correct cleanup,
> but the changelog is totally misleading".
The commit message was ac
On Wed, 13 May 2020 15:48:11 -0300, Rodrigo Alencar wrote:
> From: Rodrigo Rolim Mendes de Alencar
>
> This patch provides support for displays like VGM128064B0W10,
> which requires a column offset of 2, i.e., its segments starts
> in SEG2 and ends in SEG129.
>
> Signed-off-by: Rodrigo Alencar <
On Fri 22-05-20 02:23:09, Naresh Kamboju wrote:
> My apology !
> As per the test results history this problem started happening from
> Bad : next-20200430 (still reproducible on next-20200519)
> Good : next-20200429
>
> The git tree / tag used for testing is from linux next-20200430 tag and
> rev
Hi Rob,
On 28/5/2020 10:06 pm, Rob Herring wrote:
On Thu, 28 May 2020 13:12:10 +0800, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Muruga
On Thu, 2020-05-28 at 07:56 -0700, Bart Van Assche wrote:
> > - buff_len = max_t(size_t, hba->desc_size.dev_desc,
> > - QUERY_DESC_MAX_SIZE + 1);
> > + buff_len = QUERY_DESC_MAX_SIZE + 1;
> >desc_buf = kmalloc(buff_len, GFP_KERNEL);
> >if (!desc_buf) {
>
On 2020-05-28 04:56, Bean Huo wrote:
> At UFS initialization stage, to get the length of the descriptor,
> ufshcd_read_desc_length() being called 6 times. This patch is to
> delete unnecessary reduntant code, remove ufshcd_read_desc_length()
> and boost UFS initialization.
As explained in Document
From: Colin Ian King
The pointer raq is being assigned twice. Fix this by removing
one of the redundant assignments.
Fixes: 14ba87304bf9 ("RDMA/hns: Remove redundant type cast for general
pointers")
Addressses-Coverity: ("Evaluation order violation")
Signed-off-by: Colin Ian King
---
drivers/
The following changes since commit 8ba6fa665c52093ddc0d81137fc3c82cee2c5ef8:
Merge tag 'iwlwifi-fw-2020-05-19' of
git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/linux-firmware
(2020-05-19 07:28:12 -0400)
are available in the Git repository at:
https://github.com/PLVision/linux-firmw
On 05/28/2020 07:27 AM, Luis Chamberlain wrote:
On Wed, May 27, 2020 at 02:36:42PM -0700, Jakub Kicinski wrote:
On Wed, 27 May 2020 03:19:18 + Luis Chamberlain wrote:
I read your patch, and granted, I will accept I was under the incorrect
assumption that this can only be used by networki
On Thu, May 28, 2020 at 04:49:06PM +0200, Bartosz Golaszewski wrote:
> czw., 28 maj 2020 o 16:45 Mark Brown napisał(a):
> > The tenery here is redundant, it's converting a boolean value into a
> > boolean value. Otherwise this looks good.
> Do you mind if I respin it right away? I don't want to
On 5/28/20 2:23 PM, Michael Ellerman wrote:
Petr Mladek writes:
On Thu 2020-05-28 11:03:43, Michael Ellerman wrote:
Petr Mladek writes:
The commit 0ebeea8ca8a4d1d453a ("bpf: Restrict bpf_probe_read{, str}() only
to archs where they work") caused that bpf_probe_read{, str}() functions
were no
Marvell Prestera 98DX326x integrates up to 24 ports of 1GbE with 8
ports of 10GbE uplinks or 2 ports of 40Gbps stacking for a largely
wireless SMB deployment.
Prestera Switchdev is a firmware based driver that operates via PCI bus. The
current implementation supports only boards designed for the
On Thu, May 28, 2020 at 05:28:02PM +0300, Serge Semin wrote:
> In order to keep track of Baikal-T1 SoC power consumption and make sure
> the chip heating is within the normal temperature limits, there is
> a dedicated hardware monitor sensor embedded into the SoC. It is based
> on the Analog Bits P
ut here ]
> [ 3160.307184][T106365] memory commitment underflow
> [ 3160.307216][T106365] WARNING: CPU: 103 PID: 106365 at mm/util.c:858
> __vm_enough_memory+0x204/0x250
> [ 3160.307275][T106365] Modules linked in: brd ext4 crc16 mbcache jbd2 loop
> kvm_hv kvm ip_tabl
On Thu, May 28, 2020 at 5:59 PM Michael Walle wrote:
>
> This series is a split off of the sl28cpld series:
> https://lore.kernel.org/linux-gpio/20200423174543.17161-1-mich...@walle.cc/
>
> I wasn't sure if I should also include the gpiochip_irqchip_add_domain()
> patch here. So feel free to skip
Marvell Prestera 98DX326x integrates up to 24 ports of 1GbE with 8
ports of 10GbE uplinks or 2 ports of 40Gbps stacking for a largely
wireless SMB deployment.
Prestera Switchdev is a firmware based driver that operates via PCI bus. The
current implementation supports only boards designed for the
Add PCI interface driver for Prestera Switch ASICs family devices, which
provides:
- Firmware loading mechanism
- Requests & events handling to/from the firmware
- Access to the firmware on the bus level
The firmware has to be loaded each time device is reset. The driver is
loading it
The ethtool API provides support for the configuration of the following
features: speed and duplex, auto-negotiation, MDI-x, forward error
correction, port media type. The API also provides information about the
port status, hardware and software statistic. The following limitation
exists:
- p
Add very basic support for devlink interface:
- driver name
- fw version
- devlink ports
Signed-off-by: Vadym Kochan
---
drivers/net/ethernet/marvell/prestera/Kconfig | 1 +
.../net/ethernet/marvell/prestera/Makefile| 2 +-
.../net/ethernet/marvell/prestera/prestera.h | 4
The following features are supported:
- VLAN-aware bridge offloading
- VLAN-unaware bridge offloading
- FDB offloading (learning, ageing)
- Switchport configuration
Currently there are some limitations like:
- Only 1 VLAN-aware bridge instance supported
- FDB ageing timeo
Clear tuning_done flag while executing tuning to ensure vendor
specific HS400 settings are applied properly when the controller
is re-initialized in HS400 mode.
Without this, re-initialization of the qcom SDHC in HS400 mode fails
while resuming the driver from runtime-suspend or system-suspend.
F
Add brief description how to configure base mac address binding in
device-tree.
Describe requirement for the PCI port which is connected to the ASIC, to
allow access to the firmware related registers.
Signed-off-by: Vadym Kochan
---
.../bindings/net/marvell,prestera.txt | 34 +++
Marvell Prestera 98DX326x integrates up to 24 ports of 1GbE with 8
ports of 10GbE uplinks or 2 ports of 40Gbps stacking for a largely
wireless SMB deployment.
The current implementation supports only boards designed for the Marvell
Switchdev solution and requires special firmware.
The core Preste
On Thu, 14 May 2020 16:24:19 +0530, Sharat Masetty wrote:
> Update documentation to list the gpu opp table bindings including the
> newly added "opp-peak-kBps" needed for GPU-DDR bandwidth scaling.
>
> Signed-off-by: Sharat Masetty
> ---
> .../devicetree/bindings/display/msm/gpu.txt| 28
On Thu, May 28, 2020 at 05:07:31PM +0800, Baoquan He wrote:
> On 05/26/20 at 01:49pm, David Hildenbrand wrote:
> > On 26.05.20 13:32, Mike Rapoport wrote:
> > > Hello Baoquan,
> > >
> > > On Tue, May 26, 2020 at 04:45:43PM +0800, Baoquan He wrote:
> > >> On 05/22/20 at 05:20pm, Mike Rapoport wrote
This verifies we're correctly notified when a seccomp filter becomes
unused when a notifier is in use.
Signed-off-by: Christian Brauner
---
/* v2 */
unchanged
---
tools/testing/selftests/seccomp/seccomp_bpf.c | 136 ++
1 file changed, 136 insertions(+)
diff --git a/tools/testing
On Thu, 14 May 2020 13:30:02 +0200, Geert Uytterhoeven wrote:
> Convert the Hitachi HD44780 Character LCD Controller Device Tree binding
> documentation to json-schema.
>
> Signed-off-by: Geert Uytterhoeven
> ---
> .../bindings/auxdisplay/hit,hd44780.txt | 45 -
> .../bindings/auxd
We've been making heavy use of the seccomp notifier to intercept and
handle certain syscalls for containers. This patch allows a syscall
supervisor listening on a given notifier to be notified when a seccomp
filter has become unused.
A container is often managed by a singleton supervisor process t
On 2020/05/28 20:06, Petr Mladek wrote:
> Now, it requires lib/Kconfig.twist that is added by a patch in
> Andrew's tree. One approach is to push this into linux-next
> via Andrew's -mm tree.
>
> Another possibility would be to remove lib/Kconfig.twist
> changes from this patch and replace
> CONFI
On Thu, May 28, 2020 at 05:00:54PM +0200, 'Andrey Konovalov' via kasan-dev
wrote:
> On Thu, May 28, 2020 at 3:49 PM Qian Cai wrote:
> >
> > On Tue, May 12, 2020 at 05:33:20PM +0200, 'Andrey Konovalov' via kasan-dev
> > wrote:
> > > The kasan_report() functions belongs to report.c, as it's a comm
On Thu, 28 May 2020 at 04:12, Sedat Dilek wrote:
>
[...]
> > > >
> > > > In general, CONFIG_KCSAN=y and the defaults for the other KCSAN
> > > > options should be good. Depending on the size of your system, you
> > > > could also tweak KCSAN runtime performance:
> > > > https://lwn.net/Articles/8
On 28/05/2020 15:53, Bart Van Assche wrote:
> On 2020-05-28 03:20, Chuhong Yuan wrote:
>> sbp_fetch_command() forgets to call kfree() in an error path.
>> Add the missed call to fix it.
>
> Hi Chris,
>
> The changelog of the code under drivers/target/sbp makes we wonder
> whether this driver has
On Thu, May 28, 2020 at 07:03:17PM +0800, Zijun Hu wrote:
> Controller ID info got by VSC EDL_PATCH_GETVER is very
> important, so improve its log level from DEBUG to INFO.
>
> Signed-off-by: Zijun Hu
Please add the tags from earlier version unless the new patch has
substantial changes.
Reviewe
On Thu, 14 May 2020 19:41:10 +0800, Anson Huang wrote:
> Convert the mxs pwm binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang
> ---
> Documentation/devicetree/bindings/pwm/mxs-pwm.txt | 17 -
> Documentation/devicetree/bindings/pwm/mxs-pwm.yaml | 43
> +
On Thu, 14 May 2020 21:03:20 +0900, Kunihiko Hayashi wrote:
> Add DT bindings for PCIe controller implemented in UniPhier SoCs
> when configured in endpoint mode. This controller is based on
> the DesignWare PCIe core.
>
> Signed-off-by: Kunihiko Hayashi
> ---
> .../bindings/pci/socionext,uniphi
kvm_x86_ops.cpuid_update() is used to update vmx/svm settings based on
updated CPUID settings. So it's supposed to be called after CPUIDs are
fully updated, not in the middle stage.
Signed-off-by: Xiaoyao Li
---
arch/x86/kvm/cpuid.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-
On Thu, May 28, 2020 at 05:42:57PM +0300, Andy Shevchenko wrote:
> On Wed, May 27, 2020 at 01:50:16AM +0300, Serge Semin wrote:
> > There are DMA devices (like ours version of Synopsys DW DMAC) which have
> > DMA capabilities non-uniformly redistributed amongst the device channels.
> > In order to
From: Kan Liang
Perf cannot validate an address before the actual access to MMIO space
of some uncore units, e.g. IMC on TGL. Accessing an invalid address,
which exceeds mapped area, can trigger oops.
Perf never records the size of mapped area. Generic functions, e.g.
uncore_mmio_read_counter(),
From: Kan Liang
When counting IMC uncore events on some TGL machines, an oops will be
triggered.
[ 393.101262] BUG: unable to handle page fault for address:
b45200e15858
[ 393.101269] #PF: supervisor read access in kernel mode
[ 393.101271] #PF: error_code(0x) - not-present page
From: Kan Liang
An oops will be triggered, if perf tries to access an invalid address
which exceeds the mapped area.
Check the address before the actual access to MMIO sapce of an uncore
unit.
Suggested-by: David Laight
Signed-off-by: Kan Liang
---
Changes since V2:
- Rename is_valid_mmio_of
>If it's true, then there could be 2 solutions, one is to skip the WARN_ONCE as
>it has no practical value, as the real >check is the following code, the other
>is to rectify the percpu counter when the policy is changing to
>>OVERCOMMIT_NEVER.
I think it's better to fix it up when the polic
On Thu, May 28, 2020 at 09:59:00AM +0200, Marco Elver wrote:
>
> Ouch. The below should be all we need, assuming it's the best we can do
> for sparse right now.
Upstream sparse should be OK with it now.
-- Luc
On 28/05/20 17:19, Xiaoyao Li wrote:
> kvm_x86_ops.cpuid_update() is used to update vmx/svm settings based on
> updated CPUID settings. So it's supposed to be called after CPUIDs are
> fully updated, not in the middle stage.
>
> Signed-off-by: Xiaoyao Li
Are you seeing anything bad happening fro
Hello Richard,
Quoting Richard Cochran (2020-05-28 16:34:40)
> On Wed, May 27, 2020 at 06:41:56PM +0200, Antoine Tenart wrote:
>
> > +static struct vsc85xx_ptphdr *get_ptp_header(struct sk_buff *skb)
> > +{
> > + struct ethhdr *ethhdr = eth_hdr(skb);
> > + struct iphdr *iphdr = ip_hdr(skb
On Thu, May 28, 2020 at 5:15 PM Qian Cai wrote:
>
> On Thu, May 28, 2020 at 05:00:54PM +0200, 'Andrey Konovalov' via kasan-dev
> wrote:
> > On Thu, May 28, 2020 at 3:49 PM Qian Cai wrote:
> > >
> > > On Tue, May 12, 2020 at 05:33:20PM +0200, 'Andrey Konovalov' via
> > > kasan-dev wrote:
> > > >
>> Still, the kfree(NULL) is harmless. But it is cleaner
>> to have the patch. But the changelog is wrong, even after
>> the lengthened debating, and English is not my mother tongue,
>> so I just looked on.
>
> We have tried to tell Markus not to advise people about commit messages
A few concerns
On Thu, May 28, 2020 at 05:53:03PM +0300, Andy Shevchenko wrote:
> On Wed, May 27, 2020 at 01:50:19AM +0300, Serge Semin wrote:
> > Since some DW DMA controllers (like one installed on Baikal-T1 SoC) may
> > have non-uniform DMA capabilities per device channels, let's add
> > the DW DMA specific de
Some SPI host controllers do not support full-duplex SPI and are
marked as such via the SPI_CONTROLLER_HALF_DUPLEX controller flag.
For such controllers use half duplex transactions but retain full
duplex transactions for the controllers that can handle those.
Signed-off-by: Tim Harvey
---
driv
v5:
- Add some range checks in dt-schema
Jiaxun Yang (6):
irqchip: Add Loongson HyperTransport Vector support
dt-bindings: interrupt-controller: Add Loongson HTVEC
irqchip: Add Loongson PCH PIC controller
dt-bindings: interrupt-controller: Add Loongson PCH PIC
irqchip: Add Loongson PCH
This controller appears on Loongson-3 chips for receiving interrupt
vectors from PCH's PIC and PCH's PCIe MSI interrupts.
Signed-off-by: Jiaxun Yang
---
v2:
- Style cleanup
- Set ack callback and set correct edge_irq handler
v3:
- Correct bitops in ACK callback
v4:
Add binding for Loongson-3 HyperTransport Interrupt Vector Controller.
Signed-off-by: Jiaxun Yang
--
v4: Drop ref, '|', add additionalProperties, fix example
---
.../interrupt-controller/loongson,htvec.yaml | 57 +++
1 file changed, 57 insertions(+)
create mode 100644
Document
This controller appears on Loongson LS7A family of PCH to transform
interrupts from devices into HyperTransport vectorized interrrupts
and send them to procrssor's HT vector controller.
Signed-off-by: Jiaxun Yang
---
v2:
- Style clean-ups
- Use IRQ_FASTEOI_HIERARCHY_HANDLERS
Add binding for Loongson PCH MSI controller.
Signed-off-by: Jiaxun Yang
Reviewed-by: Rob Herring
--
v5: Add range check for msi-base-vec & msi-num-vecs
---
.../loongson,pch-msi.yaml | 62 +++
1 file changed, 62 insertions(+)
create mode 100644
Documentation
Add binding for Loongson PCH PIC Controller.
Signed-off-by: Jiaxun Yang
--
v2:
- Fix naming
- Mark loongson,pic-base-vec as required
v5:
- Add range check for loongson,pic-base-vec
---
.../loongson,pch-pic.yaml | 56 +++
1 file changed,
This controller appears on Loongson LS7A family of PCH to transform
interrupts from PCI MSI into HyperTransport vectorized interrrupts
and send them to procrssor's HT vector controller.
Signed-off-by: Jiaxun Yang
--
v2:
- Style clean-ups
- Add ack callback
- Use bitmap_fin
On Thu, 28 May 2020 at 17:22, Luc Van Oostenryck
wrote:
>
> On Thu, May 28, 2020 at 09:59:00AM +0200, Marco Elver wrote:
> >
> > Ouch. The below should be all we need, assuming it's the best we can do
> > for sparse right now.
>
> Upstream sparse should be OK with it now.
Very good, thank you! Fo
Hi Paul,
On Thu, May 28, 2020 at 3:51 PM Paul E. McKenney wrote:
> On Thu, May 28, 2020 at 09:04:38AM +0200, Geert Uytterhoeven wrote:
> > On Thu, May 28, 2020 at 5:26 AM kbuild test robot wrote:
> > > tree:
> > > https://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git
> > > de
Hi Lorenzo,
On Thu, May 28, 2020 at 4:21 PM Lorenzo Pieralisi
wrote:
> On Sun, May 24, 2020 at 10:37:49PM +0100, Lad Prabhakar wrote:
> > This patch series adds support for HSUSB, USB2.0 and USB3.0 to
> > R8A7742 SoC DT.
> >
> > This patch series applies on-top of [1].
> >
> > [1]
> > https://pa
On 5/28/20 8:31 AM, Geert Uytterhoeven wrote:
> Hi Paul,
>
> On Thu, May 28, 2020 at 3:51 PM Paul E. McKenney wrote:
>> On Thu, May 28, 2020 at 09:04:38AM +0200, Geert Uytterhoeven wrote:
>>> On Thu, May 28, 2020 at 5:26 AM kbuild test robot wrote:
tree:
https://git.kernel.org/pub/s
On 5/27/20 8:44 AM, js1...@gmail.com wrote:
> From: Joonsoo Kim
>
> For locality, it's better to migrate the page to the same node
> rather than the node of the current caller's cpu.
Should be, yeah.
> Acked-by: Roman Gushchin
> Signed-off-by: Joonsoo Kim
Reviewed-by: Vlastimil Babka
> ---
Hi Roberto,
it seems that the recent changes in IMA in linux-next caused a
regression: namely it triggers an Oops when booting with the options
ima_policy=tcb ima_template_fmt='d-ng|n-ng|d|ng'
It hits a NULL dereference at ima_match_policy() like:
[ 10.766220]
==
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8 supported. Data register used to support the
From: Ramuthevar Vadivel Murugan
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8 supported.
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
.../devicetree/bindings/mtd/intel,lgm-nand.yaml| 93 ++
1 file changed, 93 insertions(+)
cr
On Tue, May 26, 2020 at 09:42:19AM +, Ugur Usug wrote:
> This change has 2 parts:
> 1. Add support for max20710 into the existing max20730 driver.
>
> 2. Add debugfs interface support for accessing device specific registers
> (MFR_VOUT_MIN, MFR_DEVSET1 and MFR_DEVSET2) and others
> including
On Thu, May 28, 2020 at 04:55:19PM +1000, Herbert Xu wrote:
> On Wed, May 20, 2020 at 12:45:56PM -0400, st...@rowland.harvard.edu wrote:
> > On Wed, May 20, 2020 at 03:42:17PM +, Sverdlin, Alexander (Nokia -
> > DE/Ulm) wrote:
> > > Hello Dinghao,
> > >
> > > On Wed, 2020-05-20 at 21:29 +0800
Tested-by: Jami Kettunen
On 28.5.2020 17.22, Jeffrey Hugo wrote:
ufs_unipro_core_clk_src is required to allow UFS to clock scale for power
savings.
Fixes: b5f5f525c547 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver")
Signed-off-by: Jeffrey Hugo
---
drivers/clk/qcom/gcc-msm8998.c
On Thu, May 28, 2020 at 05:52:24PM +0300, Andy Shevchenko wrote:
> On Wed, May 27, 2020 at 01:50:20AM +0300, Serge Semin wrote:
> > IP core of the DW DMA controller may be synthesized with different
> > max burst length of the transfers per each channel. According to Synopsis
> > having the fixed m
On 5/28/2020 11:22 PM, Paolo Bonzini wrote:
On 28/05/20 17:19, Xiaoyao Li wrote:
kvm_x86_ops.cpuid_update() is used to update vmx/svm settings based on
updated CPUID settings. So it's supposed to be called after CPUIDs are
fully updated, not in the middle stage.
Signed-off-by: Xiaoyao Li
Are
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
.../devicetree/bindings/mtd/intel,lgm-nand.yaml| 93 ++
1 file changed, 93 insertions(+)
cr
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8 supported. Data register used to support the
From: Ramuthevar Vadivel Murugan
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8 supported.
Recomputing the uids, gids, capabilities, and related flags each time a
new bprm->file is set is error prone, and as it turns out unnecessary.
Further our decisions on when to clear personality bits and when to tell
userspace privileges have been gained so please be extra careful, is
imperfect a
On 5/28/2020 2:05 PM, Andrei Botila (OSS) wrote:
> @@ -4698,6 +4698,9 @@ static void dpaa2_dpseci_free(struct dpaa2_caam_priv
> *priv)
> struct device *dev = priv->dev;
> struct fsl_mc_device *ls_dev = to_fsl_mc_device(dev);
>
> + if (DPSECI_VER(priv->major_ver, priv->minor_ver)
On Thu, May 14, 2020 at 09:04:36AM -0700, Randy Dunlap wrote:
> On 5/14/20 4:07 AM, Stephen Rothwell wrote:
> > Hi all,
> >
> > Changes since 20200512:
> >
>
> on x86_64:
>
> drivers/ide/ide-tape.o: warning: objtool:
> ide_tape_discard_merge_buffer.constprop.7()+0x4e: unreachable instruction
>
On Thu, May 28, 2020 at 01:04:25PM +0800, Zijun Hu wrote:
>
>
> On 5/28/2020 12:48 AM, Matthias Kaehlcke wrote:
> > Hi Zijun,
> >
> > On Wed, May 27, 2020 at 10:32:39AM +0800, Zijun Hu wrote:
> >> Warm reboot can not restore qca6390 controller baudrate
> >> to default due to lack of controllable
From: Bartosz Golaszewski
In many instances regmap_update_bits() is used for simple bit setting
and clearing. In these cases the last argument is redundant and we can
hide it with a static inline function.
This adds three new helpers for simple bit operations: set_bits,
clear_bits and test_bits
Dear Linux folks,
On most (if not all) AMD Ryzen systems, including the Dell OptiPlex
5055, [1][2], Linux prints the warning below:
$ dmesg --level=warn
[0.871377] pci :00:00.2: can't derive routing for PCI INT A
[0.871732] pci :00:00.2: PCI INT A: not connected
From: Bartosz Golaszewski
Shrink the code visually by replacing regmap_update_bits() with
appropriate regmap bit operations where applicable.
Signed-off-by: Bartosz Golaszewski
---
drivers/net/ethernet/mediatek/mtk_star_emac.c | 80 ---
1 file changed, 35 insertions(+), 45 dele
From: Bartosz Golaszewski
I noticed that oftentimes I use regmap_update_bits() for simple bit
setting or clearing. In this case the fourth argument is superfluous as
it's always 0 or equal to the mask argument.
This series proposes to add simple bit operations for setting, clearing
and testing s
The bprm->per_clear field only takes the values 0 and
PER_CLEAR_ON_SETID. Reduce the field to a signle bit to make it clear
that the only question is should the dangerous personality bits be
cleared or not.
Update the documentation of the security lsm hooks.
Signed-off-by: "Eric W. Biederman"
When the credentials have been recomputed per file the per_clear
status has not been recomputed. Update the per file calcuations to
recompute per_clear on a per file basis in a separate variable and to
combine that variable into the final per_clear value.
This makes which personality bits are c
Move the computation of creds from prepare_binfmt into begin_new_exec
so that the creds can be computed only onc.
I have looked through the kernel and verified none of the binfmts
look at bprm->cred directly so computing the bprm->cred later
should be safe.
Rename preserve_creds to execfd_creds
From: Nisha Kumari
Adding the devicetree binding for labibb regulator.
Signed-off-by: Nisha Kumari
Signed-off-by: Sumit Semwal
--
v2: updated for better compatible string and names.
v3: moved to yaml
---
.../regulator/qcom-labibb-regulator.yaml | 63 +++
1 file changed,
The OcteonTX (TX1/ThunderX) SPI controller does not support full
duplex transactions. Set the appropriate flag such that the spi
core will return -EINVAL on such transactions requested by chip
drivers.
This is an RFC as I need someone from Marvell/Cavium to confirm
if this driver is used for other
This series adds a driver for LAB/IBB regulators found on some Qualcomm SoCs.
These regulators provide positive and/or negative boost power supplies
for LCD/LED display panels connected to the SoC.
This series adds the support for pmi8998 PMIC found in SDM845 family of SoCs.
Changes from v2:
- Re
Some regulators might need to verify that they have indeed been enabled
after the enable() call is made and enable_time delay has passed.
This is implemented by repeatedly checking is_enabled() upto
poll_enabled_time, waiting for the already calculated enable delay in
each iteration.
Signed-off-b
The logic in cap_bprm_creds_from_file is difficult to follow in part
because it handles both uids/gids and capabilities. That difficulty
in following the code has resulted in several small bugs. Move the
handling of uids/gids into bprm_fill_uid to make the code clearer.
A small bug is fixed wh
On Thu 28-05-20 23:10:20, Feng Tang wrote:
[...]
> If it's true, then there could be 2 solutions, one is to
> skip the WARN_ONCE as it has no practical value, as the real
> check is the following code, the other is to rectify the
> percpu counter when the policy is changing to OVERCOMMIT_NEVER.
I
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