On Tue, May 05, 2020 at 04:09:16PM +0100, Will Deacon wrote:
> On Tue, May 05, 2020 at 03:15:29PM +0100, Daniel Thompson wrote:
> > On Mon, May 04, 2020 at 09:48:04PM +0100, Will Deacon wrote:
> > > On Mon, May 04, 2020 at 06:05:18PM +0100, Daniel Thompson wrote:
> > > > diff --git a/arch/arm64/inc
> > Hi Oleksij
> >
> > reg is normally 0 to 31, since that is the address range for MDIO.
> > Did you use 14 here because of what strapping allows?
>
> Yes. Only BITs 1:3 are configurable. BIT(0) is always 0 for the PHY0 and 1
> for the PHY1
O.K. good.
> > > +required:
> > > + - compatible
>
On 06/05/2020 14:37, Juri Lelli wrote:
> On 06/05/20 12:54, Dietmar Eggemann wrote:
>> On 27/04/2020 10:37, Dietmar Eggemann wrote:
[...]
>> There is an issue w/ excl. cpusets and cpuset.sched_load_balance=0. The
>> latter is needed to demonstrate the problem since DL task affinity can't
>> be al
Hi Vishal,
Thank you for the patch.
There are a few questions for Hans below.
On Wed, Apr 29, 2020 at 07:47:04PM +0530, Vishal Sagar wrote:
> The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native SDI
> streams from SDI sources like SDI broadcast equipment like cameras and
> mixers. T
> There is a spurious 'put_device()' in the remove function.
Do you find differences in the clean-up of system resources suspicious
between the implementations of the functions “puv3_i2c_remove” and
“puv3_i2c_probe”?
Regards,
Markus
TI's J721E SoC uses Cadence PCIe core to implement both RC mode
and EP mode.
The high level features are:
*) Supports Legacy, MSI and MSI-X interrupt
*) Supports upto GEN4 speed mode
*) Supports SR-IOV
*) Supports multiple physical function
*) Ability to route all transactions via SMMU
Add a macro for aligning down a pointer. This is useful to get an
aligned register address when a device allows only word access and
doesn't allow half word or byte access.
Signed-off-by: Kishon Vijay Abraham I
---
include/linux/kernel.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/includ
commit bd22885aa188 ("PCI: cadence: Refactor driver to use as a core
library") while refactoring the Cadence PCIe driver to be used as
library, removed pm_runtime_get_sync() from cdns_pcie_ep_setup()
and cdns_pcie_host_setup() but missed to remove the corresponding
pm_runtime_put_sync() in the erro
Certain platforms like TI's J721E allow only 32-bit register accesses.
Add read and write accessors to perform only 32-bit accesses in order to
support platforms like TI's J721E.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pcie-cadence.c | 40 +++
dri
On Wed, 2020-05-06 at 16:51 +0300, Luciano Coelho wrote:
> On Tue, 2020-05-05 at 20:19 -0700, Joe Perches wrote:
> > On Wed, 2020-05-06 at 11:07 +0800, Samuel Zou wrote:
> > > This silences the following coccinelle warning:
> > >
> > > "WARNING: sum of probable bitmasks, consider |"
> >
> > I sug
Add cdns_pcie_ops to start link and verify link status. The registers
to start link and to check link status is in Platform specific PCIe
wrapper. Add support for platform specific drivers to add callback
functions for the PCIe Cadence core to start link and verify link status.
Signed-off-by: Kish
From: Alan Douglas
Implement ->set_msix() and ->get_msix() callback functions in order
to configure MSIX capability in the PCIe endpoint controller.
Add cdns_pcie_ep_send_msix_irq() to send MSIX interrupts to Host.
cdns_pcie_ep_send_msix_irq() gets the MSIX table address (virtual
address) from "
Add support to use custom read and write accessors. Platforms that
don't support half word or byte access or any other constraint
while accessing registers can use this feature to populate custom
read and write accessors. These custom accessors are used for both
standard register access and configu
Certain platforms like TI's J721E allows only 32-bit configuration
space access. In such cases pci_generic_config_read and
pci_generic_config_write cannot be used. Add support in Cadence core
to let pci_host_bridge have custom pci_ops.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/contro
Add host mode dt-bindings for TI's J721E SoC.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../bindings/pci/ti,j721e-pci-host.yaml | 113 ++
1 file changed, 113 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.
Add support for PCIe controller in J721E SoC. The controller uses the
Cadence PCIe core programmed by pcie-cadence*.c. The PCIe controller
will work in both host mode and device mode.
Some of the features of the controller are:
*) Supports both RC mode and EP mode
*) Supports MSI and MSI-X supp
Add J721E in pci_device_id table so that pci-epf-test can be used
for testing PCIe EP in J721E.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_tes
Cadence driver uses "mem" memory resource to obtain the offset of
configuration space address region, memory space address region and
message space address region. The obtained offset is used to program
the Address Translation Unit (ATU). However certain platforms like TI's
J721E SoC require the ab
On Sat, May 02, 2020 at 12:09:13PM +0200, Takashi Iwai wrote:
> On Sat, 02 May 2020 09:27:31 +0200,
> Takashi Iwai wrote:
> >
> > On Sat, 02 May 2020 09:17:28 +0200,
> > Lukas Wunner wrote:
> > >
> > > On Sat, May 02, 2020 at 09:11:58AM +0200, Takashi Iwai wrote:
> > > > --- a/drivers/gpu/drm/amd
Commit 1b79c5284439 ("PCI: cadence: Add host driver for Cadence PCIe
controller") in order to update Vendor ID, directly wrote to
PCI_VENDOR_ID register. However PCI_VENDOR_ID in root port configuration
space is read-only register and writing to it will have no effect.
Use local management register
Add PCIe EP mode dt-bindings for TI's J721E SoC.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../bindings/pci/ti,j721e-pci-ep.yaml | 89 +++
1 file changed, 89 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.
Add Kishon Vijay Abraham I as MAINTAINER for TI J721E SoC PCIe.
Signed-off-by: Kishon Vijay Abraham I
---
MAINTAINERS | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2926327e4976..9d40e1318f7c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1
On 5/5/20 3:16 PM, Thomas Gleixner wrote:
From: Thomas Gleixner
While working on the entry consolidation I stumbled over the KVM async page
fault handler and kvm_async_pf_task_wait() in particular. It took me a
while to realize that the randomly sprinkled around rcu_irq_enter()/exit()
invoca
On Tue, 5 May 2020 14:31:44 +0200
Joerg Roedel wrote:
> On Mon, May 04, 2020 at 03:10:06PM -0400, Steven Rostedt wrote:
> > I'm fine with adding it to the tracing code (with that ridiculous
> > comment! ;-)
> >
> > I'll even tag is as stable, but again, it's uncertain what commit that it
> > "fi
Hi,
I updated my old Sony Vaio a few days ago and discovered that a few Fn-keys on
my old Sony Vaio had stopped working.
The bisection points at the commit in the subject and reverting it makes
everything work again even with current
Linus' git.
Full bug report below. Please CC: me as I'm not
Vivek Goyal writes:
> On Wed, Apr 29, 2020 at 11:36:29AM +0200, Vitaly Kuznetsov wrote:
>> Commit 9a6e7c39810e (""KVM: async_pf: Fix #DF due to inject "Page not
>> Present" and "Page Ready" exceptions simultaneously") added a protection
>> against 'page ready' notification coming before 'page not
Hi Eizan,
Thank you for the patch.
On 6/5/20 7:49, Eizan Miyamoto wrote:
> These fields are not used and can be removed.
>
> Signed-off-by: ei...@chromium.org
You need to drop the above line, for this and the other patches.
> Reviewed-by: Enric Balletbo I Serra
> Signed-off-by: Eizan Miyamoto
On Wed, 6 May 2020 07:41:51 -0700 "Paul E. McKenney" wrote:
> On Wed, May 06, 2020 at 02:59:26PM +0200, SeongJae Park wrote:
> > TL; DR: It was not kernel's fault, but the benchmark program.
> >
> > So, the problem is reproducible using the lebench[1] only. I carefully read
> > it's code again.
On 2020-05-05 16:12, Rob Herring wrote:
> On Mon, Apr 27, 2020 at 03:49:30PM +0300, amirmi...@gmail.com wrote:
>> From: Amir Mizinski
>>
>> Added a YAML schema to support tpm tis i2c related dt-bindings for the I2c
>> PTP based physical layer.
>>
>> This patch adds the documentation for correspo
On Wed, May 06, 2020 at 02:55:17PM +, Michael Kelley wrote:
[...]
> > Hv_pci_bus_exit() calls hv_send_resources_released() to release all child
> > resources.
> > These child resources were allocated in hv_send_resources_allocated().
> > Hv_send_resources_allocated() could fail in the middle
randconfig-b001-20200430
i386 randconfig-b002-20200430
x86_64 randconfig-b001-20200430
i386 randconfig-b003-20200430
x86_64 randconfig-b002-20200430
x86_64 randconfig-b003-20200430
i386 randconfig-b003-20200506
i386
The name "pstore_lock" sounds very global, but it is only supposed to be
used for managing changes to "psinfo", so rename it accordingly.
Signed-off-by: Kees Cook
---
fs/pstore/platform.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/fs/pstore/platform.c b/fs/pst
The pstorefs internal list lock doesn't need to be a spinlock and will
create problems when trying to access the list in the subsequent patch
that will walk the pstorefs records during pstore_unregister(). Change
this to a mutex to avoid may_sleep() warnings when unregistering devices.
Signed-off-
Hi,
This fixes a long-standing problem[1] with pstore where the filesystem
view of backend records was not updated when the backend was unloaded
(in a modular build) through pstore_unregister(). This series is
mostly refactoring and improvements to the various locking semantics
around management o
The pstore.update_ms value was being disabled during pstore_unregister(),
which would cause any prior value to go unnoticed on the next
pstore_register(). Instead, just let del_timer() stop the timer, which
was always sufficient. This additionally refactors the timer reset code
and allows the timer
On Wed, May 06, 2020 at 08:36:22PM +0530, Aishwarya Ramakrishnan wrote:
> From: Aishwarya Ramakrishnan
>
> On Tue, May 5, 2020 at 11:49 PM Greg Kroah-Hartman
> wrote:
> > On Tue, May 05, 2020 at 09:03:24PM +0530, Aishwarya Ramakrishnan wrote:
> >> It is more clear to use DEFINE_DEBUGFS_ATTRIBUT
On Wed, 6 May 2020 16:40:19 +0800
Po Liu wrote:
> } else if (matches(*argv, "base-time") == 0) {
> + NEXT_ARG();
> + if (get_u64(&base_time, *argv, 10)) {
> + invalidarg = "base-time";
> +
The pstore backend lock wasn't being used during pstore_unregister().
Add sanity check and locking.
Signed-off-by: Kees Cook
---
fs/pstore/platform.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/fs/pstore/platform.c b/fs/pstore/platform.c
index d0ce2223
Currently pstore can only have a single backend attached at a time, and it
tracks the active backend via "psinfo", under a lock. The locking for this
does not need to be a spinlock, and in order to avoid may_sleep() issues
during future changes to pstore_unregister(), switch to a mutex instead.
Si
The "unlink" handling should perform list removal (which can also make
sure records don't get double-erased), and the "evict" handling should
be responsible only for memory freeing.
Signed-off-by: Kees Cook
---
fs/pstore/inode.c | 19 +--
1 file changed, 13 insertions(+), 6 delet
If a backend was unloaded without having first removed all its
associated records in pstorefs, subsequent removals would crash while
attempting to call into the now missing backend. Add automatic removal
from the tree in pstore_unregister(), so that no references to the
backend remain.
Reported-by
The name "allpstore" doesn't carry much meaning, so rename it to what it
actually is: the list of all records present in the filesystem. The lock
is also renamed accordingly.
Signed-off-by: Kees Cook
---
fs/pstore/inode.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(
There is no reason to be doing a module get/put in pstore_register(),
since the module calling pstore_register() cannot be unloaded since it
hasn't finished its initialization. Remove it so there is no confusion
about how registration ordering works.
Signed-off-by: Kees Cook
---
fs/pstore/platfo
Nothing was protecting changes to the pstorefs superblock. Add locking
and refactor away is_pstore_mounted(), instead using a helper to add a
way to safely lock the pstorefs root inode during filesystem changes.
Signed-off-by: Kees Cook
---
fs/pstore/inode.c| 65 +
Hi Eizan,
Thank you for your patch.
Missatge de Eizan Miyamoto del dia dc., 6 de maig
2020 a les 7:51:
>
> This is a cleanup to better handle errors during MDP probe.
>
> Signed-off-by: ei...@chromium.org
As I commented on the first patch you should drop the above line.
> Signed-off-by: Eizan
From: Jin Yao
As the code comments in perf_stat_process_counter() say, we calculate
counter's data every interval, and the display code shows ps->res_stats
avg value. We need to zero the stats for interval mode.
But the current code only zeros the res_stats[0], it doesn't zero the
res_stats[1] a
From: Ian Rogers
By default this isn't run as it reads /proc and may not have access.
For consistency, modify the single threaded benchmark to compute an
average time per event.
Committer testing:
$ grep -m1 "model name" /proc/cpuinfo
model name: Intel(R) Core(TM) i7-8650U CPU @ 1.90GHz
From: Tommi Rantala
Commit 2d4f27999b88 ("perf data: Add global path holder") missed path
conversion in tests/topology.c, causing the "Session topology" testcase
to "hang" (waits forever for input from stdin) when doing "ssh $VM perf
test".
Can be reproduced by running "cat | perf test topo", an
From: Stephane Eranian
To control degree of parallelism of the synthesize_mmap() code which
is scanning /proc/PID/task/PID/maps and can be time consuming.
Mimic perf top way of handling the option.
If not specified will default to 1 thread, i.e. default behavior before
this option.
On a desktop
From: Jin Yao
For interval mode, the metric is printed after the '#' character if it
exists. But it's not calculated by the counts generated in this
interval.
See the following examples:
root@kbl-ppc:~# perf stat -M CPI -I1000 --interval-count 2
# time counts unit even
From: Ian Rogers
The synthesize benchmark, run on a single process and thread, shows
perf_event__synthesize_mmap_events as the hottest function with fgets
and sscanf taking the majority of execution time.
fscanf performs similarly well. Replace the scanf call with manual
reading of each field of
From: Ian Rogers
al->sym may be NULL given current if conditions and may cause a segv.
Fixes: d2bedb7863e9 ("perf script: Allow --symbol to accept hexadecimal
addresses")
Signed-off-by: Ian Rogers
Acked-by: Jiri Olsa
Cc: Alexander Shishkin
Cc: Mark Rutland
Cc: Namhyung Kim
Cc: Peter Zijlst
/scm/linux/kernel/git/acme/linux into perf/core
(2020-04-22 14:08:28 +0200)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git
tags/perf-core-for-mingo-5.8-20200506
for you to fetch changes up to 19ce2321739da5fc27f6a5ed1e1cb15e384ad030:
perf
From: Tommi Rantala
Do not bother with close() if fd is not valid, just to silence valgrind:
$ valgrind ./perf script
==59169== Memcheck, a memory error detector
==59169== Copyright (C) 2002-2017, and GNU GPL'd, by Julian Seward et al.
==59169== Using Valgrind-3.14.0 and LibVEX;
From: Ian Rogers
The synthesize benchmark shows the majority of execution time going to
fgets and sscanf, necessary to parse /proc/pid/maps. Add a new buffered
reading library that will be used to replace these calls in a follow-up
CL. Add tests for the library to perf test.
Committer tests:
From: Jagadeesh Pagadala
Code cleanup: Remove duplicate headers which are included twice.
Signed-off-by: Jagadeesh Pagadala
Cc: Andi Kleen
Cc: Jiri Olsa
Link:
http://lore.kernel.org/lkml/1587276836-17088-1-git-send-email-jagdsh.li...@gmail.com
Signed-off-by: Arnaldo Carvalho de Melo
---
to
From: Tommi Rantala
Fix div-by-zero if runtime is zero:
$ perf bench futex hash --runtime=0
# Running 'futex/hash' benchmark:
Run summary [PID 12090]: 4 threads, each operating on 1024 [private] futexes
for 0 secs.
Floating point exception (core dumped)
Signed-off-by: Tommi Rantala
Ac
From: Shaokun Zhang
get_cpuid_str() is used in tools/perf/arch/xxx/util/header.c,
fix the name in comment.
Signed-off-by: Shaokun Zhang
Cc: Andi Kleen
Link:
http://lore.kernel.org/lkml/1588141992-48382-1-git-send-email-zhangshao...@hisilicon.com
Signed-off-by: Arnaldo Carvalho de Melo
---
t
From: Kajol Jain
Patch enhances current metric infrastructure to handle "?" in the metric
expression. The "?" can be use for parameters whose value not known
while creating metric events and which can be replace later at runtime
to the proper value. It also add flexibility to create multiple even
From: Zou Wei
Fixes coccicheck warnings:
tools/perf/builtin-c2c.c:1712:2-3: Unneeded semicolon
tools/perf/builtin-c2c.c:1928:2-3: Unneeded semicolon
tools/perf/builtin-c2c.c:2962:2-3: Unneeded semicolon
Reported-by: Hulk Robot
Signed-off-by: Zou Wei
Cc: Alexander Shishkin
Cc: Jiri Olsa
C
From: Kajol Jain
Commit 54b5091606c18 ("perf stat: Implement --metric-only mode") added
function 'valid_only_metric()' which drops "Hz" or "hz", if it is part
of "ScaleUnit". This patch enable it since hv_24x7 supports couple of
frequency events.
Signed-off-by: Kajol Jain
Acked-by: Jiri Olsa
C
From: Zou Wei
Fixes coccicheck warning:
tools/lib/traceevent/kbuffer-parse.c:441:2-3: Unneeded semicolon
Reported-by: Hulk Robot
Signed-off-by: Zou Wei
Acked-by: Steven Rostedt (VMware)
Link:
http://lore.kernel.org/lkml/1588065121-71236-1-git-send-email-zou_...@huawei.com
Signed-off-by: Ar
From: Zou Wei
Fixes coccicheck warning:
tools/perf/builtin-report.c:1403:2-34: WARNING: Assignment of 0/1 to bool
variable
Reported-by: Hulk Robot
Signed-off-by: Zou Wei
Cc: Alexander Shishkin
Cc: Jiri Olsa
Cc: Mark Rutland
Cc: Namhyung Kim
Cc: Peter Zijlstra
Link:
http://lore.kernel
From: Stephane Eranian
When printing iregs, there was a double newline printed because
perf_sample__fprintf_regs() was printing its own and then at the end of
all fields, perf script was adding one. This was causing blank line in
the output:
Before:
$ perf script -Fip,iregs
401b
merged into cifs-2.6.git for-next
On Tue, May 5, 2020 at 8:49 AM Geert Uytterhoeven
wrote:
>
> As per POSIX, the correct spelling is EACCES:
>
> include/uapi/asm-generic/errno-base.h:#define EACCES 13 /* Permission denied
> */
>
> Fixes: b8f7442bc46e48fb ("CIFS: refactor cifs_get_inode_info()")
From: Kajol Jain
Added test case for parsing "?" in metric expression.
Signed-off-by: Kajol Jain
Acked-by: Jiri Olsa
Cc: Alexander Shishkin
Cc: Andi Kleen
Cc: Anju T Sudhakar
Cc: Benjamin Herrenschmidt
Cc: Greg Kroah-Hartman
Cc: Jin Yao
Cc: Joe Mario
Cc: Kan Liang
Cc: Madhavan Sriniva
From: Arnaldo Carvalho de Melo
Trying to disentangle this a bit further, unfortunately it uses
parse_events(), its interesting to have it separated anyway, so do it.
Cc: Adrian Hunter
Cc: Jiri Olsa
Cc: Namhyung Kim
Signed-off-by: Arnaldo Carvalho de Melo
---
tools/perf/arch/arm/util/cs-etm.
From: Arnaldo Carvalho de Melo
To avoid dragging more stuff into the perf python binding in the
following csets.
Reported-by: Jiri Olsa
Cc: Adrian Hunter
Cc: Namhyung Kim
Signed-off-by: Arnaldo Carvalho de Melo
---
tools/perf/util/Build | 1 +
tools/perf/util/evlist.c
From: Zou Wei
Fixes coccicheck warnings:
tools/perf/builtin-diff.c:1565:2-3: Unneeded semicolon
tools/perf/builtin-lock.c:778:2-3: Unneeded semicolon
tools/perf/builtin-mem.c:126:2-3: Unneeded semicolon
tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c:555:2-3: Unneeded
semicolon
From: Arnaldo Carvalho de Melo
Where state related to a 'perf top' session is grouped.
Acked-by: Jiri Olsa
Cc: Adrian Hunter
Cc: Namhyung Kim
Cc: Song Liu
Link: http://lore.kernel.org/lkml/20200429131106.27974-3-a...@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo
---
tools/perf/builtin
From: Kajol Jain
The hv_24×7 feature in IBM® POWER9™ processor-based servers provide the
facility to continuously collect large numbers of hardware performance
metrics efficiently and accurately.
This patch adds hv_24x7 metric file for different Socket/chip
resources.
Result:
power9 platform:
From: Arnaldo Carvalho de Melo
Renaming bpf_event__add_sb_event() to evlist__add_sb_event() and
requiring that the evlist be allocated beforehand.
This will allow using the same side band thread and evlist to be used
for multiple purposes in addition to react to PERF_RECORD_BPF_EVENT soon
after
From: Arnaldo Carvalho de Melo
I.e. so far we had just one event in that side band thread, a dummy one
with attr.bpf_event set, so that 'perf record' can go ahead and ask the
kernel for further information about BPF programs being loaded.
Allow for more than one event to be there, so that we can
From: Arnaldo Carvalho de Melo
Where state related to a 'perf record' session is grouped.
Acked-by: Jiri Olsa
Cc: Adrian Hunter
Cc: Namhyung Kim
Cc: Song Liu
Link: http://lore.kernel.org/lkml/20200429131106.27974-2-a...@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo
---
tools/perf/buil
From: Arnaldo Carvalho de Melo
It is quite big by now, move that code to a separate
record__setup_sb_evlist() routine.
Suggested-by: Jiri Olsa
Acked-by: Jiri Olsa
Cc: Adrian Hunter
Cc: Namhyung Kim
Cc: Song Liu
Link: http://lore.kernel.org/lkml/20200429131106.27974-9-a...@kernel.org
Signed-
From: Ian Rogers
Fix a memory leak found by applying LLVM's libfuzzer on parse_events().
Signed-off-by: Ian Rogers
Acked-by: Jiri Olsa
Cc: Adrian Hunter
Cc: Alexander Shishkin
Cc: Andi Kleen
Cc: Leo Yan
Cc: Mark Rutland
Cc: Namhyung Kim
Cc: Peter Zijlstra
Cc: Stephane Eranian
Cc: clang
From: Ian Rogers
Fix another memory leak found by applying LLVM's libfuzzer on parse_events().
Signed-off-by: Ian Rogers
Acked-by: Jiri Olsa
Cc: Adrian Hunter
Cc: Alexander Shishkin
Cc: Andi Kleen
Cc: Leo Yan
Cc: Mark Rutland
Cc: Namhyung Kim
Cc: Peter Zijlstra
Cc: Stephane Eranian
Cc:
From: Ian Rogers
Memory leaks found by applying LLVM's libfuzzer on the tools/perf
parse_events function.
Signed-off-by: Ian Rogers
Cc: Adrian Hunter
Cc: Alexander Shishkin
Cc: Andi Kleen
Cc: Jiri Olsa
Cc: Leo Yan
Cc: Mark Rutland
Cc: Namhyung Kim
Cc: Peter Zijlstra
Cc: Stephane Eranian
From: He Zhe
A NULL pointer may be passed to perf_cpu_map__cpu and then cause a
crash, such as the one commit cb71f7d43ece ("libperf: Setup initial
evlist::all_cpus value") fix.
Signed-off-by: He Zhe
Acked-by: Jiri Olsa
Cc: Andi Kleen
Cc: Kyle Meyer
Link:
http://lore.kernel.org/lkml/1583665
From: Ian Rogers
free_list_evsel() deals with tools/perf/ evsels, not with libperf
perf_evsels, use the right destructor and avoid a leak, as
evsel__delete() will delete something perf_evsel__delete() doesn't.
Signed-off-by: Ian Rogers
Cc: Adrian Hunter
Acked-by: Jiri Olsa
Cc: Alexander Shis
From: Konstantin Khlebnikov
Check if access("devices/system/cpu/cpu%d/topology/core_cpus", F_OK)
fails, which will happen unless the current directory is "/sys".
Simply try to read this file first.
Fixes: 0ccdb8407a46 ("perf tools: Apply new CPU topology sysfs attributes")
Signed-off-by: Konsta
From: Adrian Hunter
Intel PT already has support for creating branch stacks for each context
(per-cpu or per-thread). In the more common per-cpu case, the branch stack
is not separated for different threads, instead being cleared in between
each sample.
That approach will not work very well for
From: Adrian Hunter
There is an existing option to synthesize branch stacks for synthesized
events. Add a new option to synthesize branch stacks for regular events.
Signed-off-by: Adrian Hunter
Cc: Andi Kleen
Cc: Jiri Olsa
Link: http://lore.kernel.org/lkml/20200429150751.12570-5-adrian.hun...
From: Adrian Hunter
The components of the condition do not change, so consolidate them in
one variable.
Signed-off-by: Adrian Hunter
Cc: Andi Kleen
Cc: Jiri Olsa
Link: http://lore.kernel.org/lkml/20200429150751.12570-3-adrian.hun...@intel.com
Signed-off-by: Arnaldo Carvalho de Melo
---
tool
From: Adrian Hunter
Allow for a synthesized branch stack to be added to samples. As with
synthesized call chains, the sample type cannot be changed because it is
needed to continue to parse events. So add and use helper function
evsel__has_br_stack() to indicate a branch stack, whether original o
Hi Eizan,
Thank you for your patch.
Missatge de Eizan Miyamoto del dia dc., 6 de maig
2020 a les 7:51:
>
> This is a cleanup to better handle errors during MDP probe.
>
> Signed-off-by: ei...@chromium.org
ditto, remove the above line.
> Signed-off-by: Eizan Miyamoto
> ---
Other than that:
R
From: Adrian Hunter
Use the new thread_stack__br_sample_late() function to create a thread
stack for regular events.
Example:
# perf record --kcore --aux-sample -e '{intel_pt//,cycles:ppp}' -c 1 uname
Linux
[ perf record: Woken up 2 times to write data ]
[ perf record: Captured and wrot
From: Arnaldo Carvalho de Melo
As they are not 'struct evsel' methods, not part of tools/lib/perf/, aka
libperf, to whom the perf_ prefix belongs.
Cc: Adrian Hunter
Cc: Jiri Olsa
Cc: Namhyung Kim
Signed-off-by: Arnaldo Carvalho de Melo
---
tools/perf/arch/arm/util/cs-etm.c| 4 +-
tools
From: Arnaldo Carvalho de Melo
As those are not 'struct evsel' methods, not part of tools/lib/perf/,
aka libperf, to whom the perf_ prefix belongs.
Cc: Adrian Hunter
Cc: Jiri Olsa
Cc: Namhyung Kim
Signed-off-by: Arnaldo Carvalho de Melo
---
tools/perf/builtin-trace.c | 7 +++
tools
From: Arnaldo Carvalho de Melo
As it is a 'struct evsel' method, not part of tools/lib/perf/, aka
libperf, to whom the perf_ prefix belongs.
Cc: Adrian Hunter
Cc: Jiri Olsa
Cc: Namhyung Kim
Signed-off-by: Arnaldo Carvalho de Melo
---
tools/perf/builtin-report.c | 2 +-
tools/perf/ui/gtk/his
On Wed, 2020-05-06 at 18:45 +0900, Tetsuo Handa wrote:
> On 2020/04/28 20:33, Tetsuo Handa wrote:
> > On 2020/04/27 15:21, Sergey Senozhatsky wrote:
> > > > KERN_NO_CONSOLES is for type of messages where "saved for later
> > > > analysis" is
> > > > important but "printed for immediate notificatio
From: Arnaldo Carvalho de Melo
As those are not 'struct evsel' methods, not part of tools/lib/perf/,
aka libperf, to whom the perf_ prefix belongs.
Cc: Adrian Hunter
Cc: Jiri Olsa
Cc: Namhyung Kim
Signed-off-by: Arnaldo Carvalho de Melo
---
tools/perf/arch/powerpc/util/kvm-stat.c | 2 +
Unwind information for init sections is placed in .ARM.exidx.init.text
and .ARM.extab.init.text. The module core doesn't know that these are
init sections so they are allocated along with the core sections, and if
the core and init sections get allocated in different memory regions
(which is possi
From: Arnaldo Carvalho de Melo
As it is a 'struct evsel' method, not part of tools/lib/perf/, aka
libperf, to whom the perf_ prefix belongs.
Cc: Adrian Hunter
Cc: Jiri Olsa
Cc: Namhyung Kim
Signed-off-by: Arnaldo Carvalho de Melo
---
tools/perf/builtin-script.c| 2 +-
tools/perf/util/e
From: Arnaldo Carvalho de Melo
As it is a 'struct evsel' method, not part of tools/lib/perf/, aka
libperf, to whom the perf_ prefix belongs.
Cc: Adrian Hunter
Cc: Jiri Olsa
Cc: Namhyung Kim
Signed-off-by: Arnaldo Carvalho de Melo
---
tools/perf/util/evsel.c | 4 ++--
tools/perf/util/evsel.
On Mon, May 04, 2020 at 05:38:47PM +0100, Cristian Marussi wrote:
> Add core SCMI Notifications protocol-registration support: allow protocols
> to register their own set of supported events, during their initialization
> phase. Notification core can track multiple platform instances by their
> han
From: Arnaldo Carvalho de Melo
As it is a 'struct evsel' method, not part of tools/lib/perf/, aka
libperf, to whom the perf_ prefix belongs.
Cc: Adrian Hunter
Cc: Jiri Olsa
Cc: Namhyung Kim
Signed-off-by: Arnaldo Carvalho de Melo
---
tools/perf/util/evsel.c | 6 +++---
tools/perf/util/evsel
From: Arnaldo Carvalho de Melo
As the "perf_" prefix should be restricted to functions and types in
tools/lib/perf/, aka libperf, this way we reduce a bit the confusion for
types only in libperf or the ones in the more contained tools/perf/
project.
Cc: Adrian Hunter
Cc: Jiri Olsa
Cc: Namhyung
From: Adrian Hunter
Update documentation to reflect the advent of the --kcore option for
'perf record'.
Signed-off-by: Adrian Hunter
Cc: Andi Kleen
Cc: Jiri Olsa
Link:
http://lore.kernel.org/lkml/20200429150751.12570-10-adrian.hun...@intel.com
Signed-off-by: Arnaldo Carvalho de Melo
---
to
From: Arnaldo Carvalho de Melo
As they are all 'struct evsel' methods, not part of tools/lib/perf/, aka
libperf, to whom the perf_ prefix belongs.
Cc: Adrian Hunter
Cc: Jiri Olsa
Cc: Namhyung Kim
Signed-off-by: Arnaldo Carvalho de Melo
---
tools/perf/builtin-trace.c | 8 ++
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