From: Leon Romanovsky
Changelog:
v3: Rebased on latest rdma-nex, which includes HCA set capability patch
and LAG code and this is why new patch from Maor was added.
v2: https://lore.kernel.org/linux-rdma/20200413133703.932731-1-l...@kernel.org
Dropped patch "RDMA/cm: Set flow label of recv_wc
From: Ira Weiny
Continue the kmap clean up with 2 follow on patches
These apply after the kmap cleanup V2 series:
https://lore.kernel.org/lkml/20200504010912.982044-1-ira.we...@intel.com/
Ira Weiny (2):
kmap: Remove kmap_atomic_to_page()
parisc/kmap: Remove duplicate kmap code
arch/csky/
From: Ira Weiny
parisc reimplements the kmap calls except to flush it's dcache. This is
arguably an abuse of kmap but regardless it is messy and confusing.
Remove the duplicate code and have parisc define
ARCH_HAS_FLUSH_ON_KUNMAP for a kunmap_flush_on_unmap() architecture
specific call to flush
From: Ira Weiny
kmap_atomic_to_page() has no callers and is only defined on 1 arch and
declared on another. Remove it.
Suggested-by: Al Viro
Signed-off-by: Ira Weiny
---
arch/csky/include/asm/highmem.h | 1 -
arch/csky/mm/highmem.c | 13 -
arch/nds32/include/asm/highm
On 28-04-20, 18:10, Alan Mikhak wrote:
> From: Alan Mikhak
>
> Modify dw_edma_device_transfer() to also support the semantics of dma
> device transfer for additional use cases involving pcitest utility as a
> local initiator.
>
> For its original use case, dw-edma supported the semantics of dma
Hi Vinod,
> -Original Message-
> From: Vinod Koul [mailto:vk...@kernel.org]
> Sent: Monday, May 4, 2020 10:46 AM
> To: Rafał Hibner
> Cc: Appana Durga Kedareswara Rao ; Radhey Shyam
> Pandey ; Harini Katakam ; Dan
> Williams ; Michal Simek ; open
> list:DMA GENERIC OFFLOAD ENGINE SUBSYSTE
On Sun, May 03, 2020 at 10:04:47PM -0700, Ira Weiny wrote:
> Grepping for 'asm/highmem.h' and investigations don't reveal any issues...
> But
> you do have me worried. That said 0-day has been crunching on multiple
> versions of this series without issues such as this (save the mips issue
> abo
On Mon, May 4, 2020 at 12:04 PM Atish Patra wrote:
>
> This patch removes the unused functions set_kernel_text_rw/ro.
> Currently, it is not being invoked from anywhere and no other architecture
> (except arm) uses this code. Even in ARM, these functions are not invoked
> from anywhere currently.
On 4/30/20 7:35 PM, Wolfram Sang wrote:
On Thu, Apr 30, 2020 at 05:43:21PM +0200, Alain Volmat wrote:
In case of the I2C client exposes the flag I2C_CLIENT_HOST_NOTIFY,
pm_runtime_get_sync is called in order to always keep active the
adapter. However later on, pm_runtime_put_sync is never called
On Sat, 2020-05-02 at 19:25 +0100, Jonathan Cameron wrote:
> On Tue, 28 Apr 2020 12:31:28 +0300
> Alexandru Ardelean wrote:
>
> > This change cleans up the driver's probe function to use only devm_
> > function variants. This also gets rid of the remove function and moves the
> > clock & regulato
Hello David, & All
This review and mail is more for pointing out the downsides of UTs. I
am not demanding any changes, these comments can be seen as 'nit's.
On Wed, 2020-04-29 at 12:15 +0800, David Gow wrote:
> On Tue, Apr 14, 2020 at 7:46 PM Vaittinen, Matti
> wrote:
> > Hello Stephen & All,
>
On 28-04-20, 16:13, Sanjay R Mehta wrote:
> From: Sanjay R Mehta
>
> This driver add support for AMD PTDMA controller. This device
> performs high-bandwidth memory to memory and IO copy operation.
> Device commands are managed via a circular queue of 'descriptors',
> each of which specifies sour
> … Thus add a call of the function
> “nfp_nsp_close” for the completion of the exception handling.
I suggest to mention also the addition of a jump target because of
a Linux coding style concern.
…
> +++ b/drivers/net/ethernet/netronome/nfp/abm/main.c
…
> @@ -300,12 +297,16 @@ nfp_abm_vnic_set_
Hi Stephen,
On 4/22/2020 2:34 PM, Stephen Boyd wrote:
Quoting Sivaprakash Murugesan (2020-04-13 19:55:19)
The CPU on Qualcomm's IPQ platform devices are clocked primarily by a
PLL and xo which are connected to a mux and enable block, This patch adds
The comma should be a period? Don't write "T
Hi Rob,
On 4/21/2020 2:31 AM, Rob Herring wrote:
On Tue, Apr 14, 2020 at 08:25:16AM +0530, Sivaprakash Murugesan wrote:
This patch adds schema for primary CPU PLL found on few Qualcomm
platforms.
Signed-off-by: Sivaprakash Murugesan
---
[V3]
* Fixed dt binding error in "$id" field.
.../d
On 4/21/2020 2:29 AM, Rob Herring wrote:
On Tue, Apr 14, 2020 at 08:25:15AM +0530, Sivaprakash Murugesan wrote:
Qualcomm APCS global block provides a bunch of generic properties which
are required in a device tree. Add YAML schema for these properties.
Signed-off-by: Sivaprakash Murugesan
--
On 28-04-20, 16:13, Sanjay R Mehta wrote:
> +static void pt_do_cmd_complete(unsigned long data)
> +{
> + struct pt_tasklet_data *tdata = (struct pt_tasklet_data *)data;
> + struct pt_cmd *cmd = tdata->cmd;
> + struct pt_cmd_queue *cmd_q = &cmd->pt->cmd_q;
> + u32 tail;
> +
> +
On Thu, Apr 30, 2020 at 12:36:09PM -0700, Bjorn Andersson wrote:
> On Wed 29 Apr 23:30 PDT 2020, Manivannan Sadhasivam wrote:
>
> > Add devicetree YAML binding for Qualcomm Inter-Processor Communication
> > Controller (IPCC) block.
> >
> > Signed-off-by: Manivannan Sadhasivam
> > ---
> > .../bi
On 28-04-20, 16:13, Sanjay R Mehta wrote:
> From: Sanjay R Mehta
>
> Expose data about the configuration and operation of the
> PTDMA through debugfs entries: device name, capabilities,
> configuration, statistics.
>
> Signed-off-by: Sanjay R Mehta
> ---
> drivers/dma/ptdma/Makefile|
The CPU on Qualcomm's IPQ6018 devices are primarily fed by APSS PLL and XO,
these are connected to a clock mux and enable block.
This patch series adds support for these clocks and inturn enables clocks
required for CPU freq.
[V4]
* Re-written PLL found on IPQ platforms as a separate driver
* A
The Qualcomm ipq6018 has apcs block, add compatible for the same.
Also, the apcs provides a clock controller functionality similar
to msm8916 but the clock driver is different.
Create a child platform device based on the apcs compatible for the
clock controller functionality.
Signed-off-by: Sivap
add dt-binding for ipq6018 apss clock controller
Signed-off-by: Sivaprakash Murugesan
---
include/dt-bindings/clock/qcom,apss-ipq.h | 12
1 file changed, 12 insertions(+)
create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h
diff --git a/include/dt-bindings/clock/qcom,apss-
add support for apps pll and apcs clock.
Signed-off-by: Sivaprakash Murugesan
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 1aa8d
Add dt-bindings for ipq6018 mailbox driver
Reviewed-by: Rob Herring
Signed-off-by: Sivaprakash Murugesan
---
.../bindings/mailbox/qcom,apcs-kpss-global.yaml | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git
a/Documentation/devicetree/bindings/mailbox/
Qualcomm APCS global block provides a bunch of generic properties which
are required in a device tree. Add YAML schema for these properties.
Signed-off-by: Sivaprakash Murugesan
---
[V4]
* Addressed Rob's review comments
.../bindings/mailbox/qcom,apcs-kpss-global.txt | 88
The CPUs on Qualcomm ipq based devices are clocked by an alpha PLL.
Add support for the apss pll found on ipq based devices which can
support CPU frequencies above 1Ghz.
Signed-off-by: Sivaprakash Murugesan
---
drivers/clk/qcom/Kconfig| 8
drivers/clk/qcom/Makefile | 1 +
dr
The CPU on Qualcomm ipq platform is clocked primarily by a aplha PLL
and xo which are connected to a mux and enable block.
Add support for the mux and enable block which feeds the CPU on ipq
based devices.
Signed-off-by: Sivaprakash Murugesan
---
[V4]
* Addressed review comments
drivers/clk/qc
Add dt-binding for apss pll found on QCOM IPQ platforms
Signed-off-by: Sivaprakash Murugesan
---
.../bindings/clock/qcom,ipq-apsspll.yaml | 49 ++
1 file changed, 49 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/qcom,ipq-apsspll.yaml
di
Hi Robert,
On 20-04-30 18:11, Robert Foss wrote:
> Hey Marco,
>
> On Thu, 30 Apr 2020 at 14:07, Marco Felsch wrote:
> >
> > On 20-04-30 13:20, Sakari Ailus wrote:
> > > On Thu, Apr 30, 2020 at 12:11:57PM +0200, Marco Felsch wrote:
> > > > On 20-04-30 12:59, Sakari Ailus wrote:
> > > > > Hi Marco
On Mon, May 4, 2020 at 9:24 AM Zong Li wrote:
>
> Put __cpu_up_stack_pointer and __cpu_up_task_pointer in data section.
> Currently, these two variables are put in bss section, there is a
> potential risk that secondary harts get the uninitialized value before
> main hart finishing the bss clearin
The paranoidal pointer check in IRQ handler looks very strange - it
really protects us only against bogus drivers which request IRQ line
with null pointer dev_id. However, the code fragment is incorrect
because the dev pointer is used before the actual check which leads
to undefined behavior. Remov
On Sat, May 2, 2020 at 2:03 AM Konrad Dybcio wrote:
>
> Signed-off-by: Konrad Dybcio
Reviewed-by: Amit Kucheria
> ---
> Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
On Sun, 2020-05-03 at 12:37 +0100, Jonathan Cameron wrote:
> [External]
>
> On Wed, 29 Apr 2020 10:21:29 +0300
> Alexandru Ardelean wrote:
>
> > From: Dragos Bogdan
> >
> > If the serial interface is used, the 8-bit address should be latched using
> > the rising edge of the WR/FSYNC signal.
>
This patch adds schema for primary CPU PLL found on few Qualcomm
platforms.
Signed-off-by: Sivaprakash Murugesan
---
.../devicetree/bindings/clock/qcom,a53pll.txt | 22
.../devicetree/bindings/clock/qcom,a53pll.yaml | 40 ++
2 files changed, 40 insertion
Paolo,
On 5/3/20 12:19 AM, Paolo Bonzini wrote:
On 02/05/20 11:24, Suravee Suthikulpanit wrote:
The questions to answer are: what is causing the re-entrancy? and why
is dropping the second EOI update safe?
The answer to the latter could well be "because we've already processed
it", but the
On 30. 04. 20, 13:34, Gregory CLEMENT wrote:
> Warn the upper layer when n_gms is ready to receive data
> again. Without this the associated virtual tty remain blocked
s/remain/&s/
> indefinitely.
>
> Fixes: 96fd7ce58ffb ("TTY: create drivers/tty and move the tty core files
> there")
This look
On Sat, May 2, 2020 at 2:03 AM Konrad Dybcio wrote:
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/thermal/qcom/tsens-v0_1.c | 142 +-
> drivers/thermal/qcom/tsens.c | 3 +
> drivers/thermal/qcom/tsens.h | 2 +-
> 3 files changed, 145 insertions(+), 2
so that the driver can load by matching the device tree
if compiled as module.
Cc: sta...@vger.kernel.org # v5.3+
Fixes: 90b86fcc47b4 ("DRM: Add KMS driver for the Ingenic JZ47xx SoCs")
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/ingenic-drm.c | 1 +
1 file changed, 1 inserti
Maxime Ripard 於 2020年4月29日 週三 上午12:21寫道：
>
> Hi,
>
> On Mon, Apr 27, 2020 at 03:23:42PM +0800, Jian-Hong Pan wrote:
> > Hi Maxime,
> >
> > Thanks for your V2 patch series! I'm testing it.
> >
> > This patch series is applied upon mainline kernel 5.7-rc2 cleanly and built.
> > System can boot into
On 30. 04. 20, 13:34, Gregory CLEMENT wrote:
> Use appropriate print helpers for debug messages.
>
> Signed-off-by: Gregory CLEMENT
> ---
> drivers/tty/n_gsm.c | 18 +-
> 1 file changed, 5 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/tty/n_gsm.c b/drivers/tty/n_gsm.c
On 30. 04. 20, 13:34, Gregory CLEMENT wrote:
> For at least some modems like the TELIT LE910, skipping SOF makes
> transfers blocking indefinitely after a short amount of data
> transferred.
>
> Given the small improvement provided by skipping the SOF (just one
> byte on about 100 bytes), it seems
From: Ben Chuang
Need to clear some bits in a vendor-defined register after reboot from
Windows 10.
Fixes: e51df6ce668a ("mmc: host: sdhci-pci: Add Genesys Logic GL975x support")
Reported-by: Grzegorz Kowal
Signed-off-by: Ben Chuang
---
drivers/mmc/host/sdhci-pci-gli.c | 5 +
1 file chang
On Sun, 2020-05-03 at 13:51 +0100, Jonathan Cameron wrote:
> On Wed, 29 Apr 2020 18:17:39 +0300
> Alexandru Ardelean wrote:
>
> > From: Lars-Peter Clausen
> >
> > Let the core handle the buffer scan mask management including allocation
> > and channel selection. Having this handled in a central
On Sun, 2020-05-03 at 16:39 +0100, Jonathan Cameron wrote:
> [External]
>
> On Mon, 27 Apr 2020 16:10:57 +0300
> Alexandru Ardelean wrote:
>
> > The final intent is to localize all buffer ops into the
> > industrialio-buffer.c file, to be able to add support for multiple buffers
> > per IIO devi
On 5/1/20 11:03 PM, Ian Rogers wrote:
> Current expression allows 2 escaped '-,=' characters. However, some
> metrics require more, for example Haswell DRAM_BW_Use.
>
> Fixes: 26226a97724d (perf expr: Move expr lexer to flex)
> Signed-off-by: Ian Rogers
> ---
> tools/perf/util/expr.l | 2 +-
>
On 5/1/20 11:03 PM, Ian Rogers wrote:
> This is expected in expr.y and metrics use floating point values such as
> x86 broadwell IFetch_Line_Utilization.
>
> Fixes: 26226a97724d (perf expr: Move expr lexer to flex)
> Signed-off-by: Ian Rogers
> ---
> tools/perf/util/expr.l | 14 +++---
On Sat, May 2, 2020 at 1:06 PM Bin Meng wrote:
> From: Bin Meng
>
> CONFIG_MTD_M25P80 was removed and replaced by CONFIG_MTD_SPI_NOR in
> commit b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c")
>
> Signed-off-by: Bin Meng
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Hi Bin,
On Sat, May 2, 2020 at 1:05 PM Bin Meng wrote:
> On Sat, May 2, 2020 at 6:09 PM Geert Uytterhoeven
> wrote:
> > On Sat, May 2, 2020 at 6:27 AM Bin Meng wrote:
> > > From: Bin Meng
> > >
> > > Drop CONFIG_MTD_M25P80 that was removed in
> > > commit b35b9a10362d ("mtd: spi-nor: Move m25
On Thu 30-04-20 11:27:12, Shakeel Butt wrote:
> Lowering memory.max can trigger an oom-kill if the reclaim does not
> succeed. However if oom-killer does not find a process for killing, it
> dumps a lot of warnings.
It shouldn't dump much more than the regular OOM report AFAICS. Sure
there is "Out
On Thu 30-04-20 13:20:10, Shakeel Butt wrote:
> On Thu, Apr 30, 2020 at 12:29 PM Johannes Weiner wrote:
> >
> > On Thu, Apr 30, 2020 at 11:27:12AM -0700, Shakeel Butt wrote:
> > > Lowering memory.max can trigger an oom-kill if the reclaim does not
> > > succeed. However if oom-killer does not find
On Thu, Apr 30, 2020 at 01:18:07PM -0700, Bjorn Andersson wrote:
> On Wed 29 Apr 23:30 PDT 2020, Manivannan Sadhasivam wrote:
>
> > From: Venkata Narendra Kumar Gutta
> >
> > Add support for the Inter-Processor Communication Controller (IPCC)
> > driver that coordinates the interrupts (inbound &
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