On Wed, Aug 21, 2019 at 12:19 AM David Rientjes wrote:
>
> On Wed, 21 Aug 2019, Michal Hocko wrote:
>
> > > vm.oom_dump_tasks is pretty useful, however, so it's curious why you
> > > haven't left it enabled :/
> >
> > Because it generates a lot of output potentially. Think of a workload
> > with t
On Wed, Aug 21, 2019 at 09:39:25AM -0700, Okash Khawaja wrote:
> Hi Greg N,
>
> Would like to send this as a patch as Greg K-H suggested? If not, I
> can do that with your email in Authored-by: tag?
>
> Thanks,
> Okash
Hi Okash and all,
feel free to submit the patch with my email in the Authored
This patchs series add support of New Amlogic temperature sensor and minimal
thermal zone for SEI510 and ODROID-N2 boards.
First implementation was doing on IIO[1] but after comments i move on thermal
framework.
Formulas and calibration values come from amlogic.
Changes since v3:
- Add cooling
Adding the devicetree binding documentation for the Amlogic temperature
sensor found in the Amlogic Meson G12 SoCs.
the G12A and G12B SoCs are supported.
Signed-off-by: Guillaume La Roque
Reviewed-by: Rob Herring
---
.../bindings/thermal/amlogic,thermal.yaml | 54 +++
1 fil
Amlogic G12A and G12B SoCs integrate two thermal sensors
with the same design.
One is located close to the DDR controller and the other one is
located close to the PLLs (between the CPU and GPU).
The calibration data for each of the thermal sensors instance is
stored in a different location within
Add minimal thermal zone for two temperature sensor
One is located close to the DDR and the other one is
located close to the PLLs (between the CPU and GPU)
Signed-off-by: Guillaume La Roque
Acked-by: Martin Blumenstingl
---
.../boot/dts/amlogic/meson-g12a-sei510.dts| 70 +++
Add minimal thermal zone for two temperature sensor
One is located close to the DDR and the other one is
located close to the PLLs (between the CPU and GPU)
Signed-off-by: Guillaume La Roque
Acked-by: Martin Blumenstingl
---
.../boot/dts/amlogic/meson-g12b-odroid-n2.dts | 76 +++
Add cpu and ddr temperature sensors for G12 Socs
Signed-off-by: Guillaume La Roque
Reviewed-by: Martin Blumenstingl
---
.../boot/dts/amlogic/meson-g12-common.dtsi| 20 +++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
b/arc
Add myself as maintainer for Amlogic Thermal driver.
Signed-off-by: Guillaume La Roque
Reviewed-by: Neil Armstrong
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index fb2b12f75c37..299f27d11058 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@
On Tue, Aug 20, 2019 at 8:25 PM David Rientjes wrote:
>
> On Tue, 20 Aug 2019, Edward Chron wrote:
>
> > For an OOM event: print oom_score_adj value for the OOM Killed process to
> > document what the oom score adjust value was at the time the process was
> > OOM Killed. The adjustment value can b
Hi Ben,
Those are correct adjustment and I had tested previously.
Thanks,
Justin
Reviewed-by: Justin Lee
> Update response packet length for the following commands per NC-SI spec
> - Get Controller Packet Statistics
> - Get NC-SI Statistics
> - Get NC-SI Pass-through Statistics command
>
>
On 8/21/19 6:41 AM, YueHaibing wrote:
> Use devm_platform_ioremap_resource() to simplify the code a bit.
> This is detected by coccinelle.
>
> Reported-by: Hulk Robot
> Signed-off-by: YueHaibing
> ---
> drivers/net/ethernet/broadcom/genet/bcmgenet.c | 4 +---
> 1 file changed, 1 insertion(+), 3
On Wed, Aug 21, 2019 at 09:08:48PM +0200, Thomas Gleixner wrote:
> The code contains three slightly different copies of validating whether a
> given clock resolves to a valid task and whether the current caller has
> permissions to access it.
>
> Create central functions. Replace check_clock() as
Hello,
syzbot found the following crash on:
HEAD commit:61ccdad1 Revert "drm/bochs: Use shadow buffer for bochs fr..
git tree: https://github.com/google/kmsan.git master
console output: https://syzkaller.appspot.com/x/log.txt?x=1596d33c60
kernel config: https://syzkaller.appspot.c
Hello,
syzbot found the following crash on:
HEAD commit:61ccdad1 Revert "drm/bochs: Use shadow buffer for bochs fr..
git tree: https://github.com/google/kmsan.git master
console output: https://syzkaller.appspot.com/x/log.txt?x=13d6909c60
kernel config: https://syzkaller.appspot.c
Hello,
syzbot found the following crash on:
HEAD commit:6e625a1a Merge tag 'xtensa-20190816' of git://github.com/j..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=174e04ac60
kernel config: https://syzkaller.appspot.com/x/.config?x=3ff364e429585cf2
da
On Wed 07 Aug 00:09 PDT 2019, Sibi Sankar wrote:
> Add the corresponding APSS shared offset for SM8150 and SC7180 SoCs.
>
> Signed-off-by: Sibi Sankar
Reviewed-by: Bjorn Andersson
> ---
> drivers/mailbox/qcom-apcs-ipc-mailbox.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/driv
From: Branden Bonaby Sent: Monday, August 19, 2019
7:45 PM
>
> Introduce user specified latency in the packet reception path.
>
> Signed-off-by: Branden Bonaby
> ---
> Changes in v2:
> - Add #ifdef in Kconfig file so test code will not interfere
>with non-test code.
> - Move test code fu
Zdravstvujte! Vas interesujut klientskie bazy dannyh?
On Wed 07 Aug 00:09 PDT 2019, Sibi Sankar wrote:
> This patch series adds SCM, APSS shared mailbox and QMP AOSS PD/clock
> support on SM8150 and SC7180 SoCs.
>
> v2:
> * re-arrange the compatible lists in sort order
>
Applied patches 1-3 and 6-7.
Regards,
Bjorn
> Sibi Sankar (7):
> soc: qc
On Wed 21 Aug 11:42 PDT 2019, Vinod Koul wrote:
> This series adds DTS for SM8150, PMIC PM8150, PM8150B, PM8150L and
> the MTP for SM8150.
>
Applied, with Amit's acks.
> Changes in v4:
> - Update the address and size cell to 2 and extend ranges and describe DMA
>space
> - Fix node locatio
> -Original Message-
> From: linux-kernel-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Troy Benjegerdes
> Sent: Wednesday, August 21, 2019 11:25 PM
> To: Atish Patra
> Cc: h...@lst.de; paul.walms...@sifive.com; linux-ri...@lists.infradead.org;
> Damien Le Moal ; linux-
> ke
On Thu, Aug 22, 2019 at 12:33:56AM +0200, Frederic Weisbecker wrote:
> On Wed, Aug 21, 2019 at 09:08:48PM +0200, Thomas Gleixner wrote:
> > The code contains three slightly different copies of validating whether a
> > given clock resolves to a valid task and whether the current caller has
> > permi
From: Branden Bonaby Sent: Tuesday, August 20, 2019
4:39 PM
>
> Expose the test parameters as part of the debugfs channel attributes.
> We will control the testing state via these attributes.
>
> Signed-off-by: Branden Bonaby
> ---
> Changes in v3:
> - Change call to IS_ERR_OR_NULL, to IS_ERR
On Wed, Aug 21, 2019 at 12:47 AM Michal Hocko wrote:
>
> On Wed 21-08-19 00:19:37, David Rientjes wrote:
> > On Wed, 21 Aug 2019, Michal Hocko wrote:
> >
> > > > vm.oom_dump_tasks is pretty useful, however, so it's curious why you
> > > > haven't left it enabled :/
> > >
> > > Because it generates
Split the AER stats into multiple sysfs atributes. Note that
this changes the ABI of the AER stats, but hopefully, there
aren't active users that need to change. This is how the AERs
are being exposed now:
localhost /sys/devices/pci:00/:00:1c.0/aer_stats # ls -l
total 0
-r--r--r--. 1 root
The elements in the aer_uncorrectable_error_string[] refer to
the bit names in Uncorrectable Error status Register in the PCIe spec
(Sec 7.8.4.2 in PCIe 4.0)
Add the last error bit in the strings array that was missing.
Signed-off-by: Rajat Jain
---
drivers/pci/pcie/aer.c | 3 ++-
1 file change
Neil Armstrong writes:
> Add support for the General Purpose Amlogic Everything-Else Power controller,
> with the first support for G12A and SM1 SoCs dedicated to the VPU, PCIe,
> USB, NNA, GE2D and Ethernet Power Domains.
>
> Signed-off-by: Neil Armstrong
Nice! Thanks for generalizing this.
Instead of printing the policy, which is incidentally a kernel pointer,
so with limited interest, print the cpufreq driver name that failed to
be suspend, which is more useful for debugging.
Fixes: 2f0aea936360 ("cpufreq: suspend governors on system suspend/hibernate")
Signed-off-by: Florian Faine
This is a respin of the "Address rcutorture issues" patchset,
minus the actual rcutorture changes.
I still plan to implement detection of bad nesting scenarios, but it's
complicated by the need to distinguish (on a non-RT kernel) between
irq/preempt disabling that would and would not happen on an
Without this, rcu_note_context_switch() will complain if an RCU read
lock is held when migrate_enable() calls stop_one_cpu().
Signed-off-by: Scott Wood
---
v2: Added comment.
If my migrate disable changes aren't taken, then pin_current_cpu()
will also need to use sleeping_lock_inc() because call
A plain local_bh_disable() is documented as creating an RCU critical
section, and (at least) rcutorture expects this to be the case. However,
in_softirq() doesn't block a grace period on PREEMPT_RT, since RCU checks
preempt_count() directly. Even if RCU were changed to check
in_softirq(), that wo
Besides restoring behavior that used to be default on RT, this avoids
a deadlock on scheduler locks:
[ 136.894657] 039:
[ 136.900401] 039: WARNING: possible recursive locking detected
[ 136.906146] 039: 5.2.9-rt3.dbg+ #174 Tainted: GE
[
> -Original Message-
> From: owner-linux...@kvack.org On Behalf
> Of Matthew Wilcox
> Sent: Tuesday, August 20, 2019 3:21 PM
> To: Nitin Gupta
> Cc: a...@linux-foundation.org; vba...@suse.cz;
> mgor...@techsingularity.net; mho...@suse.com;
> dan.j.willi...@intel.com; Yu Zhao ; Qian Cai
Guillaume La Roque writes:
> Add minimal thermal zone for two temperature sensor
> One is located close to the DDR and the other one is
> located close to the PLLs (between the CPU and GPU)
>
> Signed-off-by: Guillaume La Roque
> Acked-by: Martin Blumenstingl
> ---
> .../boot/dts/amlogic/meson
Neil Armstrong writes:
> Update compatible of the pwc-vpu node and add the HDMI support nodes
> for the Amlogic SM1 Based SEI610 Board.
I think this changelog is out of date. It's not doing anything with the
VPU pwrc node.
Kevin
> Signed-off-by: Neil Armstrong
> ---
> .../boot/dts/amlogic/m
> On Aug 21, 2019, at 4:02 PM, Anup Patel wrote:
>
>
>
>> -Original Message-
>> From: linux-kernel-ow...@vger.kernel.org > ow...@vger.kernel.org> On Behalf Of Troy Benjegerdes
>> Sent: Wednesday, August 21, 2019 11:25 PM
>> To: Atish Patra
>> Cc: h...@lst.de; paul.walms...@sifive.co
On Wed, Aug 21, 2019 at 06:19:04PM -0500, Scott Wood wrote:
> A plain local_bh_disable() is documented as creating an RCU critical
> section, and (at least) rcutorture expects this to be the case. However,
> in_softirq() doesn't block a grace period on PREEMPT_RT, since RCU checks
> preempt_count(
On Wed, Aug 21, 2019 at 06:19:05PM -0500, Scott Wood wrote:
> Without this, rcu_note_context_switch() will complain if an RCU read
> lock is held when migrate_enable() calls stop_one_cpu().
>
> Signed-off-by: Scott Wood
I have to ask... Both sleeping_lock_inc() and sleeping_lock_dec() are
no-op
Guillaume La Roque writes:
> This patchs series add support of New Amlogic temperature sensor and minimal
> thermal zone for SEI510 and ODROID-N2 boards.
>
> First implementation was doing on IIO[1] but after comments i move on thermal
> framework.
> Formulas and calibration values come from aml
On Wed, Aug 21, 2019 at 09:08:49PM +0200, Thomas Gleixner wrote:
> Replace the next slightly different copy of permission checks. That also
> removes the necessarity to check the return value of the sample functions
> because the clock id is already validated.
>
> Signed-off-by: Thomas Gleixner
>
On Wed, Aug 21, 2019 at 06:19:06PM -0500, Scott Wood wrote:
> Besides restoring behavior that used to be default on RT, this avoids
> a deadlock on scheduler locks:
>
> [ 136.894657] 039:
> [ 136.900401] 039: WARNING: possible recursive locking detect
Guillaume La Roque writes:
> Adding the devicetree binding documentation for the Amlogic temperature
> sensor found in the Amlogic Meson G12 SoCs.
> the G12A and G12B SoCs are supported.
>
> Signed-off-by: Guillaume La Roque
> Reviewed-by: Rob Herring
nit: put your sign-off at the end. The t
On Wed, Aug 21, 2019 at 09:08:50PM +0200, Thomas Gleixner wrote:
> Yet another copy of the same thing gone...
>
> Signed-off-by: Thomas Gleixner
> ---
Reviewed-by: Frederic Weisbecker
From: Wei Hu Sent: Wednesday, August 21, 2019 4:11 AM
>
> Beginning from Windows 10 RS5+, VM screen resolution is obtained from host.
> The "video=hyperv_fb" boot time option is not needed, but still can be
> used to overwrite what the host specifies. The VM resolution on the host
> could be set
On Wed, Aug 21, 2019 at 01:44:21PM -0700, Ira Weiny wrote:
> > The order FD's are closed during sigkill is not deterministic, so when
> > all the fputs happen during a kill'd exit we could end up blocking in
> > close(fd) as close(uverbs) will come after in the close
> > list. close(uverbs) is the
On Wed, Aug 21, 2019 at 01:24:20PM -0300, Jason Gunthorpe wrote:
> On Tue, Aug 20, 2019 at 07:58:22PM -0700, Dan Williams wrote:
> > On Tue, Aug 20, 2019 at 6:27 AM Jason Gunthorpe wrote:
> > >
> > > On Mon, Aug 19, 2019 at 06:44:02PM -0700, Dan Williams wrote:
> > > > On Sun, Aug 18, 2019 at 2:12
On Wed, Aug 21, 2019 at 05:38:20AM +0200, Guillem Jover wrote:
> This type is used to pass the sigset_t from userland to the kernel,
> but it was using the kernel native pointer type for the member
> representing the compat userland pointer to the userland sigset_t.
>
> This messes up the layout,
On Mon, Aug 19, 2019 at 08:49:22AM -0600, Keith Busch wrote:
> On Mon, Aug 19, 2019 at 12:06:23AM -0700, Marta Rybczynska wrote:
> > - On 16 Aug, 2019, at 15:16, Christoph Hellwig h...@lst.de wrote:
> > > Sorry for not replying to the earlier version, and thanks for doing
> > > this work.
> > >
From: Yazen Ghannam
AMD Family 17h systems have a set of secondary Chip Select Base
Addresses and Address Masks. These do not represent unique Chip
Selects, rather they are used in conjunction with the primary
Chip Select registers in certain use cases.
Cache these secondary Chip Select register
From: Yazen Ghannam
The struct chip_select array that's used for saving chip select bases
and masks is fixed at length of two. There should be one struct
chip_select for each controller, so this array should be increased to
support systems that may have more than two controllers.
Increase the si
From: Yazen Ghannam
AMD Family 17h systems currently require address translation in order to
report the system address of a DRAM ECC error. This is currently done
before decoding the syndrome information. The syndrome information does
not depend on the address translation, so the proper EDAC csro
From: Yazen Ghannam
Chip Select memory size reporting on AMD Family 17h was recently fixed
in order to account for interleaving. However, the current method is not
robust.
The Chip Select Address Mask can be used to find the memory size. There
are a couple of cases.
1) For single-rank and dual-
From: Yazen Ghannam
...now that the data is available earlier.
Signed-off-by: Yazen Ghannam
---
drivers/edac/amd64_edac.c | 20
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 84832771dec0..c1cb0234
From: Yazen Ghannam
Split out gathering hardware information from init_one_instance() into a
separate function get_hardware_info().
This is necessary so that the information can be cached earlier and used
to check if memory is populated and if ECC is enabled on a node.
Signed-off-by: Yazen Ghan
From: Yazen Ghannam
Return early before checking for ECC if the node does not have any
populated memory.
Free any cached hardware data before returning. Also, return 0 in this
case since this is not a failure. Other nodes may have memory and the
module should attempt to load an instance for them
From: Yazen Ghannam
Currently, the DIMM info for AMD Family 17h systems is initialized in
init_csrows(). This function is shared with legacy systems, and it has a
limit of two channel support.
This prevents initialization of the DIMM info for a number of ranks, so
there will be missing ranks in
From: Yazen Ghannam
Hi Boris,
This set contains a few fixes for some changes merged in v5.2. There
are also a couple of fixes for older issues. In addition, there are a
couple of patches to add support for Asymmetric Dual-Rank DIMMs.
I don't have the failing config readily available that you us
From: Yazen Ghannam
AMD Family 17h systems support x4 and x16 DRAM devices. However, the
device type is not checked when setting EDAC_CTL_CAP.
Set the appropriate EDAC_CTL_CAP flag based on the device type.
Default to x8 DRAM device when neither the x4 or x16 bits are set.
Fixes: 2d09d8f301f5
From: Yazen Ghannam
Future AMD systems will support "Asymmetric" Dual-Rank DIMMs. These are
DIMMs where the ranks are of different sizes.
The even rank will use the Primary Even Chip Select registers and the
odd rank will use the Secondary Odd Chip Select registers.
Recognize if a Secondary Odd
On Mon, Aug 19, 2019 at 07:06:40PM +0300, Denis Efremov wrote:
> Add pciehp_set_indicators() to set power and attention indicators with a
> single register write. Thus, avoiding waiting twice for Command Complete.
>
> Signed-off-by: Denis Efremov
> ---
> drivers/pci/hotplug/pciehp.h | 1 +
>
On Fri, Aug 16, 2019 at 11:47:21AM +0200, Marta Rybczynska wrote:
> It is not possible to get 64-bit results from the passthru commands,
> what prevents from getting for the Capabilities (CAP) property value.
>
> As a result, it is not possible to implement IOL's NVMe Conformance
> test 4.3 Case 1
Implements the optimization noted in f75fdf22b0a8 ("fuse: don't use
->d_time"), as the additional memory can be significant. (In particular,
on SLAB configurations this 8-byte alloc becomes 32 bytes). Per-dentry,
this can consume significant memory.
Signed-off-by: Khazhismel Kumykov
---
fs/fuse/
The SF2 binding does not specify that the CPU port should have
properties mandatory for successfully instantiating a PHYLINK object. As
such, there will be missing properties (including fixed-link) and when
attempting to validate and later configure link modes, we will have an
incorrect set of para
Instead of having a helper per flag
Signed-off-by: Khazhismel Kumykov
---
fs/fuse/dev.c| 22 +++---
fs/fuse/file.c | 6 +++---
fs/fuse/fuse_i.h | 6 +-
fs/fuse/inode.c | 4 ++--
4 files changed, 9 insertions(+), 29 deletions(-)
diff --git a/fs/fuse/dev.c b/fs/fuse/
account per-file, dentry, and inode data
accounts the per-file reserved request, adding new
fuse_request_alloc_account()
blockdev/superblock and temporary per-request data was left alone, as
this usually isn't accounted
Signed-off-by: Khazhismel Kumykov
---
fs/fuse/dev.c| 6 ++
fs/fuse
On Wed, Aug 21, 2019 at 5:09 PM Khazhismel Kumykov wrote:
>
> Implements the optimization noted in f75fdf22b0a8 ("fuse: don't use
> ->d_time"), as the additional memory can be significant. (In particular,
> on SLAB configurations this 8-byte alloc becomes 32 bytes). Per-dentry,
> this can consume
On Wed, Aug 21, 2019 at 5:10 PM Khazhismel Kumykov wrote:
>
> Instead of having a helper per flag
>
> Signed-off-by: Khazhismel Kumykov
I think it would be better to re-order the patch 2 and 3 of this
series. There will be less code churn.
> ---
> fs/fuse/dev.c| 22 +++---
>
On Wed, 2019-08-21 at 22:27 +0200, Christophe Leroy wrote:
>
> Le 20/08/2019 à 06:36, Alastair D'Silva a écrit :
> > On Fri, 2019-08-16 at 15:52 +, Christophe Leroy wrote:
>
> [...]
>
> >
> > Thanks Christophe,
> >
> > I'm trying a somewhat different approach that requires less
> > knowled
On Wed, Aug 07, 2019 at 05:51:20PM +1000, Benjamin Herrenschmidt wrote:
> +#define NVME_NVM_ADMSQES 6
> #define NVME_NVM_IOSQES 6
> #define NVME_NVM_IOCQES 4
The NVM in the two defines here stands for the NVM command set,
so this should just be named NVME_ADM_SQES o
On Wed, Aug 07, 2019 at 05:51:21PM +1000, Benjamin Herrenschmidt wrote:
> Based on reverse engineering and original patch by
>
> Paul Pawlowski
>
> This adds support for Apple weird implementation of NVME in their
> 2018 or later machines. It accounts for the twice-as-big SQ entries
> for the IO
On Wed, Aug 07, 2019 at 05:51:22PM +1000, Benjamin Herrenschmidt wrote:
> Another issue with the Apple T2 based 2018 controllers seem to be
> that they blow up (and shut the machine down) if there's a tag
> collision between the IO queue and the Admin queue.
>
> My suspicion is that they use our t
On Thu, 2019-08-22 at 02:28 +0200, Christoph Hellwig wrote:
> On Wed, Aug 07, 2019 at 05:51:20PM +1000, Benjamin Herrenschmidt
> wrote:
> > +#define NVME_NVM_ADMSQES 6
> > #define NVME_NVM_IOSQES6
> > #define NVME_NVM_IOCQES4
>
> The NVM in the two defines here stands f
On Wed, 21 Aug 2019 at 15:55, Paolo Bonzini wrote:
>
> On 20/08/19 09:16, Wanpeng Li wrote:
> > Kindly reminder, :)
>
> It's already in my pull request from yesterday.
Do you mean this pull
https://www.mail-archive.com/qemu-devel@nongnu.org/msg638707.html ?
This patch is missing.
Regards,
Wanpen
On Wed, 2019-08-21 at 13:50 -0500, Rob Herring wrote:
> On Mon, Aug 05, 2019 at 05:11:53PM +0800, Mars Cheng wrote:
> > Add devicetree bindings for Mediatek mt6779 SoC Pin Controller.
>
> checkpatch.pl reports typo in subject.
>
> Otherwise,
>
> Reviewed-by: Rob Herring
>
got it, will fix the
If tlbflush request is for page only, there is no need to do a
complete local tlb shootdown.
Just do a local tlb flush for the given address.
Signed-off-by: Atish Patra
---
arch/riscv/mm/tlbflush.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/mm/tlbflush.c
This series adds few optimizations to reduce the trap cost in the tlb
flush path. We should only make SBI calls to remote tlb flush only if
absolutely required.
This series is based on Christoph's series:
http://lists.infradead.org/pipermail/linux-riscv/2019-August/006148.html
Changes from v2->
In RISC-V, tlb flush happens via SBI which is expensive. If the local
cpu is the only cpu in cpumask, there is no need to invoke a SBI call.
Just do a local flush and return.
Signed-off-by: Atish Patra
---
arch/riscv/mm/tlbflush.c | 15 +++
1 file changed, 15 insertions(+)
diff --g
Hi Marc
> >>> + soc {
> >>> + #address-cells = <2>;
> >>> + #size-cells = <2>;
> >>> + compatible = "simple-bus";
> >>> + ranges;
> >>> +
> >>> + gic: interrupt-controller@0c00 {
> >>> + compatible = "arm,gic-v3";
> >>> +
SBI calls are expensive. If cpumask is empty, there is no need to
trap via SBI as no remote tlb flushing is required.
Signed-off-by: Atish Patra
---
arch/riscv/mm/tlbflush.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index 9f58b3790
On Tue, 6 Aug 2019 at 14:20, Paolo Bonzini wrote:
>
> On 06/08/19 02:35, Wanpeng Li wrote:
> > Thank you, Paolo! Btw, how about other 5 patches?
>
> Queued everything else too.
How about patch 4/6~5/6, they are not in kvm/queue. :)
Regards,
Wanpeng Li
On Wed, Aug 21, 2019 at 11:59:53PM +, Ghannam, Yazen wrote:
> I've also added RFC patches to avoid the "ECC disabled" message for
> nodes without memory. I haven't fully tested these, but I wanted to get
> your thoughts. Here's an earlier discussion:
> https://lkml.kernel.org/r/20180321191335.7
> The series applies on top of:
>
>git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers/core
>
> and is available from git as well:
>
>git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git WIP.timers/core
Btw, for some reason git here seems to be very unhappy about that
On Thu, Aug 22, 2019 at 02:54:34AM +0200, Christoph Hellwig wrote:
> > The series applies on top of:
> >
> >git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers/core
> >
> > and is available from git as well:
> >
> >git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git WI
On Thu, Aug 22, 2019 at 03:02:04AM +0200, Frederic Weisbecker wrote:
> > which repeats every time I fetch. I can't of anythign particular on
> > my side that would cause this.
>
> Yeah I had to run "git remote prune tip" and fetch again.
>
> Apparently there was an old remote branch tip/WIP.time
On Wed, 2019-08-21 at 20:52 +0300, Andrey Ryabinin wrote:
>
> On 8/20/19 8:37 AM, Walter Wu wrote:
> > On Tue, 2019-08-06 at 13:43 +0800, Walter Wu wrote:
> >> This patch adds memory corruption identification at bug report for
> >> software tag-based mode, the report show whether it is "use-after-
From: Marco Hartman Sent: Wednesday, August 21, 2019 7:44 PM
> IEEE 802.3ae clause 45 defines a modified MDIO protocol that uses a two
> staged access model in order to increase the address space.
>
> This patch adds support for C45 MDIO read and write accesses, which are
> used whenever the MII_A
On 08/21/19 at 05:12pm, Qian Cai wrote:
> > > Does disabling CONFIG_RANDOMIZE_BASE help? Maybe that workaround has
> > > regressed. Effectively we need to find what is causing the kernel to
> > > sometimes be placed in the middle of a custom reserved memmap= range.
> >
> > Yes, disabling KASLR wor
On Wed, Aug 21, 2019 at 04:27:00PM +, Long Li wrote:
> >>>Subject: Re: [PATCH 0/3] fix interrupt swamp in NVMe
> >>>
> >>>On Wed, Aug 21, 2019 at 07:47:44AM +, Long Li wrote:
> >>>Subject: Re: [PATCH 0/3] fix interrupt swamp in NVMe
> >>>
> >>>On 20/08/2019 09:25, Ming Lei wr
Tool function issues: Please validate args errors for '-p' and '--path', in
or following validate_args_path().
Comments of functionality:
- it's confusing when fuzz_testing are all OFF, then user run ' python3
/home/lisa/vmbus_testing -p
/sys/kernel/debug/hyperv/000d3a6e-4548-000d-3a
On 2019/8/21 20:38, James Clark wrote:
> Hi,
>
> I also had a look at this and had a question about the --spe option.
> It seems that whatever options I give it, the output is the same:
>
> perf report
> And
> perf report --spe=t
>
> Both give the same result:
>
> # Samples:
On Wed, Aug 21, 2019 at 05:46:42PM -0700, Atish Patra wrote:
> In RISC-V, tlb flush happens via SBI which is expensive. If the local
> cpu is the only cpu in cpumask, there is no need to invoke a SBI call.
>
> Just do a local flush and return.
>
> Signed-off-by: Atish Patra
> ---
> arch/riscv/m
On Wed, Aug 21, 2019 at 05:46:43PM -0700, Atish Patra wrote:
> + if (size <= PAGE_SIZE && size != -1)
> + local_flush_tlb_page(start);
> + else
> + local_flush_tlb_all();
As Andreas pointed out (unsigned long)-1 is actually larger tha
On Wed, Aug 21, 2019 at 05:46:44PM -0700, Atish Patra wrote:
> SBI calls are expensive. If cpumask is empty, there is no need to
> trap via SBI as no remote tlb flushing is required.
>
> Signed-off-by: Atish Patra
> ---
> arch/riscv/mm/tlbflush.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> d
> On Aug 21, 2019, at 9:31 PM, Baoquan He wrote:
>
> On 08/21/19 at 05:12pm, Qian Cai wrote:
Does disabling CONFIG_RANDOMIZE_BASE help? Maybe that workaround has
regressed. Effectively we need to find what is causing the kernel to
sometimes be placed in the middle of a custom re
The kbuild reported a built failure due to a header loop when RCUTINY is
enabled with my pending riscv-nommu port. Switch rcutiny.h to only
include the minimal required header to get HZ instead.
Signed-off-by: Christoph Hellwig
---
include/linux/rcutiny.h | 2 +-
1 file changed, 1 insertion(+),
On Wed, Aug 21, 2019 at 7:34 PM Ming Lei wrote:
> On Wed, Aug 21, 2019 at 04:27:00PM +, Long Li wrote:
> > Here is the command to benchmark it:
> >
> > fio --bs=4k --ioengine=libaio --iodepth=128
> > --filename=/dev/nvme0n1:/dev/nvme1n1:/dev/nvme2n1:/dev/nvme3n1:/dev/nvme4n1:/dev/nvme5n1:/dev
Refactor enqueue_entity, dequeue_entity, and update_load_avg, in order
to split out the things we still want to happen at every level in the
cgroup hierarchy with a flat runqueue from the things we only need to
happen once.
No functional changes.
Signed-off-by: Rik van Riel
---
kernel/sched/fai
Sometimes the hierarchical load of a sched_entity needs to be calculated.
Rename task_h_load to task_se_h_load, and directly pass a sched_entity to
that function.
Move the function declaration up above where it will be used later.
No functional changes.
Signed-off-by: Rik van Riel
Reviewed-by:
The current implementation of the CPU controller uses hierarchical
runqueues, where on wakeup a task is enqueued on its group's runqueue,
the group is enqueued on the runqueue of the group above it, etc.
This increases a fairly large amount of overhead for workloads that
do a lot of wakeups a seco
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