Hi all,
This small series contains a few fixes for the hrtimer code in RT linux
(v5.2.9-rt3-rebase).
The patch #2 contains a error I managed to reproduce. The other two are
were found while looking at the code.
Cheers,
Julien Grall (3):
hrtimer: Use READ_ONCE to access timer->base in
hrim
There are no guarantee the hrtimer_cancel() will be called on the same
CPU as the non-soft hrtimer is running on so the following scenario
can happen.
CPU0 | CPU1
|
|
Add the PWM DT node in SiFive FU540 soc-specific DT file.
Enable the PWM nodes in HiFive Unleashed board-specific DT file.
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 19 +++
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 8
The 08/21/2019 09:20, Igor Russkikh wrote:
> > Talking about packet numbers, can you describe how PN exhaustion is
> > handled? I couldn't find much about packet numbers at all in the
> > driver patches (I hope the hw doesn't wrap around from 2^32-1 to 0 on
> > the same SA). At some point userspa
Use the standard obj-y form to specify the sub-directories under
arch/riscv/. No functional change intended.
Signed-off-by: Masahiro Yamada
---
arch/riscv/Kbuild | 3 +++
arch/riscv/Makefile | 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/Kbuild
diff --
On 7/24/19 7:10 PM, Krzysztof Kozlowski wrote:
> On Mon, Jul 22, 2019 at 11:46:43AM +0200, Lukasz Luba wrote:
>> Add the chipid label which allows to use it in phandle from other device.
>> Use syscon in compatible to get the regmap of the device register set.
>> The chipid is used in DMC during
On Wed, Aug 21, 2019 at 11:19 AM Andy Shevchenko
wrote:
>
> On Wed, Aug 21, 2019 at 10:06:09AM +0200, Rafael J. Wysocki wrote:
> > From: Rafael J. Wysocki
> >
> > Commit 10a08fd65ec1 ("ACPI: PM: Set up EC GPE for system wakeup from
> > drivers that need it") assumed that the EC GPE would only nee
On 21/8/2019 4:34 PM, Thomas Gleixner wrote:
Secondly, this link is irrelevant. ioapic_dynirq_base has nothing to do
with virtual IRQ number 0. It's a boundary for the dynamic allocation of
virtual interrupt numbers so that the core allocator does not pick
interrupts out of the IOAPIC's fixed in
On Wed, Aug 21, 2019 at 5:19 PM Code Kipper wrote:
>
> On Wed, 14 Aug 2019 at 08:09, wrote:
> >
> > From: Jernej Skrabec
> >
> > I2S doesn't work if parent rate couldn't be change. Difference between
> > wanted and actual rate is too big.
> >
> > Fix this by adding CLK_SET_RATE_PARENT flag to I2
On Wed, Aug 21, 2019 at 11:21:43AM +0800, Tanwar, Rahul wrote:
> On 20/8/2019 10:57 PM, Peter Zijlstra wrote:
> > What would describe the special sause that warranted a new SOC? If this
> > thing is marketed as 'Network Processor' then I suppose we can actually
> > use it, esp. if we're going to s
From: Rafael J. Wysocki
Commit 10a08fd65ec1 ("ACPI: PM: Set up EC GPE for system wakeup from
drivers that need it") assumed that the EC GPE would only need to be
set up for system wakeup if either the intel-hid or the intel-vbtn
driver was in use, but that turns out to be incorrect. In particula
> On Aug 20, 2019, at 1:23 PM, Song Liu wrote:
>
> Before 32-bit support, pti_clone_pmds() always adds PMD_SIZE to addr.
> This behavior changes after the 32-bit support: pti_clone_pgtable()
> increases addr by PUD_SIZE for pud_none(*pud) case, and increases addr by
> PMD_SIZE for pmd_none(*p
On Wed, Aug 21, 2019 at 07:47:44AM +, Long Li wrote:
> >>>Subject: Re: [PATCH 0/3] fix interrupt swamp in NVMe
> >>>
> >>>On 20/08/2019 09:25, Ming Lei wrote:
> On Tue, Aug 20, 2019 at 2:14 PM wrote:
> >
> > From: Long Li
> >
> > This patch set tries to fix interrupt swam
Commit d3c61619568c ("ARM: 8788/1: ftrace: remove old mcount support")
removed the old mcount support, but forget to remove these two
declarations. Remove them to clean up.
Signed-off-by: Jisheng Zhang
---
arch/arm/include/asm/ftrace.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/a
Am Mi., 21. Aug. 2019 um 10:07 Uhr schrieb Miroslav Lichvar
:
> > Currently I do not see the benefit from this. The original intention was to
> > compensate for the remaining offset as good as possible.
>
> That's ok, but IMHO the change should not break the assumptions of
> existing application an
Add SC7180 AOSS reset to the list of possible bindings.
Signed-off-by: Sibi Sankar
---
Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
b/Documentation/de
This patch series adds PDC Global and AOSS reset support on SC7180 SoCs.
Sibi Sankar (4):
dt-bindings: reset: aoss: Add AOSS reset binding for SC7180 SoCs
reset: qcom: aoss: Add support for SC7180 SoCs
dt-bindings: reset: pdc: Add PDC Global binding for SC7180 SoCs
reset: qcom: pdc: Add su
Add AOSS reset support for SC7180 SoCs.
Signed-off-by: Sibi Sankar
---
drivers/reset/reset-qcom-aoss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
index 36db967504507..a400db93eb7d2 100644
--- a/drivers/reset/reset-qcom-ao
Add PCD Global support for SC7180 SoCs.
Signed-off-by: Sibi Sankar
---
drivers/reset/reset-qcom-pdc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/reset/reset-qcom-pdc.c b/drivers/reset/reset-qcom-pdc.c
index ab74bccd4a5b5..d876e48f05524 100644
--- a/drivers/reset/reset-qcom-pdc.c
Add SC7180 PDC global to the list of possible bindings.
Signed-off-by: Sibi Sankar
---
Documentation/devicetree/bindings/reset/qcom,pdc-global.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
b/Documentation/de
On 8/20/2019 9:42 PM, Rob Herring wrote:
On Tue, Aug 20, 2019 at 4:40 AM Dilip Kota wrote:
The Intel PCIe RC controller is Synopsys Designware
based PCIe core. Add YAML schemas for PCIe in RC mode
present in Intel Universal Gateway soc.
Run 'make dt_binding_check' and fix all the warnings.
The common kprobes provides a weak implementation of
arch_kprobe_on_func_entry(). The parisc version is the same as the
common version, so remove it.
Signed-off-by: Jisheng Zhang
---
arch/parisc/kernel/kprobes.c | 4
1 file changed, 4 deletions(-)
diff --git a/arch/parisc/kernel/kprobes.c
There is no particular reason to not enable TSC page clocksource
on 32-bit. mul_u64_u64_shr() is available and despite the increased
computational complexity (compared to 64bit) TSC page is still a huge
win compared to MSR-based clocksource.
In-kernel reads:
MSR based clocksource: 3361 cycles
On Tue, Aug 20, 2019 at 01:15:58PM -0300, Leonardo Bras wrote:
> On Tue, 2019-08-20 at 07:36 +0200, Florian Westphal wrote:
> > Wouldn't fib_netdev.c have the same problem?
> Probably, but I haven't hit this issue yet.
>
> > If so, might be better to place this test in both
> > nft_fib6_eval_type
Hi Sabrina,
On Tue, Aug 20, 2019 at 04:41:19PM +0200, Sabrina Dubroca wrote:
> 2019-08-20, 12:01:40 +0200, Antoine Tenart wrote:
> > So it seems the ability to enable or disable the offloading on a given
> > interface is the main missing feature. I'll add that, however I'll
> > probably (at least
From: Deepa Madiregama
- mixer_ctl_set() function is limiting the volume level
to particular range. This results in incorrect initial
volume setting for that device.
- In USB mixer while calculating the dBmin/dBmax values
resolution factor is hardcoded to 256 which results in
populating t
On 21/08/2019 10:44, Ming Lei wrote:
On Wed, Aug 21, 2019 at 07:47:44AM +, Long Li wrote:
Subject: Re: [PATCH 0/3] fix interrupt swamp in NVMe
On 20/08/2019 09:25, Ming Lei wrote:
On Tue, Aug 20, 2019 at 2:14 PM wrote:
From: Long Li
This patch set tries to fix interrupt swamp in NVMe
--
Dear Beloved,
I'm Reverend Father David Nolan, I was born in Brooklyn, NYC, 1970, I
was ordained into the Catholic Priesthood.
Please take your time to read this message, although we have never met
before, this is no spam, It's a real message sent to you. I know also
that you will be amazed
On 20 Aug 2019, at 17:16, Ilya Maximets wrote:
Tx code doesn't clear the descriptor status after cleaning.
So, if the budget is larger than number of used elems in a ring, some
descriptors will be accounted twice and xsk_umem_complete_tx will move
prod_tail far beyond the prod_head breaking t
On Tue, Aug 20, 2019 at 01:23:14PM -0700, Song Liu wrote:
> Before 32-bit support, pti_clone_pmds() always adds PMD_SIZE to addr.
> This behavior changes after the 32-bit support: pti_clone_pgtable()
> increases addr by PUD_SIZE for pud_none(*pud) case, and increases addr by
> PMD_SIZE for pmd_non
From: Ramuthevar Vadivel Murugan
Add a YAML schema to use the host controller driver with the
eMMC PHY on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
changes in v3:
- resolve 'make dt_binding_check' warnings
changes in v2:
As per Rob Herring review commen
On 29/07/2019 19:03, Avi Fishman wrote:
> NPCM7XX_Tx_OPER GENMASK bits where wrong,
> Since NPCM7XX_REG_TICR0 register reset value of those bits was 0,
> it did not cause an issue.
> in npcm7xx_timer_oneshot() the original NPCM7XX_REG_TCSR0 register was
> read again after masking it with ~NPCM7XX_T
From: Ramuthevar Vadivel Murugan
Add support for eMMC PHY on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
changes in v3:
- As per Andy's review comments macro optimization,aligned
function call in proper order and udelay added.
changes in v2:
- optimize I
If binding a pending gadget driver fails we should not
remove it from the pending driver list, otherwise it
will cause a segmentation fault later when the gadget driver is
unloaded.
Test case:
- Make sure no UDC is available
- modprobe g_mass_storage file=wrongfile
- Load UDC driver so it becomes
Attn: Fund Beneficiary
This is the 2nd time i am sending you this notification letter
regarding your abandoned ATM Visa Card valued sum of US$9,500.000.00
and i have not
received any positive respond from you or asking a suggestion on how
you wish to receive your ATM Visa Card. Once again; I am Mr
On Tue, 13 Aug 2019 at 16:41, Michael K. Johnson wrote:
>
> Add support for the GL9750 and GL9755 chipsets.
>
> Signed-off-by: Ben Chuang
> Co-developed-by: Michael K Johnson
> Signed-off-by: Michael K Johnson
I am having a hard time to follow the different versions of the
patches in the serie
On Wed, 21 Aug 2019, Song Liu wrote:
> > On Aug 20, 2019, at 1:23 PM, Song Liu wrote:
> >
> > Before 32-bit support, pti_clone_pmds() always adds PMD_SIZE to addr.
> > This behavior changes after the 32-bit support: pti_clone_pgtable()
> > increases addr by PUD_SIZE for pud_none(*pud) case, and
Since version 4 of eLCDIF, there are some registers that can do
transformations on the input data, like re-arranging the pixel
components. By doing that, we can support more pixel formats.
This patch adds support for X/ABGR and RGBX/A. Although, the local alpha
is not supported by eLCDIF, the alpha
On Wed, Aug 21, 2019 at 11:53:12AM +0200, Hubert Feurstein wrote:
> Am Mi., 21. Aug. 2019 um 10:07 Uhr schrieb Miroslav Lichvar
> > Because those reports/statistics are important in calculation of
> > maximum error. If someone had a requirement for a clock to be accurate
> > to 1.5 microseconds and
On Wed, 21 Aug 2019 at 12:53, Hubert Feurstein wrote:
>
> Am Mi., 21. Aug. 2019 um 10:07 Uhr schrieb Miroslav Lichvar
> :
> > > Currently I do not see the benefit from this. The original intention was
> > > to
> > > compensate for the remaining offset as good as possible.
> >
> > That's ok, but I
In a couple of places there is a need to select whether read-only
protection of shadow pages is performed with PAGE_KERNEL_RO or with
PAGE_READONLY.
Add a helper to avoid duplicating the choice.
Signed-off-by: Christophe Leroy
Cc: sta...@vger.kernel.org
---
This small series applies on top of p
Today, the STACK_END_MAGIC is set on init_stack in start_kernel().
To avoid a false 'Thread overran stack, or stack corrupted' message
on early Oopses, setup STACK_END_MAGIC as soon as possible.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 4
1 file changed, 4 inser
Uncompressing Kernel Image ... OK
Loading Device Tree to 01ff7000, end 01fff74f ... OK
[0.00] printk: bootconsole [udbg0] enabled
[0.00] BUG: Unable to handle kernel data access at 0xf818c000
[0.00] Faulting instruction address: 0xc0013c7c
[0.00] Thread overran
"Naveen N. Rao" writes:
> Since BPF constant blinding is performed after the verifier pass, there
> are certain ALU32 instructions inserted which don't have a corresponding
> zext instruction inserted after. This is causing a kernel oops on
> powerpc and can be reproduced by running 'test_cgroup_s
From: Vidyakumar Athota
Most of the modern codecs supports 352.8KHz and 384KHz sample rates.
Currently HW params fails to set 352.8Kz and 384KHz sample rate
as these are not in known rates list.
Add these new rates to known list to allow them.
This patch also adds defines in pcm.h so that driver
On Tue, 20 Aug 2019 at 11:49, Hubert Feurstein wrote:
>
> From: Hubert Feurstein
>
> In order to improve the synchronisation precision of phc2sys (from
> the linuxptp project) for devices like switches which are attached
> to the MDIO bus, it is necessary the get the system timestamps as
> close
On Tue, 2019-08-20 at 20:54 +0100, Andrew Murray wrote:
> On Tue, Aug 20, 2019 at 05:06:22PM +, Chocron, Jonathan wrote:
> > On Tue, 2019-08-20 at 16:25 +0100, Andrew Murray wrote:
> > > On Tue, Aug 20, 2019 at 02:52:30PM +, Chocron, Jonathan
> > > wrote:
> > > > On Mon, 2019-08-19 at 19:23
On Wed, Aug 21, 2019 at 12:10:08PM +0200, Peter Zijlstra wrote:
> On Tue, Aug 20, 2019 at 01:23:14PM -0700, Song Liu wrote:
> > host-5.2-after # grep "x pmd" /sys/kernel/debug/page_tables/dump_pid
> > 0x0060-0x00e0 8M USR ro PSE
> > x pmd
> > 0x
On Tue, Aug 20, 2019 at 01:29:32PM -0700, Paul E. McKenney wrote:
> On Tue, Aug 20, 2019 at 03:56:12PM +0200, Peter Zijlstra wrote:
> > On Sat, Aug 17, 2019 at 01:08:02AM -0700, Linus Torvalds wrote:
> >
> > > The data tearing issue is almost a non-issue. We're not going to add
> > > WRITE_ONCE()
On Wed, 2019-08-21 at 15:24 +0530, Sibi Sankar wrote:
> Add SC7180 AOSS reset to the list of possible bindings.
>
> Signed-off-by: Sibi Sankar
> ---
> Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documenta
On Wed, Aug 21, 2019 at 08:20:48AM +, Long Li wrote:
> >>>Subject: Re: [PATCH 1/3] sched: define a function to report the number of
> >>>context switches on a CPU
> >>>
> >>>On Mon, Aug 19, 2019 at 11:14:27PM -0700, lon...@linuxonhyperv.com
> >>>wrote:
> From: Long Li
>
> The nu
On Wed, Aug 21, 2019 at 08:37:55AM +, Long Li wrote:
> >>>Subject: Re: [PATCH 3/3] nvme: complete request in work queue on CPU
> >>>with flooded interrupts
> >>>
> >>>On Mon, Aug 19, 2019 at 11:14:29PM -0700, lon...@linuxonhyperv.com
> >>>wrote:
> From: Long Li
>
> When a NVMe h
On Tue, Aug 20, 2019 at 02:19:16PM -0400, Hui Peng wrote:
> In the while loop of technisat_usb2_get_ir, it scans through
> a fix-sized buffer read from the device side, the termination
> condition of the loop is `*b == 0xff`. If no `0xff` byte is read
> from the device side, OOB access happens.
>
In order to get the clock by phandle and use it with regmap it needs to be
compatible with syscon. The DMC driver uses two registers from clock
register set and needs the regmap of them.
Signed-off-by: Lukasz Luba
---
arch/arm/boot/dts/exynos5420.dtsi | 2 +-
arch/arm/boot/dts/exynos5800.dtsi |
The patch adds description for DT binding for a new Exynos5422 Dynamic
Memory Controller device.
Acked-by: Krzysztof Kozlowski
Reviewed-by: Rob Herring
Signed-off-by: Lukasz Luba
---
.../memory-controllers/exynos5422-dmc.txt | 73 +++
1 file changed, 73 insertions(+)
creat
This patch adds driver for Exynos5422 Dynamic Memory Controller.
The driver provides support for dynamic frequency and voltage scaling
for DMC and DRAM. It supports changing timings of DRAM running with
different frequency. There is also an algorithm to calculate timigns
based on memory description
Change directory name to be ready for new types of memories.
Reviewed-by: Rob Herring
Signed-off-by: Lukasz Luba
---
.../devicetree/bindings/{lpddr2 => ddr}/lpddr2-timings.txt | 0
Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2.txt| 2 +-
2 files changed, 1 insertion(+), 1 de
Thanks Daniel,
It seems more clear now :)
Good to know about the need for Fixes tag.
On Wed, Aug 21, 2019 at 1:11 PM Daniel Lezcano
wrote:
>
> On 29/07/2019 19:03, Avi Fishman wrote:
> > NPCM7XX_Tx_OPER GENMASK bits where wrong,
> > Since NPCM7XX_REG_TICR0 register reset value of those bits was
Specifies the AC timing parameters of the LPDDR3 memory device.
Reviewed-by: Rob Herring
Signed-off-by: Lukasz Luba
---
.../bindings/ddr/lpddr3-timings.txt | 58 +++
.../devicetree/bindings/ddr/lpddr3.txt| 97 +++
2 files changed, 155 insertions(+)
cre
The patch adds AC timings information needed to support LPDDR3 and memory
controllers. The structure is used in of_memory and currently in Exynos
5422 DMC. Add parsing data needed for LPDDR3 support.
It is currently used in Exynos5422 Dynamic Memory Controller.
Acked-by: Krzysztof Kozlowski
Signe
Enable driver for Exynos5422 Dynamic Memory Controller supporting
dynamic frequency and voltage scaling in Exynos5422 SoCs.
Signed-off-by: Lukasz Luba
---
arch/arm/configs/exynos_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/exynos_defconfig
b/arch/arm/configs/e
Hi all,
This is v13 which makes cosmetic changes. It is based on current mainline
(v5.3-rc5) with with devfreq/for-next where there is a PPMU patch [1].
The patch set adds support of Dynamic Memory Controller for Exynos5422 SoC.
The driver supports Dynamic Voltage and Frequency Scaling
for the DM
Add description of Dynamic Memory Controller and PPMU counters.
They are used by exynos5422-dmc driver.
There is a definition of the memory chip, which is then used during
calculation of timings for each OPP.
The algorithm in the driver needs these two sets to bound the timings.
Signed-off-by: Luk
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing in e-mail?
On Wed, Aug 21, 2019 at 04:26:17PM +0800, c00423981 wrote:
> Sorry, I cannot understand this problem accurately. I try to un
Hi Rob,
Le mar. 20 août 2019 à 22:50, Rob Herring a écrit :
On Mon, Jul 29, 2019 at 02:31:07PM -0400, Paul Cercueil wrote:
Inside the Video Processing Unit (VPU) of the recent JZ47xx SoCs
from
Ingenic is a second Xburst MIPS CPU very similar to the main core.
This document describes the d
> +static s64 __scale_delta(s64 diff)
> +{
> + do_div(diff, (1 << (ALPHA_BETA_GRANULARITY + 1)) - 1);
> + return diff;
> +}
[...]
> + delta = __scale_delta(((s64)qdelay - q->pi2.target) * q->pi2.alpha);
> + delta += __scale_delta(((s64)qdelay - qdelay_old) * q->pi2.beta);
I just no
On 19.08.19 21:51, Heiner Kallweit wrote:
> On 19.08.2019 19:52, Marco Hartmann wrote:
>> and call it from phy_config_aneg().
>>
> Here something went wrong.
>
>> commit 34786005eca3 ("net: phy: prevent PHYs w/o Clause 22 regs from
>> calling genphy_config_aneg") introduced a check that aborts
>>
Michael Ellerman writes:
> "Naveen N. Rao" writes:
>> Since BPF constant blinding is performed after the verifier pass, there
>> are certain ALU32 instructions inserted which don't have a corresponding
>> zext instruction inserted after. This is causing a kernel oops on
>> powerpc and can be re
Hi Greentime,
On Wed, Aug 21, 2019 at 05:16:13PM +0800, Greentime Hu wrote:
> Hi Mao,
>
> Mao Han 於 2019年8月20日 週二 下午4:57寫道：
> >
> > This patch add support for perf callchain sampling on riscv platform.
> > The return address of leaf function is retrieved from pt_regs as
> > it is not saved in the
Commit 34786005eca3 ("net: phy: prevent PHYs w/o Clause 22 regs from calling
genphy_config_aneg") introduced a check that aborts phy_config_aneg()
if the phy is a C45 phy.
This causes phy_state_machine() to call phy_error() so that the phy
ends up in PHY_HALTED state.
Instead of returning -EOPNOTS
On Tue, Aug 13, 2019 at 03:53:09PM +0530, Ashish Kumar wrote:
> There are 2 version of QSPI-IP, according to which controller registers sets
> can be big endian or little endian.There are some other minor changes like
> RX fifo depth etc.
>
> The big endian version uses driver compatible "fsl,ls1
On Tue, Aug 20, 2019 at 10:58:47AM -0700, Daniel Xu wrote:
> Hi Peter,
>
> On Tue Aug 20, 2019 at 4:45 PM Peter Zijlstra wrote:
> > On Fri, Aug 16, 2019 at 03:31:46PM -0700, Daniel Xu wrote:
> > > It's useful to know [uk]probe's nmissed and nhit stats. For example with
> > > tracing tools, it's im
On Tue, Aug 20, 2019 at 03:50:55PM +0200, Peter Zijlstra wrote:
> On Fri, Aug 16, 2019 at 10:12:02PM +0800, Peng Liu wrote:
> > Since sched_slice() is used in high frequency,
> > small change should also make sense.
>
> An actual Changelog would also make sense; but alas.
Thanks for your time!
A
On Wed, 21 Aug 2019, Tanwar, Rahul wrote:
> On 21/8/2019 4:34 PM, Thomas Gleixner wrote:
>
> > Secondly, this link is irrelevant. ioapic_dynirq_base has nothing to do
> > with virtual IRQ number 0. It's a boundary for the dynamic allocation of
> > virtual interrupt numbers so that the core allocat
On Mon, Aug 19, 2019 at 10:52:13AM +0200, Ingo Molnar wrote:
> * Mark Rutland wrote:
> > On Wed, Aug 14, 2019 at 01:26:43PM +0200, Geert Uytterhoeven wrote:
> > > On Wed, Aug 14, 2019 at 12:43 PM Mark Rutland
> > > wrote:
> > > > +static inline bool is_kthread(const struct task_struct *p)
> > >
On Tue, Aug 20, 2019 at 01:33:14PM -0500, Li Yang wrote:
> Some of the RTC hardware has the capability of address wrapping which
> means if you access a continuous address range across a certain
> boundary(could be the boundary of a regmap region) the hardware
> actually wrap the access to a lower
On 20/08/19 1:09 AM, Shirley Her (SC) wrote:
> Move functions in preparation to fix DLL lock phase shift issue
>
> Signed-off-by:Shirley Her
Please do not prefix the subject by "Subject: "
Please put a space after Signed-off-by:
> ---
> change in V7:
> 1. change subject to match the patch
> 2
On 20/08/19 1:08 AM, Shirley Her (SC) wrote:
> Change O2 Host PLL and DLL register name
>
> Signed-off-by:Shirley Her
Please do not prefix the subject by "Subject: "
Please put a space after Signed-off-by:
> ---
> change in v7:
> 1. change subject
>
> change in V6:
> 1. change subject and co
On 21/08/2019 12:21:42+0100, Mark Brown wrote:
> On Tue, Aug 20, 2019 at 01:33:14PM -0500, Li Yang wrote:
>
> > Some of the RTC hardware has the capability of address wrapping which
> > means if you access a continuous address range across a certain
> > boundary(could be the boundary of a regmap r
On 20/08/19 1:11 AM, Shirley Her (SC) wrote:
> Fix data read/write error in HS200 mode due to chip DLL lock phase shift
>
> Signed-off-by:Shirley Her
Please do not prefix the subject by "Subject: "
Please put a space after Signed-off-by:
> ---
> change in V7:
> 1. change subject
> 2. change t
Hi Jonathan, Jacopo,
On Mon, Aug 5, 2019 at 7:15 PM Jonathan Cameron wrote:
> On Mon, 5 Aug 2019 17:55:15 +0200
> Jacopo Mondi wrote:
>
> > The max9611 driver reads the die temperature at probe time to validate
> > the communication channel. Use the actual read value to perform the test
> > ins
On Wed, Aug 21, 2019 at 10:13 AM Marc Zyngier wrote:
> Linus: do you want to take this patch (daa19fe5b082) through your tree
> instead in order to avoid the conflict when this hit the other Linus?
> It shouldn't create any havoc...
Is it completely independent from the rest? Then I will pick it
On Wed, Aug 21, 2019 at 01:24:13PM +0200, Alexandre Belloni wrote:
> On 21/08/2019 12:21:42+0100, Mark Brown wrote:
> > On Tue, Aug 20, 2019 at 01:33:14PM -0500, Li Yang wrote:
> > > violation check of regmap rejects such access. According to
> > > Alexcandre, the address wrapping is essential to
On Mon, Aug 19, 2019 at 04:31:46PM +0200, Thomas Gleixner wrote:
> Warning when p == NULL and then proceeding and dereferencing p does not
> make any sense as the kernel will crash with a NULL pointer dereference
> right away.
>
> Bailing out when p == NULL and returning an error code does not cur
On Wed, Aug 21, 2019 at 09:56:40AM +, Jisheng Zhang wrote:
> The common kprobes provides a weak implementation of
> arch_kprobe_on_func_entry(). The parisc version is the same as the
> common version, so remove it.
>
> Signed-off-by: Jisheng Zhang
Acked-by: Sven Schnelle
> ---
> arch/pari
On Mon, Aug 19, 2019 at 04:31:47PM +0200, Thomas Gleixner wrote:
> It's always current. Don't give people wrong ideas.
>
> Signed-off-by: Thomas Gleixner
Reviewed-by: Frederic Weisbecker
On 20.08.19 16:22, Pali Rohár wrote:
Hi,
In that case, wouldn't a comment be more suitable for that ?
And why to add comment if current state of code is more-readable and
does not need it?
Readability is probably a bit subjective :p
With ongoing efforts of automatically identifying redunda
* Adam Ford [190819 19:26]:
> On Sat, Aug 17, 2019 at 2:03 AM Tony Lindgren wrote:
> >
> > * Adam Ford [190816 23:02]:
> > > On Wed, Aug 14, 2019 at 8:16 AM Tony Lindgren wrote:
> > > > Well I just posted some sgx interconnect target module patches. We might
> > > > still have them in v5.4 assu
Hi Wenwen,
On 18/08/2019 06:58, Wenwen Wang wrote:
> In fdp1_open(), 'ctx' is allocated through kzalloc(). However, it is not
> deallocated if v4l2_ctrl_new_std() fails, leading to a memory leak bug. To
> fix this issue, free 'ctx' before going to the 'done' label.
We could also free it up in the
On 21/08/2019 12:30:29+0100, Mark Brown wrote:
> On Wed, Aug 21, 2019 at 01:24:13PM +0200, Alexandre Belloni wrote:
> > On 21/08/2019 12:21:42+0100, Mark Brown wrote:
> > > On Tue, Aug 20, 2019 at 01:33:14PM -0500, Li Yang wrote:
>
> > > > violation check of regmap rejects such access. According
Replace the VPU-centric power domain controller by the generic system-wide
Everything-Else power domain controller and setup the right power-domains
properties on the VPU, Ethernet & USB nodes.
Signed-off-by: Neil Armstrong
---
.../boot/dts/amlogic/meson-g12-common.dtsi| 92 ++---
Add the bindings for the Amlogic Everything-Else power domains,
controlling the Everything-Else peripherals power domains.
The bindings targets the Amlogic G12A and SM1 compatible SoCs,
support for earlier SoCs will be added later.
Signed-off-by: Neil Armstrong
---
.../bindings/power/amlogic,me
Update compatible of the pwc-vpu node and add the HDMI support nodes
for the Amlogic SM1 Based SEI610 Board.
Signed-off-by: Neil Armstrong
---
.../boot/dts/amlogic/meson-sm1-sei610.dts | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-
Add the USB properties for the Amlogic SM1 Based SEI610 Board in order to
support the USB DRD Type-C port and the USB3 Type A port.
The USB DRD Type-C controller uses the ID signal to toggle the USB role
between the DWC3 Host controller and the DWC2 Device controller.
Signed-off-by: Neil Armstron
Add support for the General Purpose Amlogic Everything-Else Power controller,
with the first support for G12A and SM1 SoCs dedicated to the VPU, PCIe,
USB, NNA, GE2D and Ethernet Power Domains.
Signed-off-by: Neil Armstrong
---
drivers/soc/amlogic/Kconfig | 11 +
drivers/soc/amlogic/Mak
This patchset introduces a new "Everything-Else Power Domain Controller"
designed to handle all the different non-Always On peripherals like :
- VPU
- Ethernet Memories
- USB, PCIe, Audio, NNA on SM1
The current "gx-vpu-pwrc" process has been integrated to support the VPU
and the other power domai
On Wed, 21 Aug 2019 at 13:21, Adrian Hunter wrote:
>
> On 20/08/19 1:08 AM, Shirley Her (SC) wrote:
> > Change O2 Host PLL and DLL register name
> >
> > Signed-off-by:Shirley Her
>
> Please do not prefix the subject by "Subject: "
> Please put a space after Signed-off-by:
Also, I recommend to ru
IEEE 802.3ae clause 45 defines a modified MDIO protocol that uses a two
staged access model in order to increase the address space.
This patch adds support for C45 MDIO read and write accesses, which are
used whenever the MII_ADDR_C45 flag in the regnum argument is set.
In case it is not set, C22
On 20.08.19 04:08, Andy Duan wrote:
> From: Marco Hartmann Sent: Tuesday, August 20, 2019 1:11 AM
>> IEEE 802.3ae clause 45 defines a modified MDIO protocol that uses a two
>> staged access model in order to increase the address space.
>>
>> This patch adds support for C45 MDIO read and write acces
On Wed, Aug 21, 2019 at 01:38:56PM +0200, Alexandre Belloni wrote:
> On 21/08/2019 12:30:29+0100, Mark Brown wrote:
> > What's the mechanism here? It's a very strange thing to require.
> The clock control is on the first register, then you have sec, min,
> hour, day, mon, year.
> To be able to
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