On 2019-08-21 08:44:22 [+0200], Juri Lelli wrote:
> > Hi Juri, currently if the mail subject has RFC, we will test it but send
> > report
> > privately to author only.
>
> OK. But, my email had "RT" and not "RFC" in the subject (since it is
> meant for one of the PREEMPT_RT stable trees [1]).
Wa
On Wed, Aug 21, 2019 at 8:16 AM Stephen Rothwell wrote:
> After merging the pinctrl tree, today's linux-next build (arm
> multi_v7_defconfig) failed like this:
>
> drivers/pinctrl/pinctrl-st.c: In function 'st_pctl_dt_parse_groups':
> drivers/pinctrl/pinctrl-st.c:1212:15: error: implicit declarat
These are not real targets. Adding them to PHONY is preferred.
Signed-off-by: Masahiro Yamada
---
scripts/package/Makefile | 29 -
1 file changed, 20 insertions(+), 9 deletions(-)
diff --git a/scripts/package/Makefile b/scripts/package/Makefile
index a2d8830f54be..4
This '+' was added a long time ago:
|commit c23e6bf05f7802e92fd3da69a1ed35e56f9c85bb (HEAD)
|Author: Kai Germaschewski
|Date: Mon Oct 28 01:16:34 2002 -0600
|
|kbuild: Fix a "make -j" warning
|
|diff --git a/scripts/Makefile.clean b/scripts/Makefile.clean
|index 2c843e0380bc..e7c392fd5788 1
I am not a big fan of the $(objtree)/ hack for clean-files/clean-dirs.
These are created in the top of $(objtree), so let's clean them up
from the top Makefile.
Signed-off-by: Masahiro Yamada
---
Makefile | 6 --
scripts/Makefile | 2 +-
scripts/package/Makefile | 9
This line contains $(MAKE), so Make knows that it will invoke sub-make
without help of the '+' marker.
Signed-off-by: Masahiro Yamada
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index ec2a6b85a0fa..c0be1a4dbfdd 100644
--- a/Makefile
+++ b
On Tue, Aug 20, 2019 at 04:51:21PM +0530, Mamatha Inamdar wrote:
SNIP
> #ifdef HAVE_ZSTD_SUPPORT
> static int perf_session__process_compressed_event(struct perf_session
> *session,
> @@ -183,6 +184,7 @@ static int ordered_events__deliver_event(struct
> ordered_events *oe,
> struct perf_sessi
There is a new product which reuses Lantiq serial controller IP. Patch 1 in this
series converts existing lantiq dt bindings to YAML schema and Patch 2 updates
it to support newer product.
These patches are baselined upon Linux 5.3-rc4 at below Git tree:
git://git.kernel.org/pub/scm/linux/kernel/g
These structs have holes in them so we end up disclosing a few bytes of
uninitialized stack data.
drivers/misc/xilinx_sdfec.c:305 xsdfec_get_status() warn: check that 'status'
doesn't leak information (struct has a hole after 'activity')
drivers/misc/xilinx_sdfec.c:449 xsdfec_get_turbo() warn: ch
Intel Lightning Mountain(LGM) reuses Lantiq ASC serial controller IP.
Update the dt bindings to support LGM as well.
Signed-off-by: Rahul Tanwar
---
.../devicetree/bindings/serial/lantiq,asc.yaml | 35 ++
1 file changed, 35 insertions(+)
diff --git a/Documentation/device
Convert the existing DT binding document for Lantiq SoC ASC serial controller
from txt format to YAML format.
Signed-off-by: Rahul Tanwar
---
.../devicetree/bindings/serial/lantiq,asc.yaml | 55 ++
.../devicetree/bindings/serial/lantiq_asc.txt | 31
2 fi
The copy_from_user() funciton returns the number of bytes remaining to
be copied but we want to return -EFAULT to the user.
Fixes: 20ec628e8007 ("misc: xilinx_sdfec: Add ability to configure LDPC")
Signed-off-by: Dan Carpenter
---
drivers/misc/xilinx_sdfec.c | 5 +++--
1 file changed, 3 insertio
The "psize" value comes from the user so we need to verify that it's
non-zero before we check if "n % psize" or it will crash.
Fixes: 20ec628e8007 ("misc: xilinx_sdfec: Add ability to configure LDPC")
Signed-off-by: Dan Carpenter
---
The parentheses in this condition are a no-op. They're just co
The checking here needs to handle integer overflows because "offset" and
"len" come from the user.
Fixes: 20ec628e8007 ("misc: xilinx_sdfec: Add ability to configure LDPC")
Signed-off-by: Dan Carpenter
---
drivers/misc/xilinx_sdfec.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
On Tue, Aug 20, 2019 at 09:14:41PM -0700, Troy Benjegerdes wrote:
>
>
> > On Aug 13, 2019, at 8:47 AM, Christoph Hellwig wrote:
> >
> > No point in bloating the kernel image with a bootloader header if
> > we run bare metal.
>
> I would say the same for S-mode. EFI booting should be an option,
The isst_send_msr_command() function will read 8 bytes but we are
passing an address to an int (4 bytes) so it results in a read overflow.
Fixes: 3fb4f7cd472c ("tools/power/x86: A tool to validate Intel Speed Select
commands")
Signed-off-by: Dan Carpenter
---
tools/power/x86/intel-speed-select/
Michael Kelley writes:
> From: Vitaly Kuznetsov Sent: Tuesday, August 13, 2019
> 1:34 AM
>>
>> Michael Kelley writes:
>>
>> > From: Tianyu Lan Sent: Tuesday, July 30, 2019
>> > 6:41 AM
>> >>
>> >> On Mon, Jul 29, 2019 at 8:13 PM Vitaly Kuznetsov
>> >> wrote:
>> >> >
>> >> > Peter Zijlstr
On Wed, 21 Aug 2019 at 13:41, Naoya Horiguchi wrote:
>
> On Tue, Aug 20, 2019 at 03:03:55PM +0800, Wanpeng Li wrote:
> > Cc Mel Gorman, Kirill, Dave Hansen,
> > On Tue, 11 Jun 2019 at 07:51, Naoya Horiguchi
> > wrote:
> > >
> > > On Wed, May 29, 2019 at 04:31:01PM -0700, Mike Kravetz wrote:
> >
On Wed, Aug 21, 2019 at 09:22:48AM +0530, Anup Patel wrote:
> I agree that IPI mechanism should be standardized for RISC-V but I
> don't support the idea of mandating CLINT as part of the UNIX
> platform spec. For example, the AndesTech SOC does not use CLINT
> instead they have PLMT for per-HART t
On Wed, 21 Aug 2019, Michal Hocko wrote:
> > vm.oom_dump_tasks is pretty useful, however, so it's curious why you
> > haven't left it enabled :/
>
> Because it generates a lot of output potentially. Think of a workload
> with too many tasks which is not uncommon.
Probably better to always print
Hi all,
Today's linux-next merge of the akpm-current tree got a conflict in:
arch/arm/Kconfig
between commit:
936376f88ff1 ("arm: select the dma-noncoherent symbols for all swiotlb
builds")
from the dma-mapping tree and commit:
83286f0dcb91 ("arm: use generic mmap top-down layout and b
On Tue, Aug 20, 2019 at 09:17:17AM -0500, Bjorn Helgaas wrote:
> On Tue, Aug 20, 2019 at 12:58:20PM +0300, Mika Westerberg wrote:
> > On Mon, Aug 19, 2019 at 06:52:45PM -0500, Bjorn Helgaas wrote:
> > > > Right, it looks like we need some sort of flag there anyway.
> > >
> > > Does this mean you'r
Miquel,
On 08/16/2019 01:55 AM, thor.tha...@linux.intel.com wrote:
> External E-Mail
>
>
> From: Thor Thayer
>
> The current Cadence QSPI driver sometimes caused a
> "rcu_sched self-detected stall" while writing large files.
>
> Stall Report:
> '# mtd_debug write /dev/mtd1 0 48816464 blob.img
On Wed, Aug 21, 2019 at 12:47 AM Kristian Klausen wrote:
>
> On 20.08.2019 23.38, Rafael J. Wysocki wrote:
> > On Tuesday, August 20, 2019 3:29:48 PM CEST Rafael J. Wysocki wrote:
> >> On Tue, Aug 20, 2019 at 3:10 PM Kristian Klausen
> >> wrote:
> >>> On 19.08.2019 22.41, Rafael J. Wysocki wrote
Commit 0505d00c8dba ("soc/fsl/qbman: Cleanup buffer pools if BMan was
initialized prior to bootup") defined a new variable to store the return
error, but forgot to return this value at the end of the function.
Fixes: 0505d00c8dba ("soc/fsl/qbman: Cleanup buffer pools if BMan was
initialized prior
On Wed 21-08-19 00:19:37, David Rientjes wrote:
> On Wed, 21 Aug 2019, Michal Hocko wrote:
>
> > > vm.oom_dump_tasks is pretty useful, however, so it's curious why you
> > > haven't left it enabled :/
> >
> > Because it generates a lot of output potentially. Think of a workload
> > with too many
>>>Subject: Re: [PATCH 0/3] fix interrupt swamp in NVMe
>>>
>>>On 20/08/2019 09:25, Ming Lei wrote:
On Tue, Aug 20, 2019 at 2:14 PM wrote:
>
> From: Long Li
>
> This patch set tries to fix interrupt swamp in NVMe devices.
>
> On large systems with many CPUs, a number
On Tue, 20 Aug 2019 at 23:38, Sylwester Nawrocki wrote:
>
> On 8/20/19 21:37, Krzysztof Kozlowski wrote:
> >>> diff --git a/drivers/soc/samsung/exynos-chipid.c
> >>> b/drivers/soc/samsung/exynos-chipid.c
>
> >>> @@ -51,29 +48,24 @@ static const char * __init
> >>> product_id_to_soc_id(unsigned i
This patch inlines bitmap_weight() call. Thus, removing the BUG_ON,
and 'longs to bits -> bits to longs' conversion by directly calling
hweight_long().
./scripts/bloat-o-meter lib/memweight.o.old lib/memweight.o.new
add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-10 (-10)
Function
From: Ding Xiang
In the error path of stm_source_register_device(), the kfree is
unnecessary, as the put_device() before it ends up calling
stm_source_device_release() to free stm_source_device, leading to
a double free at the outer kfree() call. Remove it.
Signed-off-by: Ding Xiang
Signed-off-
From: Nishad Kamdar
This patch corrects the SPDX License Identifier style
in header files related to Drivers for Intel(R) Trace Hub
controller.
For C header files Documentation/process/license-rules.rst
mandates C-like comments (opposed to C source files where
C++ style should be used)
Changes m
This adds support for the Trace Hub in Tiger Lake PCH.
Signed-off-by: Alexander Shishkin
Cc: sta...@vger.kernel.org # v4.14+
---
drivers/hwtracing/intel_th/pci.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/hwtracing/intel_th/pci.c b/drivers/hwtracing/intel_th/pci.c
index 5c4
Hi Greg,
These are the fixes that I have for v5.3. One is an actual bugfix that's
copied to stable, one SPDX header fix and two new PCI IDs, copied to
stable as well. Signed tag below, individual patches follow. Please
consider applying or pulling. Thanks!
Alexander Shishkin (2):
intel_th: pci:
On Fri, 16 Aug 2019 at 18:30, Krzysztof Kozlowski wrote:
>
> The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
>
> Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
>
> are available in the Git repository at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
Add support for the Trace Hub in another Lewisburg PCH.
Signed-off-by: Alexander Shishkin
Cc: sta...@vger.kernel.org # v4.14+
---
drivers/hwtracing/intel_th/pci.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/hwtracing/intel_th/pci.c b/drivers/hwtracing/intel_th/pci.c
index c0
On Fri, 16 Aug 2019 at 18:30, Krzysztof Kozlowski wrote:
>
> The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
>
> Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
>
> are available in the Git repository at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
On Fri, 16 Aug 2019 at 18:30, Krzysztof Kozlowski wrote:
>
> The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
>
> Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
>
> are available in the Git repository at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
Hi Georgi,
Thanks for the review!
On 8/20/19 12:34 PM, Georgi Djakov wrote:
> Hi Stan,
>
> On 8/14/19 11:47, Stanimir Varbanov wrote:
>> This aims to add a requests for bandwidth scaling depending
>> on the resolution and framerate (macroblocks per second). The
>> exact value ff the requested ba
On 20/08/19 09:16, Wanpeng Li wrote:
> Kindly reminder, :)
It's already in my pull request from yesterday.
Palo
> On Mon, 15 Jul 2019 at 17:16, Paolo Bonzini wrote:
>>
>> On 15/07/19 03:28, Wanpeng Li wrote:
>>> From: Wanpeng Li
>>>
>>> Allow guest reads CORE cstate when exposing host CPU powe
On Tue, 2019-08-13 at 00:43 +, James Nylen wrote:
> > I suppose we could consider applying a workaround like this if it has a
> > condition checking that the buffer passed in is the maximum possible
> > buffer (65535 bytes, due to iw_point::length being u16)
>
> This is what the latest patch d
From: Rafael J. Wysocki
Commit 10a08fd65ec1 ("ACPI: PM: Set up EC GPE for system wakeup from
drivers that need it") assumed that the EC GPE would only need to be
set up for system wakeup if either the intel-hid or the intel-vbtn
driver was in use, but that turns out to be incorrect. In particula
On Tue, Aug 20, 2019 at 06:56:56PM +0200, Hubert Feurstein wrote:
> Am Di., 20. Aug. 2019 um 17:40 Uhr schrieb Miroslav Lichvar
> > I think a large jitter is ok in this case. We just need to timestamp
> > something that we know for sure happened after the PHC timestamp. It
> > should have no impact
On Tue, Aug 20, 2019 at 06:59:39PM -0700, Matthew Wilcox wrote:
>On Wed, Aug 21, 2019 at 09:22:44AM +0800, Wei Yang wrote:
>> On Tue, Aug 20, 2019 at 05:54:17PM -0700, Matthew Wilcox wrote:
>> >On Wed, Aug 21, 2019 at 08:52:34AM +0800, Wei Yang wrote:
>> >> On Tue, Aug 20, 2019 at 10:26:29AM -0700,
On Wed, 21 Aug 2019 07:03:35 +0100,
Stephen Rothwell wrote:
Hi Stephen,
>
> Hi all,
>
> Today's linux-next merge of the gpio tree got a conflict in:
>
> drivers/gpio/gpio-ixp4xx.c
>
> between commit:
>
> daa19fe5b082 ("gpio/ixp4xx: Register the base PA instead of its VA in
> fwnode")
>
'ioapic_dynirq_base' contains the virtual IRQ base number. Presently, it is
updated to the end of hardware IRQ numbers but this is done only when IOAPIC
configuration type is IOAPIC_DOMAIN_LEGACY or IOAPIC_DOMAIN_STRICT. There is
a third type IOAPIC_DOMAIN_DYNAMIC which applies when IOAPIC configur
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/bus/moxtet.c: In function moxtet_remove:
drivers/bus/moxtet.c:822:6: warning: variable dummy set but not used
[-Wunused-but-set-variable]
Signed-off-by: Jason Yan
---
drivers/bus/moxtet.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions
Hi,
> From: Jian-Hong Pan [mailto:jian-h...@endlessm.com]
>
> There is a mass of jobs between spin lock and unlock in the hardware
> IRQ which will occupy much time originally. To make system work more
> efficiently, this patch moves the jobs to the soft IRQ (bottom half) to
> reduce the time in
>>>Subject: Re: [PATCH 1/3] sched: define a function to report the number of
>>>context switches on a CPU
>>>
>>>On Mon, Aug 19, 2019 at 11:14:27PM -0700, lon...@linuxonhyperv.com
>>>wrote:
From: Long Li
The number of context switches on a CPU is useful to determine how
busy th
On 08/16/2019 01:55 AM, thor.tha...@linux.intel.com wrote:
> External E-Mail
>
>
> From: Thor Thayer
>
> The current Cadence QSPI driver sometimes caused a
> "rcu_sched self-detected stall" while writing large files.
>
> Stall Report:
> '# mtd_debug write /dev/mtd1 0 48816464 blob.img
> [ 18
On 08/19/2019 08:16 PM, Wenwen Wang wrote:
> External E-Mail
>
>
> In spi_nor_parse_4bait(), 'dwords' is allocated through kmalloc(). However,
> it is not deallocated in the following execution if spi_nor_read_sfdp()
> fails, leading to a memory leak. To fix this issue, free 'dwords' before
> r
Patches 1 and 2 are the same as the previous patch, but using
svm_get_supported_cpuid and with a fix to the placement of cpuid_mask.
Patch 3 is new and, unlike the previous one, will only be in kvm/next.
Paolo Bonzini (3):
KVM: x86: fix reporting of AMD speculation bug CPUID leaf
KVM: x86: al
The AMD_* bits have to be set from the vendor-independent
feature and bug flags, because KVM_GET_SUPPORTED_CPUID does not care
about the vendor and they should be set on Intel processors as well.
On top of this, SSBD, STIBP and AMD_SSB_NO bit were not set, and
VIRT_SSBD does not have to be added ma
Sorry, I cannot understand this problem accurately. I try to understand it and
I guess what you want
to express is that the return value type should be cputime64_t but not u64,
just like as follows:
+static cputime64_t cpustat_curr_cputime(int cpu, int index)
+{
+ cputime64_t time;
+
+
Even though it is preferrable to use SPEC_CTRL (represented by
X86_FEATURE_AMD_SSBD) instead of VIRT_SPEC, VIRT_SPEC is always
supported anyway because otherwise it would be impossible to
migrate from old to new CPUs. Make this apparent in the
result of KVM_GET_SUPPORTED_CPUID as well.
While at i
Similar to AMD bits, set the Intel bits from the vendor-independent
feature and bug flags, because KVM_GET_SUPPORTED_CPUID does not care
about the vendor and they should be set on AMD processors as well.
Suggested-by: Jim Mattson
Signed-off-by: Paolo Bonzini
---
arch/x86/kvm/cpuid.c | 6 ++
On Tue, Aug 20, 2019 at 10:55 PM Vinod Koul wrote:
>
> This add base DTS file for sm8150-mtp and enables boot to console, adds
> tlmm reserved range, resin node, volume down key and also includes pmic
> file.
For some reason, your mailer sent out 2 patches 5/8. I was wondering
why the patch 5 fai
On 20.08.19 18:01, Nadav Amit wrote:
> The compaction code already marks pages as offline when it enqueues
> pages in the ballooned page list, and removes the mapping when the pages
> are removed from the list. VMware balloon also updates the flags,
> instead of letting the balloon-compaction logic
Naveen N. Rao wrote:
Since BPF constant blinding is performed after the verifier pass, there
are certain ALU32 instructions inserted which don't have a corresponding
zext instruction inserted after. This is causing a kernel oops on
powerpc and can be reproduced by running 'test_cgroup_storage' wi
From: Olga Albisser
DualPI2 provides L4S-type low latency & loss to traffic that uses a
scalable congestion controller (e.g. TCP-Prague, DCTCP) without
degrading the performance of 'classic' traffic (e.g. Reno,
Cubic etc.). It is intended to be the reference implementation of the
IETF's DualQ Cou
Add calculations to determine a time range that encompasses all data.
Signed-off-by: Adrian Hunter
---
.../scripts/python/exported-sql-viewer.py | 113 +-
1 file changed, 109 insertions(+), 4 deletions(-)
diff --git a/tools/perf/scripts/python/exported-sql-viewer.py
b/tools
Add ability for Call tree to open at a specified task and time.
Signed-off-by: Adrian Hunter
---
.../scripts/python/exported-sql-viewer.py | 44 ++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/tools/perf/scripts/python/exported-sql-viewer.py
b/tools/perf/sc
Hi
These patches to exported-sql-viewer.py, add a time chart based on context
switch information. Context switch information was added to the database
export fairly recently, so the chart menu option will only appear if
context switch information is in the database. Refer to the Exported SQL
Vie
Record call_time on tree nodes and re-name the misnamed "count" parameter.
Signed-off-by: Adrian Hunter
---
tools/perf/scripts/python/exported-sql-viewer.py | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/tools/perf/scripts/python/exported-sql-viewer.py
b/too
Add a time chart based on context switch information. Context switch
information was added to the database export fairly recently, so the chart
menu option will only appear if context switch information is in the
database. Refer to the Exported SQL Viewer Help option for more
information about the
Add LookupModel() to find a model in the model cache without creating it.
Signed-off-by: Adrian Hunter
---
tools/perf/scripts/python/exported-sql-viewer.py | 9 +
1 file changed, 9 insertions(+)
diff --git a/tools/perf/scripts/python/exported-sql-viewer.py
b/tools/perf/scripts/python/e
Add layout classes HBoxLayout and VBoxLayout.
Signed-off-by: Adrian Hunter
---
.../scripts/python/exported-sql-viewer.py | 41 ++-
1 file changed, 31 insertions(+), 10 deletions(-)
diff --git a/tools/perf/scripts/python/exported-sql-viewer.py
b/tools/perf/scripts/python/exp
On Wed, 21 Aug 2019, Rahul Tanwar wrote:
> 'ioapic_dynirq_base' contains the virtual IRQ base number. Presently, it is
> updated to the end of hardware IRQ numbers but this is done only when IOAPIC
> configuration type is IOAPIC_DOMAIN_LEGACY or IOAPIC_DOMAIN_STRICT. There is
> a third type IOAPIC
On 21. 08. 19 4:10, Phil Reid wrote:
> On 20/08/2019 22:11, Michal Simek wrote:
>> On systems with multiple ina2xx chips it is impossible to find out which
>> iio device is which one based on probe order. That's why it is
>> necessary to
>> setup better name based on possition.
>> The patch is reus
There is no need to handle optional module request in the driver
when user space tools has that feature for ages.
Replace custom code by MODULE_SOFTDEP() macro to let user space know
that we would like to have the DMA driver loaded first, if any.
Signed-off-by: Andy Shevchenko
---
drivers/mfd/i
>>>Subject: Re: [PATCH 3/3] nvme: complete request in work queue on CPU
>>>with flooded interrupts
>>>
>>>On Mon, Aug 19, 2019 at 11:14:29PM -0700, lon...@linuxonhyperv.com
>>>wrote:
From: Long Li
When a NVMe hardware queue is mapped to several CPU queues, it is
possible that t
>>>Subject: Re: [PATCH 3/3] nvme: complete request in work queue on CPU
>>>with flooded interrupts
>>>
>>>
From: Long Li
When a NVMe hardware queue is mapped to several CPU queues, it is
possible that the CPU this hardware queue is bound to is flooded by
returning I/O for
On Tue, Aug 20, 2019 at 10:55 PM Vinod Koul wrote:
>
> Add hwlock, pmu, smem, tcsr_mutex_regs, apss_shared mailbox, apps_rsc
> including the rpmhcc child nodes to the SM8150 DTSI
>
> Co-developed-by: Sibi Sankar
> Signed-off-by: Sibi Sankar
> Signed-off-by: Vinod Koul
> ---
> arch/arm64/boot/d
Hi all,
Changes since 20190820:
The security tree gained conflicts against Linus' tree.
The integrity tree gained a conflict against the security tree.
The iommu tree gained a conflict against the drm-misc tree.
The irqchip tree gained a conflict against the pci tree.
The gpio tree gained a c
+++ zhe...@windriver.com [20/08/19 22:53 +0800]:
From: He Zhe
We should keep the case of "#define debug_align(X) (X)" for all arches
without CONFIG_HAS_STRICT_MODULE_RWX ability, which would save people, who
are sensitive to system size, a lot of memory when using modules,
especially for embedd
Vitaly Kuznetsov writes:
> Michael Kelley writes:
>
>> I talked to KY Srinivasan for any history about TSC page on 32-bit. He said
>> there was no technical reason not to implement it, but our focus was always
>> 64-bit Linux, so the 32-bit was much less important. Also, on 32-bit Linux,
>> th
Hi lpfc experts,
We observed these warnings during the mainline kernel-v5.3.0-rc4
testing. There is no explicit reproducer so far, if you need some more
information, plz let me know.
Test system has this device: OneConnect 10Gb FCoE Initiator (be3)
[ 211.080240] lpfc :47:00.3: 1:2505 EQ_DES
On Wed, Aug 21, 2019 at 07:19:39AM +1000, Stephen Rothwell wrote:
> Hi all,
>
> Commit
>
> c4a29fbba415 ("PCI: hv: Use bytes 4 and 5 from instance ID as the PCI
> domain numbers")
>
> is missing a Signed-off-by from its committer.
>
> Also, all the tags should be kept together, please.
Fixe
Hi Krzysztof,
On 7/24/19 1:39 PM, Krzysztof Kozlowski wrote:
> On Mon, 22 Jul 2019 at 11:47, Lukasz Luba wrote:
>>
>> The patch adds AC timings information needed to support LPDDR3 and memory
>> controllers. The structure is used in of_memory and currently in Exynos
>> 5422 DMC. Add parsing data
Naveen N. Rao writes:
> Naveen N. Rao wrote:
>> Since BPF constant blinding is performed after the verifier pass, there
>> are certain ALU32 instructions inserted which don't have a corresponding
>> zext instruction inserted after. This is causing a kernel oops on
>> powerpc and can be reproduce
On Tue, Aug 20, 2019 at 10:53:42PM +0530, Vinod Koul wrote:
> This series adds DTS for SM8150, PMIC PM8150, PM8150B, PM8150L and
> the MTP for SM8150.
>
> Changes in v3:
> - Fix copyright comment style to Linux kernel style
> - Make property values all hex or decimal
> - Fix patch titles and lo
Add Amit Kucheria as the reviewer for thermal as he would like to
participate in the review process effort for the thermal framework.
Signed-off-by: Amit Kucheria
---
Hi thermal maintainers, I'd like to help out with reviewing patches to the
thermal framework. I respectfully submit this patch for
On 05-08-19, 19:55, Pierre-Louis Bossart wrote:
> This series provides an update on the initial RFC. Debugfs and Intel
> updates will be provided in follow-up patches. The order of patches
> was changed since the RFC so detailed change logs are provided below.
Applied all except 14, which didnt ap
On 09-08-19, 14:34, Srinivas Kandagatla wrote:
> This patch adds bindings for Soundwire Slave devices that includes how
> SoundWire enumeration address and Link ID are used to represented in
> SoundWire slave device tree nodes.
Rob does this look good to you, I intent to apply the soundwire parts
On some Qualcomm SoCs, Operating State Manager (OSM) controls the
resources of scaling L3 caches. Add a driver to handle bandwidth
requests to OSM L3 from CPU/GPU.
Signed-off-by: Sibi Sankar
---
drivers/interconnect/qcom/Kconfig | 7 +
drivers/interconnect/qcom/Makefile | 2 +
drivers/inter
This patch series aims to add Operating State Manager (OSM) L3
interconnect provider support on SDM845 SoCs to handle bandwidth
requests from CPU to scale L3 caches.
v2:
* addressed review comments from Evan
* dropped unused gpu icc node on SDM845 SoC
Sibi Sankar (2):
dt-bindings: interconnec
Add bindings for Operating State Manager (OSM) L3 interconnect provider
on SDM845 SoCs.
Signed-off-by: Sibi Sankar
---
.../bindings/interconnect/qcom,osm-l3.yaml| 56 +++
.../dt-bindings/interconnect/qcom,osm-l3.h| 12
2 files changed, 68 insertions(+)
create mode 1
Use the standard obj-y form to specify the sub-directories under
arch/arm64/. No functional change intended.
Signed-off-by: Masahiro Yamada
---
arch/arm64/Kbuild | 6 ++
arch/arm64/Makefile | 6 +-
2 files changed, 7 insertions(+), 5 deletions(-)
create mode 100644 arch/arm64/Kbuild
On 21. 08. 19 4:11, Phil Reid wrote:
> On 20/08/2019 22:11, Michal Simek wrote:
>> Add support for using label property for easier device identification via
>> iio framework.
>>
>> Signed-off-by: Michal Simek
>> ---
>>
>> drivers/iio/adc/ina2xx-adc.c | 2 +-
>> 1 file changed, 1 insertion(+), 1
Hi Dmitry
On 2019/08/17 2:12, Dmitry Torokhov wrote:
Hi Jiada,
On Fri, Aug 16, 2019 at 05:28:50PM +0900, Jiada Wang wrote:
input_mt_report_slot_state() ignores the tool when the slot is closed.
which has caused a bit of confusion.
This patch introduces input_mt_report_slot_inactive() to report
On Wed, Aug 21, 2019 at 03:21:18PM +0800, zhangfei@foxmail.com wrote:
> Hi, Greg
>
> On 2019/8/21 上午12:59, Greg Kroah-Hartman wrote:
> > On Tue, Aug 20, 2019 at 09:08:55PM +0800, zhangfei wrote:
> > >
> > > On 2019/8/15 下午10:13, Greg Kroah-Hartman wrote:
> > > > On Wed, Aug 14, 2019 at 05:34:
Hi Mao,
Mao Han 於 2019年8月20日 週二 下午4:57寫道：
>
> This patch add support for perf callchain sampling on riscv platform.
> The return address of leaf function is retrieved from pt_regs as
> it is not saved in the outmost frame.
>
> Signed-off-by: Mao Han
> Cc: Paul Walmsley
> Cc: Greentime Hu
> Cc:
Hi Krzysztof,
On 7/24/19 1:31 PM, Krzysztof Kozlowski wrote:
> On Mon, 22 Jul 2019 at 11:47, Lukasz Luba wrote:
>>
>> The patch adds AC timings information needed to support LPDDR3 and memory
>> controllers. The structure is used in of_memory and currently in Exynos
>> 5422 DMC. Add parsing data
On Wed, 14 Aug 2019 at 08:09, wrote:
>
> From: Jernej Skrabec
>
> I2S doesn't work if parent rate couldn't be change. Difference between
> wanted and actual rate is too big.
>
> Fix this by adding CLK_SET_RATE_PARENT flag to I2S clocks.
>
> Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Co
On Tue, Aug 20, 2019 at 10:40:54PM +0100, Yu-cheng Yu wrote:
> On Tue, 2019-08-20 at 10:57 +0100, Dave Martin wrote:
> > ELF program properties will needed for detecting whether to enable
> > optional architecture or ABI features for a new ELF process.
> >
> > For now, there are no generic propert
>
> Talking about packet numbers, can you describe how PN exhaustion is
> handled? I couldn't find much about packet numbers at all in the
> driver patches (I hope the hw doesn't wrap around from 2^32-1 to 0 on
> the same SA). At some point userspace needs to know that we're
> getting close to
On Wed, Aug 21, 2019 at 10:06:09AM +0200, Rafael J. Wysocki wrote:
> From: Rafael J. Wysocki
>
> Commit 10a08fd65ec1 ("ACPI: PM: Set up EC GPE for system wakeup from
> drivers that need it") assumed that the EC GPE would only need to be
> set up for system wakeup if either the intel-hid or the in
在 2019-08-20二的 15:58 +0200，Maxime Ripard写道：
> On Fri, Aug 16, 2019 at 04:00:16PM +0200, Corentin Labbe wrote:
> > On Fri, Aug 16, 2019 at 03:52:06PM +0200, Maxime Ripard wrote:
> > > On Fri, Aug 16, 2019 at 01:57:50PM +0200, Corentin Labbe wrote:
> > > > On Fri, Aug 16, 2019 at 01:36:50PM +0200, Ma
Hi,
I can add some information to the HW Antoine is working on, general design of it
and the thoughts behind it. See below.
The 08/20/2019 16:41, Sabrina Dubroca wrote:
> 2019-08-20, 12:01:40 +0200, Antoine Tenart wrote:
> > So it seems the ability to enable or disable the offloading on a given
>
migration_base is used as a placeholder when an hrtimer is switching
between base (see switch_hrtimer_timer_base). It is possible
theoritically possible to have timer->base equal to migration_base.
Even if it is a placeholder, it would pass all the current check in
hrtimer_grab_expiry_lock() leadi
The update to timer->base is protected by the base->cpu_base->lock().
However, hrtimer_grab_expirty_lock() does not access it with the lock.
So it would theorically be possible to have timer->base changed under
our feet. We need to prevent the compiler to refetch timer->base so the
check and the a
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