Hoan,
On Wed, 10 Jul 2019, Hoan Tran OS wrote:
> On 6/25/19 3:45 PM, Thomas Gleixner wrote:
> > On Tue, 25 Jun 2019, Hoan Tran OS wrote:
> >> @@ -1567,15 +1567,6 @@ config X86_64_ACPI_NUMA
> >>---help---
> >> Enable ACPI SRAT based node topology detection.
> >>
> >> -# Some NUMA nodes
Hi Tomas,
On Tue, 9 Jul 2019 07:12:34 + "Winkler, Tomas"
wrote:
>
> Actually I've asked Greg this git expertise question: how the
> **exact** conflict resolution is carried between git trees (before it
> is finally resolved in upstream for all.). For next time If anyone
> has the answer, ple
During the review of commit 1ff2f0fa450e ("net/mlx5e: Return in default
case statement in tx_post_resync_params"), Leon and Nick pointed out
that the switch statements can be converted to single if statements
that return early so that the code is easier to follow.
Suggested-by: Leon Romanovsky
Su
On 08/07/2019 16:12, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.4.185 release.
> There are 73 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses sh
On 08/07/2019 16:11, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.9.185 release.
> There are 102 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses s
On 08/07/2019 16:12, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.14.133 release.
> There are 56 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses s
On Tue, 9 Jul 2019, John Stultz wrote:
> Though unfortunately, it seems the arm64 vdso code that just landed is
> breaking AOSP for me.
>
> I see a lot of the following errors:
> 01-01 01:22:14.097 755 755 F libc: Fatal signal 11 (SIGSEGV),
> code 1 (SEGV_MAPERR), fault addr 0x3cf2c96c in
On 08/07/2019 16:12, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.19.58 release.
> There are 90 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses sh
On 08/07/2019 16:12, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 5.1.17 release.
> There are 96 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses sho
Hi Thomas,
On 7/10/19 12:58 PM, Thomas Gleixner wrote:
> Hoan,
>
> On Wed, 10 Jul 2019, Hoan Tran OS wrote:
>> On 6/25/19 3:45 PM, Thomas Gleixner wrote:
>>> On Tue, 25 Jun 2019, Hoan Tran OS wrote:
@@ -1567,15 +1567,6 @@ config X86_64_ACPI_NUMA
---help---
In iw_create_tx_threads(), failure to create kthread
is basic failure, which affect performance only. The
whole kthread creation spam in this driver looked
suspicious during submission and it continues to be.
This patch remove the failed print to fix gcc warning:
drivers/infiniband/sw/siw/siw_main
On 05-07-19, 11:57, Niklas Cassel wrote:
> -static struct platform_driver qcom_cpufreq_kryo_driver = {
> - .probe = qcom_cpufreq_kryo_probe,
> - .remove = qcom_cpufreq_kryo_remove,
> +static struct platform_driver qcom_cpufreq_driver = {
> + .probe = qcom_cpufreq_probe,
> + .remove
On 08/07/19 21:32, Lendacky, Thomas wrote:
>> AMD and Intel both have serializing lfence (X86_FEATURE_LFENCE_RDTSC).
>> They've both had it for a long time, and AMD has had it enabled in Linux
>> since Spectre v1 was announced.
>>
>> Back then, there was a proposal to remove the serializing mfence
Tegra PCIe rootports don't generate MSI interrupts for PME and AER events.
Since PCIe spec (Ref: r4.0 sec 7.7.1.2 and 7.7.2.2) doesn't support using
a mix of INTx and MSI/MSI-X, MSI needs to be disabled to avoid root ports
service drivers registering their respective ISRs with MSI interrupt and
to
Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s
features as defined in PCIe spec r4.0, sec 7.7.4 for Data Link Feature and
sec 7.7.5 for Physical Layer 16.0 GT/s.
Signed-off-by: Vidya Sagar
Reviewed-by: Thierry Reding
---
V13:
* Updated commit message to include referenc
Tegra194 has six PCIe controllers based on Synopsys DesignWare core.
There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO:
Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively.
Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 uses
UPHY lanes from NVH
Some of DesignWare core's DBI registers (a.k.a configuration space
registers) are write-protected with a lock without enabling which they are
read-only by default. These write-protected registers are implementation
specific. Tegra194's BAR-0 register which is at offset 0x10 in the
configuration spa
Move PCIe config space capability search API to common DesignWare file
as this can be used by both host and ep mode codes.
Signed-off-by: Vidya Sagar
Acked-by: Gustavo Pimentel
Reviewed-by: Thierry Reding
---
V13:
* None
V12:
* None
V11:
* None
V10:
* None
V9:
* None
V8:
* Changed comment
[This email was generated by a script. Let me know if you have any suggestions
to make it better, or if you want it re-generated with the latest status.
Note: currently the mm bugs look hard to do anything with and most look
outdated, but I figured I'd send them out just in case someone has an
Add support for Tegra194 PCIe controllers. These controllers are based
on Synopsys DesignWare core IP.
Signed-off-by: Vidya Sagar
Reviewed-by: Rob Herring
Acked-by: Thierry Reding
---
V13:
* None
V12:
* None
V11:
* None
V10:
* None
V9:
* Added Acked-by from Thierry
V8:
* Addressed review c
Add extended configuration space capability search API using struct dw_pcie *
pointer
Signed-off-by: Vidya Sagar
Acked-by: Gustavo Pimentel
Acked-by: Thierry Reding
---
V13:
* None
V12:
* None
V11:
* None
V10:
* None
V9:
* Added Acked-by from Thierry
V8:
* Changed data types of return and
Some host controllers need to know the existence of clkreq signal routing to
downstream devices to be able to advertise low power features like ASPM L1
substates. Without clkreq signal routing being present, enabling ASPM L1 sub
states might lead to downstream devices falling off the bus. Hence a n
Add support to enable CDM (Configuration Dependent Module) registers check
for any data corruption. CDM registers include standard PCIe configuration
space registers, Port Logic registers and iATU and DMA registers.
Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook
Vers
Add support to enable CDM (Configuration Dependent Module) register check
for any data corruption based on the device-tree flag 'snps,enable-cdm-check'.
Signed-off-by: Vidya Sagar
Acked-by: Gustavo Pimentel
Reviewed-by: Thierry Reding
---
V13:
* None
V12:
* None
V11:
* None
V10:
* None
V9:
On Wed, Jul 10, 2019 at 10:26:10AM +0800, Jason Wang wrote:
> On 2019/7/9 下午2:33, Tiwei Bie wrote:
> > On Tue, Jul 09, 2019 at 10:50:38AM +0800, Jason Wang wrote:
> > > On 2019/7/8 下午2:16, Tiwei Bie wrote:
> > > > On Fri, Jul 05, 2019 at 08:49:46AM -0600, Alex Williamson wrote:
> > > > > On Thu, 4
Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC interface
with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module.
For each PCIe lane of a controller, there is a P2U unit instantiated at
hardware level. This driver provides support for the programming required
for each P2
Add support for Tegra194 P2U (PIPE to UPHY) module block which is a glue
module instantiated one for each PCIe lane between Synopsys DesignWare core
based PCIe IP and Universal PHY block.
Signed-off-by: Vidya Sagar
Reviewed-by: Rob Herring
Acked-by: Thierry Reding
Acked-by: Kishon Vijay Abraham
Add support for Synopsys DesignWare core IP based PCIe host controller
present in Tegra194 SoC.
Signed-off-by: Vidya Sagar
Acked-by: Thierry Reding
---
V13:
* Modified according to modifications in PATCH V13 01/12
V12:
* None
V11:
* None
V10:
* Used _relaxed() versions of readl() & writel()
Le 10/07/2019 à 06:54, Ravi Bangoria a écrit :
On Powerpc64, watchpoint match range is double-word granular. On
a watchpoint hit, DAR is set to the first byte of overlap between
actual access and watched range. And thus it's quite possible that
DAR does not point inside user specified range. E
Thanks for review.
On Wed, 10 Jul 2019 at 13:30, Boqun Feng wrote:
>
> On Fri, Jun 28, 2019 at 05:15:28PM +0800, Yuyang Du wrote:
> > We have a lockdep warning:
> >
> >
> > WARNING: possible irq lock inversion dependency detected
> >
On 05-07-19, 11:57, Niklas Cassel wrote:
> + drv->opp_tables = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables),
> + GFP_KERNEL);
> + if (!drv->opp_tables) {
> + ret = -ENOMEM;
> + goto free_drv;
> + }
>
> for_each_possi
On 08/07/19 09:07, Jing Liu wrote:
>>
> And when adding subleaf 1, plan to add codes,
>
> case 1:
> entry->eax |= kvm_cpuid_7_1_eax_x86_features;
> entry->ebx = entry->ecx = entry->edx =0;
> break;
>
> What do you think?
This should be "&=", not "|=". Otherwise yes, that's the idea.
On 08/07/19 09:09, Jing Liu wrote:
> It seems the two func are introduced by 2b5e97e, as paravirtual cpuid.
> But when searching KVM_CPUID_SIGNATURE, there seems no caller requesting
> this cpuid. Meanwhile, I felt curious if KVM_CPUID_FEATURES is still in
> use but it seems kvm_update_cpuid() uses
On 7/10/19 11:57 AM, Christophe Leroy wrote:
>
>
> Le 10/07/2019 à 06:54, Ravi Bangoria a écrit :
>> On Powerpc64, watchpoint match range is double-word granular. On
>> a watchpoint hit, DAR is set to the first byte of overlap between
>> actual access and watched range. And thus it's quite poss
Signed-off-by: Kirill Marinushkin
---
MAINTAINERS| 2 +-
sound/soc/codecs/pcm3060-i2c.c | 4 ++--
sound/soc/codecs/pcm3060-spi.c | 4 ++--
sound/soc/codecs/pcm3060.c | 4 ++--
sound/soc/codecs/pcm3060.h | 2 +-
5 files changed, 8 insertions(+), 8 deletions(-)
diff --g
Hi, Rob,
Sorry to bother you, could you please review this patch when you are
available? Thanks.
On Mon, 2019-07-01 at 15:48 +0800, Bibby Hsieh wrote:
> cmdq driver provide a function that get the relationship
> of sub system number from device node for client.
> add specification for #subsys-ce
From: Anson Huang
Enable i.MX8MM cpu-idle using generic ARM cpu-idle driver, 2 states
are supported, details as below:
root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/name
WFI
root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/usage
3973
root@imx8mmevk:~# cat /sy
From: Anson Huang
ARCH_MXC platforms needs system counter as broadcast timer
to support cpuidle, enable it by default.
Signed-off-by: Anson Huang
---
New patch, now that system counter driver lands in main line, we can enable it
by default.
---
arch/arm64/Kconfig.platforms | 1 +
1 file chang
From: Anson Huang
The system counter block guide states that the base clock is
internally divided by 3 before use, that means the clock input of
system counter defined in DT should be base clock which is normally
from OSC, and then internally divided by 3 before use.
Signed-off-by: Anson Huang
From: Anson Huang
Add i.MX8MQ system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang
---
Changes since V4:
- update the clock info using fixed clock node;
- correct the reg range;
- update the interrupt number as the system coun
From: Anson Huang
Add i.MX8MM system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang
---
Changes since V4:
- update the clock info using fixed clock node;
- correct the reg range;
- update the interrupt number as the system coun
On 09.07.19 14:25, Denis Efremov wrote:
> The function ap_query_configuration is declared static and marked
> EXPORT_SYMBOL, which is at best an odd combination. Because the
> function is not used outside of the drivers/s390/crypto/ap_bus.c
> file it is defined in, this commit removes the EXPORT_SY
On Wed, Jul 10, 2019 at 2:22 AM Chuanhong Guo wrote:
>
> This commit adds device-tree node for mt7621-pll and use its clock
> accordingly.
>
> Signed-off-by: Chuanhong Guo
Oops. Please ignore this single patch for now. I forgot to drop
cpuclock node in drivers/staging/mt7621-dts/gbpc1.dts
I'll r
On 09.07.2019 20:08, Luis de Oliveira wrote:
>
> Hi Eugen,
>
>
> From: eugen.hris...@microchip.com
> Date: Tue, Jul 09, 2019 at 15:33:50
>
>>
>>
>> On 11.06.2019 22:20, Luis Oliveira wrote:
>>> From: Luis Oliveira
>>>
>>> Add bindings for Synopsys DesignWare MIPI CSI-2 host.
>>>
>>> Signed
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